Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_tmu_dim_relgen.v

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// 
// OpenSPARC T2 Processor File: dmu_tmu_dim_relgen.v
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module dmu_tmu_dim_relgen (
				clk,
				rst_l,	

				// ILU interface
				k2y_rel_rcd,
				k2y_rel_enq,

				// talk to diufsm.v
                                rcd_is_cpld_reg,

				// talk to datapath.v
				k2y_buf_addr );
  
  //synopsys sync_set_reset "rst_l"

  // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<  

  //------------------------------------------------------------------------
  //  Clock and Reset Signals
  //------------------------------------------------------------------------
  input		  clk;		    
  input		  rst_l;

  //------------------------------------------------------------------------
  //   ILU interface
  //------------------------------------------------------------------------
  output [`FIRE_DLC_URR_REC_WDTH-1:0]  k2y_rel_rcd;         // ingress release rcd
  output                               k2y_rel_enq;         // ingress enqueue
  
  //------------------------------------------------------------------------
  //   talk to diufsm.v
  //------------------------------------------------------------------------
  input 	    rcd_is_cpld_reg;      // from diufsm.v
 
  //------------------------------------------------------------------------
  //   talk to datapath.v
  //------------------------------------------------------------------------
  input [`FIRE_DLC_ITI_ADDR_WDTH-1:0] k2y_buf_addr;
    
  // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<

  // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  reg [`FIRE_DLC_ITI_ADDR_WDTH-1:0]   pre_k2y_buf_addr;

  reg [`FIRE_DLC_URR_REC_WDTH-1:0]  k2y_rel_rcd;         // ingress release rcd
  reg                               k2y_rel_enq; 
  
  // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~

  // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  wire 			    rcd_type; // 0 - pio (CPLD), 1 - dma (PD)
  wire 			    n_k2y_rel_enq;
  wire [`FIRE_DLC_URR_REC_WDTH-1:0] n_k2y_rel_rcd;

  
  // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<

  //---------------------------------------------------------------------
  // outputs
  //---------------------------------------------------------------------
  assign rcd_type = rcd_is_cpld_reg ? 1'b0 : 1'b1;
  assign n_k2y_rel_rcd = {rcd_type, pre_k2y_buf_addr};
  assign n_k2y_rel_enq = pre_k2y_buf_addr[0] ^ k2y_buf_addr[0];

  always @ (posedge clk)
    if (~rst_l) begin
      k2y_rel_enq <= 1'b0;
      k2y_rel_rcd <= {`FIRE_DLC_URR_REC_WDTH{1'b0}};
	end
    else begin
      k2y_rel_enq <= n_k2y_rel_enq;
      k2y_rel_rcd <= n_k2y_rel_rcd;
    end

  //---------------------------------------------------------------------
  // flop lsb_k2y_buf_addr
  //---------------------------------------------------------------------
  always @ (posedge clk)
	if(~rst_l) begin
      pre_k2y_buf_addr <= {`FIRE_DLC_ITI_ADDR_WDTH{1'b0}};
	end
    else begin
      pre_k2y_buf_addr <= k2y_buf_addr;
    end 
  
  // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

endmodule // dmu_tmu_dim_relgen