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// OpenSPARC T2 Processor File: dmu_tmu_dim_relgen.v
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// ========== Copyright Header End ============================================
module dmu_tmu_dim_relgen (
//synopsys sync_set_reset "rst_l"
// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//------------------------------------------------------------------------
// Clock and Reset Signals
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//------------------------------------------------------------------------
output [`FIRE_DLC_URR_REC_WDTH-1:0] k2y_rel_rcd; // ingress release rcd
output k2y_rel_enq; // ingress enqueue
//------------------------------------------------------------------------
//------------------------------------------------------------------------
input rcd_is_cpld_reg; // from diufsm.v
//------------------------------------------------------------------------
//------------------------------------------------------------------------
input [`FIRE_DLC_ITI_ADDR_WDTH-1:0] k2y_buf_addr;
// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
reg [`FIRE_DLC_ITI_ADDR_WDTH-1:0] pre_k2y_buf_addr;
reg [`FIRE_DLC_URR_REC_WDTH-1:0] k2y_rel_rcd; // ingress release rcd
// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~
// ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire rcd_type; // 0 - pio (CPLD), 1 - dma (PD)
wire [`FIRE_DLC_URR_REC_WDTH-1:0] n_k2y_rel_rcd;
// >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<
//---------------------------------------------------------------------
//---------------------------------------------------------------------
assign rcd_type = rcd_is_cpld_reg ? 1'b0 : 1'b1;
assign n_k2y_rel_rcd = {rcd_type, pre_k2y_buf_addr};
assign n_k2y_rel_enq = pre_k2y_buf_addr[0] ^ k2y_buf_addr[0];
k2y_rel_rcd <= {`FIRE_DLC_URR_REC_WDTH{1'b0}};
k2y_rel_enq <= n_k2y_rel_enq;
k2y_rel_rcd <= n_k2y_rel_rcd;
//---------------------------------------------------------------------
//---------------------------------------------------------------------
pre_k2y_buf_addr <= {`FIRE_DLC_ITI_ADDR_WDTH{1'b0}};
pre_k2y_buf_addr <= k2y_buf_addr;
// >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
endmodule // dmu_tmu_dim_relgen