Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / mac / synopsys / script / user_cfg.scr

source -echo -verbose $dv_root/design/sys/synopsys/script/project_io_cfg.scr

set rtl_files {\
libs/cl/cl_rtl_ext.v
libs/cl/cl_a1/cl_a1.behV
libs/cl/cl_u1/cl_u1.behV
libs/cl/cl_dp1/cl_dp1.behV
libs/cl/cl_sc1/cl_sc1.behV
libs/cl/cl_mc1/cl_mc1.v

libs/clk/rtl/clkgen_mac_io.v

libs/clk/n2_clk_pgrid_cust_l/n2_clk_mac_io_cust/rtl/n2_clk_mac_io_cust.v
libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v

design/sys/iop/niu/rtl/df1.v \
design/sys/iop/niu/rtl/dffe.v \
design/sys/iop/niu/rtl/dffr.v \
design/sys/iop/niu/rtl/dffre.v \

design/sys/iop/mac/rtl/mac.v \
design/sys/iop/niu/rtl/xmac.h \
design/sys/iop/niu/rtl/mif.h \
design/sys/iop/niu/rtl/pcs_define.h \
design/sys/iop/niu/rtl/mac_core.v \
design/sys/iop/niu/rtl/n2_txd_blatch.v \
design/sys/iop/niu/rtl/n2_rxd_alatch.v \
design/sys/iop/niu/rtl/mac_2ports.v \
design/sys/iop/niu/rtl/sphy_dpath2.v \
design/sys/iop/niu/rtl/esr_ctl2.v \
design/sys/iop/niu/rtl/clkgen_mac.v \
design/sys/iop/niu/rtl/phy_clock_2ports.v \
design/sys/iop/niu/rtl/mac_pio_intf.v \
design/sys/iop/niu/rtl/mac_clk_driver.v \
design/sys/iop/niu/rtl/xmac_2pcs_core.v \
design/sys/iop/niu/rtl/esr_bscan.v \
design/sys/iop/niu/rtl/mac_reset_hdr.v \
design/sys/iop/niu/rtl/phy_dpath.v \
design/sys/iop/niu/rtl/mif.v \
design/sys/iop/niu/rtl/mif_control_sm.v \
design/sys/iop/niu/rtl/mif_exec_sm.v \
design/sys/iop/niu/rtl/lib.v \
design/sys/iop/niu/rtl/xmac_2pcs_clk_mux.v \
design/sys/iop/niu/rtl/rgmii_clk_gen.v \
design/sys/iop/niu/rtl/xmac.h
design/sys/iop/niu/rtl/lfs.v \
design/sys/iop/niu/rtl/lfs_sm.v \
design/sys/iop/niu/rtl/address_decoder.v \
design/sys/iop/niu/rtl/xrlm_sm.v \
design/sys/iop/niu/rtl/rx_xdecap.v \
design/sys/iop/niu/rtl/xmac_fcs.v \
design/sys/iop/niu/rtl/crc_gen_xmii.v \
design/sys/iop/niu/rtl/rx_xmac.v \
design/sys/iop/niu/rtl/rx_xgmii_intf.v \
design/sys/iop/niu/rtl/sop_sm.v \
design/sys/iop/niu/rtl/rxfifo_load.v \
design/sys/iop/niu/rtl/srfifo_load.v \
design/sys/iop/niu/rtl/rxfifo_unload.v \
design/sys/iop/niu/rtl/xmac_slv.v \
design/sys/iop/niu/rtl/xmac_sync.v \
design/sys/iop/niu/rtl/xdeferral.v \
design/sys/iop/niu/rtl/xtlm_sm.v \
design/sys/iop/niu/rtl/txfifo_unload.v \
design/sys/iop/niu/rtl/txfifo_load.v \
design/sys/iop/niu/rtl/tx_xmac.v \
design/sys/iop/niu/rtl/tx_byte_counter.v \
design/sys/iop/niu/rtl/ipg_checker.v \
design/sys/iop/niu/rtl/tx_mii_gmii.v \
design/sys/iop/niu/rtl/rx_mii_gmii.v \
design/sys/iop/niu/rtl/mgrlm_sm.v \
design/sys/iop/niu/rtl/xmac.v \
design/sys/iop/niu/rtl/xpcs_define.v \
design/sys/iop/niu/rtl/xpcs.v \
design/sys/iop/niu/rtl/xpcs_dbg.v \
design/sys/iop/niu/rtl/xpcs_xgmii_dpath.v \
design/sys/iop/niu/rtl/xpcs_FD1.v \
design/sys/iop/niu/rtl/xpcs_SYNC_CELL.v \
design/sys/iop/niu/rtl/xpcs_dpath.v \
design/sys/iop/niu/rtl/xpcs_pio.v \
design/sys/iop/niu/rtl/xpcs_sync.v \
design/sys/iop/niu/rtl/xpcs_rx.v \
design/sys/iop/niu/rtl/xpcs_tx_del.v \
design/sys/iop/niu/rtl/xpcs_tx_randomizer.v \
design/sys/iop/niu/rtl/xpcs_tx.v \
design/sys/iop/niu/rtl/xpcs_DEL05.v \
design/sys/iop/niu/rtl/xpcs_txio.v \
design/sys/iop/niu/rtl/xpcs_txio_pcs.v \
design/sys/iop/niu/rtl/xpcs_rxio.v \
design/sys/iop/niu/rtl/xpcs_rxio_ebuffer.v \
design/sys/iop/niu/rtl/xpcs_rxio_ebuffer_sm.v \
design/sys/iop/niu/rtl/xpcs_rxio_sync.v \
design/sys/iop/niu/rtl/xpcs_rxio_sync_decoder.v \
design/sys/iop/niu/rtl/xpcs_rxio_sync_deskew_fifo.v \
design/sys/iop/niu/rtl/xpcs_rxio_sync_fifo_ptr.v \
design/sys/iop/niu/rtl/xpcs_rxio_sync_sm.v \
design/sys/iop/niu/rtl/pcs.v \
design/sys/iop/niu/rtl/pcs_decoder.v \
design/sys/iop/niu/rtl/pcs_encoder.v \
design/sys/iop/niu/rtl/pcs_lfsr.v \
design/sys/iop/niu/rtl/pcs_link_config.v \
design/sys/iop/niu/rtl/pcs_rx_ctrl.v \
design/sys/iop/niu/rtl/pcs_rx_disparity.v \
design/sys/iop/niu/rtl/pcs_rx_dpath.v \
design/sys/iop/niu/rtl/pcs_sequence_detect.v \
design/sys/iop/niu/rtl/pcs_slave.v \
design/sys/iop/niu/rtl/pcs_tx_ctrl.v \
design/sys/iop/niu/rtl/pcs_tx_disparity.v \
design/sys/iop/niu/rtl/pcs_tx_dpath.v \

design/sys/iop/niu/rtl/niu_dff.v \
design/sys/iop/niu/rtl/make_b8_macro.v \
design/sys/iop/niu/rtl/hedwig.v \
design/sys/iop/niu/rtl/MDIO2P_IO.v \
design/sys/iop/niu/rtl/P2REGS.v \
design/sys/iop/niu/rtl/P2REGS_CFG_STS.v \
design/sys/iop/niu/rtl/MDIO_TO_REGS.v \
design/sys/iop/niu/rtl/MDIO2P.v \
design/sys/iop/niu/rtl/MDIO2P_FRMR.v \
design/sys/iop/niu/rtl/MDIO2P_REGS.v \
}

set link_library [concat $link_library \
   dw_foundation.sldb \
]


set mix_files {}
set top_module mac

set include_paths {\
}

set black_box_libs {}
set black_box_designs {}
set mem_libs {}

set dont_touch_modules {\
}

set compile_effort   "medium"

set compile_flatten_all 1

set compile_no_new_cells_at_top_level false

set default_clk cmp_gclk_c1_mac
set default_clk_freq  1500
set default_setup_skew  0.0
set default_hold_skew  0.0
set default_clk_transition  0.05
set clk_list {                        \
                { cmp_gclk_c1_mac    1500.0   0.000   0.000   0.05}        \
}

set ideal_net_list {}
set false_path_list {}
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set skip_scan            0
set add_lockup_latch     false
set chain_count          1
set scanin_port_list     {}
set scanout_port_list    {}
set scanenable_port      global_shift_enable
set has_test_stub        1
set scanenable_pin       test_stub_no_bist/se
set long_chain_so_0_net  long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set so_0_net             so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}