[OpenSPARC-T2-DV] / design / sys / iop / ncu / rtl / ncu_ssiui4_ctl.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ncu_ssiui4_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`define UCB_BUS_WIDTH 4
`define UCB_BUS_WIDTH_M1 3
`define CYC_NUM 32
`define CYC_NUM_M1 31

module ncu_ssiui4_ctl (
  iol2clk, 
  scan_in, 
  scan_out, 
  tcu_pce_ov, 
  tcu_clk_stop, 
  tcu_scan_en, 
  tcu_aclk, 
  tcu_bclk, 
  vld, 
  data, 
  stall, 
  indata_buf_vld, 
  indata_buf, 
  stall_a1) ;
wire stall_d1_n;
wire stall_d1;
wire vld_d1_ff_scanin;
wire vld_d1_ff_scanout;
wire vld_d1;
wire l1clk;
wire data_d1_ff_scanin;
wire data_d1_ff_scanout;
wire [3:0] data_d1;
wire stall_ff_scanin;
wire stall_ff_scanout;
wire stall_d1_ff_scanin;
wire stall_d1_ff_scanout;
wire skid_buf0_en;
wire vld_buf0_ff_scanin;
wire vld_buf0_ff_scanout;
wire vld_buf0;
wire data_buf0_ff_scanin;
wire data_buf0_ff_scanout;
wire [3:0] data_buf0;
wire skid_buf1_en_ff_scanin;
wire skid_buf1_en_ff_scanout;
wire skid_buf1_en;
wire vld_buf1_ff_scanin;
wire vld_buf1_ff_scanout;
wire vld_buf1;
wire data_buf1_ff_scanin;
wire data_buf1_ff_scanout;
wire [3:0] data_buf1;
wire skid_buf0_sel;
wire skid_buf1_sel_ff_scanin;
wire skid_buf1_sel_ff_scanout;
wire skid_buf1_sel;
wire vld_mux;
wire [3:0] data_mux;
wire [31:0] indata_vec_next;
wire [31:0] indata_vec;
wire stall_a1_n;
wire indata_vec_ff_scanin;
wire indata_vec_ff_scanout;
wire [127:0] indata_buf_next;
wire indata_buf_ff_scanin;
wire indata_buf_ff_scanout;
wire indata_vec0_d1_ff_scanin;
wire indata_vec0_d1_ff_scanout;
wire indata_vec0_d1;
wire siclk;
wire soclk;
wire se;
wire pce_ov;
wire stop;


////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input		iol2clk;
input		scan_in;
output		scan_out;
input		tcu_pce_ov;
input		tcu_clk_stop;
input		tcu_scan_en;
input		tcu_aclk;
input		tcu_bclk;

// UCB bus interface
input		vld;
input [`UCB_BUS_WIDTH_M1 :0]	data;
output		stall;


// Local interface
output		indata_buf_vld;
output [127:0]	indata_buf;
input		stall_a1;


// Internal signals


////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/************************************************************
 * UCB bus interface flops
 * This is to make signals going between IOB and UCB flop-to-flop
 * to improve timing.
 ************************************************************/
assign stall_d1_n = ~stall_d1;
ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 vld_d1_ff  
				(
				.scan_in(vld_d1_ff_scanin),
				.scan_out(vld_d1_ff_scanout),
				.dout		(vld_d1),
				.l1clk		(l1clk),
				.en		(stall_d1_n),
				.din		(vld),
  .siclk(siclk),
  .soclk(soclk)
				);

ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_4 data_d1_ff  
				(
				.scan_in(data_d1_ff_scanin),
				.scan_out(data_d1_ff_scanout),
				.dout		(data_d1[`UCB_BUS_WIDTH_M1:0]),
				.l1clk		(l1clk),
				.en		(stall_d1_n),
				.din		(data[`UCB_BUS_WIDTH_M1:0]),
  .siclk(siclk),
  .soclk(soclk)
				);

ncu_ssiui4_ctl_msff_ctl_macro__width_1 stall_ff 
				(
				.scan_in(stall_ff_scanin),
				.scan_out(stall_ff_scanout),
				.dout		(stall),
				.l1clk		(l1clk),
				.din		(stall_a1),
  .siclk(siclk),
  .soclk(soclk)
				);

ncu_ssiui4_ctl_msff_ctl_macro__width_1 stall_d1_ff 
				(
				.scan_in(stall_d1_ff_scanin),
				.scan_out(stall_d1_ff_scanout),
				.dout		(stall_d1),
				.l1clk		(l1clk),
				.din		(stall),
  .siclk(siclk),
  .soclk(soclk)
				);


/************************************************************
 * Skid buffer
 * We need a two deep skid buffer to handle stalling.
 ************************************************************/
// Assertion: stall has to be deasserted for more than 1 cycle
//            ie time between two separate stalls has to be
//            at least two cycles.  Otherwise, contents from
//            skid buffer will be lost.

// Buffer 0
assign  skid_buf0_en = stall_a1 & ~stall;

ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 vld_buf0_ff  
				(
				.scan_in(vld_buf0_ff_scanin),
				.scan_out(vld_buf0_ff_scanout),
				.dout		(vld_buf0),
				.l1clk		(l1clk),
				.en		(skid_buf0_en),
				.din		(vld_d1),
  .siclk(siclk),
  .soclk(soclk)
				);

ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_4 data_buf0_ff   
				(
				.scan_in(data_buf0_ff_scanin),
				.scan_out(data_buf0_ff_scanout),
				.dout		(data_buf0[`UCB_BUS_WIDTH_M1 :0]),
				.l1clk		(l1clk),
				.en		(skid_buf0_en),
				.din		(data_d1[`UCB_BUS_WIDTH_M1 :0]),
  .siclk(siclk),
  .soclk(soclk)
				);

// Buffer 1
ncu_ssiui4_ctl_msff_ctl_macro__width_1 skid_buf1_en_ff 
				(
				.scan_in(skid_buf1_en_ff_scanin),
				.scan_out(skid_buf1_en_ff_scanout),
				.dout		(skid_buf1_en),
				.l1clk		(l1clk),
				.din		(skid_buf0_en),
  .siclk(siclk),
  .soclk(soclk)
				);

ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 vld_buf1_ff  
				(
				.scan_in(vld_buf1_ff_scanin),
				.scan_out(vld_buf1_ff_scanout),
				.dout		(vld_buf1),
				.l1clk		(l1clk),
				.en		(skid_buf1_en),
				.din		(vld_d1),
  .siclk(siclk),
  .soclk(soclk)
				);

ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_4 data_buf1_ff   
				(
				.scan_in(data_buf1_ff_scanin),
				.scan_out(data_buf1_ff_scanout),
				.dout		(data_buf1[`UCB_BUS_WIDTH_M1 :0]),
				.l1clk		(l1clk),
				.en		(skid_buf1_en),
				.din		(data_d1[`UCB_BUS_WIDTH_M1 :0]),
  .siclk(siclk),
  .soclk(soclk)
				);


/************************************************************
 * Mux between skid buffer and interface flop
 ************************************************************/
// Assertion: stall has to be deasserted for more than 1 cycle
//            ie time between two separate stalls has to be
//            at least two cycles.  Otherwise, contents from
//            skid buffer will be lost.

assign	skid_buf0_sel = ~stall_a1 & stall;

ncu_ssiui4_ctl_msff_ctl_macro__width_1 skid_buf1_sel_ff 
				(
				.scan_in(skid_buf1_sel_ff_scanin),
				.scan_out(skid_buf1_sel_ff_scanout),
				.dout		(skid_buf1_sel),
				.l1clk		(l1clk),
				.din		(skid_buf0_sel),
  .siclk(siclk),
  .soclk(soclk)
				);

assign	vld_mux = skid_buf0_sel ? vld_buf0 : 
	   	     skid_buf1_sel ? vld_buf1 :
		                     vld_d1;

assign	data_mux[`UCB_BUS_WIDTH_M1 :0] = skid_buf0_sel ? data_buf0[`UCB_BUS_WIDTH_M1 :0] : 
					skid_buf1_sel ? data_buf1[`UCB_BUS_WIDTH_M1 :0] : 
					       		 data_d1[`UCB_BUS_WIDTH_M1 :0];


/************************************************************
 * Assemble inbound data
 ************************************************************/
// valid vector
assign	indata_vec_next[`CYC_NUM_M1:0] = {vld_mux, indata_vec[`CYC_NUM_M1 :1]};

assign	stall_a1_n = ~stall_a1;
ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_32 indata_vec_ff   
				(
				.scan_in(indata_vec_ff_scanin),
				.scan_out(indata_vec_ff_scanout),
				.dout		(indata_vec[`CYC_NUM_M1 :0]),
				.l1clk		(l1clk),
				.en		(stall_a1_n),
				.din		(indata_vec_next[`CYC_NUM_M1 :0]),
  .siclk(siclk),
  .soclk(soclk)
				);

// data buffer
assign	indata_buf_next[127:0] = {data_mux[`UCB_BUS_WIDTH_M1 :0], indata_buf[127:`UCB_BUS_WIDTH ]};
ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_128 indata_buf_ff  
				(
				.scan_in(indata_buf_ff_scanin),
				.scan_out(indata_buf_ff_scanout),
				.dout		(indata_buf[127:0]),
				.l1clk		(l1clk),
				.en		(stall_a1_n),
				.din		(indata_buf_next[127:0]),
  .siclk(siclk),
  .soclk(soclk)
				);

// detect a new packet	  
ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 indata_vec0_d1_ff  
				(
				.scan_in(indata_vec0_d1_ff_scanin),
				.scan_out(indata_vec0_d1_ff_scanout),
				.dout		(indata_vec0_d1),
				.l1clk		(l1clk),
				.en		(stall_a1_n),
				.din		(indata_vec[0]),
  .siclk(siclk),
  .soclk(soclk)
				);

assign	indata_buf_vld = indata_vec[0] & ~indata_vec0_d1;


/**** adding clock header ****/
ncu_ssiui4_ctl_l1clkhdr_ctl_macro clkgen (
				.l2clk	(iol2clk),
				.l1en	(1'b1),
				.l1clk	(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
				);

/*** building tcu port ***/
assign	siclk = tcu_aclk;
assign	soclk = tcu_bclk;
assign	   se = tcu_scan_en;
assign	pce_ov = tcu_pce_ov;
assign	stop = tcu_clk_stop;

// fixscan start:
assign vld_d1_ff_scanin          = scan_in                  ;
assign data_d1_ff_scanin         = vld_d1_ff_scanout        ;
assign stall_ff_scanin           = data_d1_ff_scanout       ;
assign stall_d1_ff_scanin        = stall_ff_scanout         ;
assign vld_buf0_ff_scanin        = stall_d1_ff_scanout      ;
assign data_buf0_ff_scanin       = vld_buf0_ff_scanout      ;
assign skid_buf1_en_ff_scanin    = data_buf0_ff_scanout     ;
assign vld_buf1_ff_scanin        = skid_buf1_en_ff_scanout  ;
assign data_buf1_ff_scanin       = vld_buf1_ff_scanout      ;
assign skid_buf1_sel_ff_scanin   = data_buf1_ff_scanout     ;
assign indata_vec_ff_scanin      = skid_buf1_sel_ff_scanout ;
assign indata_buf_ff_scanin      = indata_vec_ff_scanout    ;
assign indata_vec0_d1_ff_scanin  = indata_buf_ff_scanout    ;
assign scan_out                  = indata_vec0_d1_ff_scanout;
// fixscan end:
endmodule // ucb_bus_in


// any PARAMS parms go into naming of macro

module ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_4 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}});


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_ssiui4_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_32 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [31:0] fdin;
wire [30:0] so;

  input [31:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [31:0] dout;
  output scan_out;
assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}});


dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_128 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [127:0] fdin;
wire [126:0] so;

  input [127:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [127:0] dout;
  output scan_out;
assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}});


dff #(128)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[127:0]),
.si({scan_in,so[126:0]}),
.so({so[126:0],scan_out}),
.q(dout[127:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_ssiui4_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: ncu_ssiui4_ctl.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	`define UCB_BUS_WIDTH 4
	36	`define UCB_BUS_WIDTH_M1 3
	37	`define CYC_NUM 32
	38	`define CYC_NUM_M1 31
	39
	40	module ncu_ssiui4_ctl (
	41	iol2clk,
	42	scan_in,
	43	scan_out,
	44	tcu_pce_ov,
	45	tcu_clk_stop,
	46	tcu_scan_en,
	47	tcu_aclk,
	48	tcu_bclk,
	49	vld,
	50	data,
	51	stall,
	52	indata_buf_vld,
	53	indata_buf,
	54	stall_a1) ;
	55	wire stall_d1_n;
	56	wire stall_d1;
	57	wire vld_d1_ff_scanin;
	58	wire vld_d1_ff_scanout;
	59	wire vld_d1;
	60	wire l1clk;
	61	wire data_d1_ff_scanin;
	62	wire data_d1_ff_scanout;
	63	wire [3:0] data_d1;
	64	wire stall_ff_scanin;
65	wire stall_ff_scanout;
66	wire stall_d1_ff_scanin;
67	wire stall_d1_ff_scanout;
68	wire skid_buf0_en;
69	wire vld_buf0_ff_scanin;
70	wire vld_buf0_ff_scanout;
71	wire vld_buf0;
72	wire data_buf0_ff_scanin;
73	wire data_buf0_ff_scanout;
74	wire [3:0] data_buf0;
75	wire skid_buf1_en_ff_scanin;
76	wire skid_buf1_en_ff_scanout;
77	wire skid_buf1_en;
78	wire vld_buf1_ff_scanin;
79	wire vld_buf1_ff_scanout;
80	wire vld_buf1;
81	wire data_buf1_ff_scanin;
82	wire data_buf1_ff_scanout;
83	wire [3:0] data_buf1;
84	wire skid_buf0_sel;
85	wire skid_buf1_sel_ff_scanin;
86	wire skid_buf1_sel_ff_scanout;
87	wire skid_buf1_sel;
88	wire vld_mux;
89	wire [3:0] data_mux;
90	wire [31:0] indata_vec_next;
91	wire [31:0] indata_vec;
92	wire stall_a1_n;
93	wire indata_vec_ff_scanin;
94	wire indata_vec_ff_scanout;
95	wire [127:0] indata_buf_next;
96	wire indata_buf_ff_scanin;
97	wire indata_buf_ff_scanout;
98	wire indata_vec0_d1_ff_scanin;
99	wire indata_vec0_d1_ff_scanout;
100	wire indata_vec0_d1;
101	wire siclk;
102	wire soclk;
103	wire se;
104	wire pce_ov;
105	wire stop;
106
107
108	////////////////////////////////////////////////////////////////////////
109	// Signal declarations
110	////////////////////////////////////////////////////////////////////////
111	// Global interface
112	input iol2clk;
113	input scan_in;
114	output scan_out;
115	input tcu_pce_ov;
116	input tcu_clk_stop;
117	input tcu_scan_en;
118	input tcu_aclk;
119	input tcu_bclk;
120
121	// UCB bus interface
122	input vld;
123	input [`UCB_BUS_WIDTH_M1 :0] data;
124	output stall;
125
126
127	// Local interface
128	output indata_buf_vld;
129	output [127:0] indata_buf;
130	input stall_a1;
131
132
133	// Internal signals
134
135
136	////////////////////////////////////////////////////////////////////////
137	// Code starts here
138	////////////////////////////////////////////////////////////////////////
139	/************************************************************
140	* UCB bus interface flops
141	* This is to make signals going between IOB and UCB flop-to-flop
142	* to improve timing.
143	************************************************************/
144	assign stall_d1_n = ~stall_d1;
145	ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 vld_d1_ff
146	(
147	.scan_in(vld_d1_ff_scanin),
148	.scan_out(vld_d1_ff_scanout),
149	.dout (vld_d1),
150	.l1clk (l1clk),
151	.en (stall_d1_n),
152	.din (vld),
153	.siclk(siclk),
154	.soclk(soclk)
155	);
156
157	ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_4 data_d1_ff
158	(
159	.scan_in(data_d1_ff_scanin),
160	.scan_out(data_d1_ff_scanout),
161	.dout (data_d1[`UCB_BUS_WIDTH_M1:0]),
162	.l1clk (l1clk),
163	.en (stall_d1_n),
164	.din (data[`UCB_BUS_WIDTH_M1:0]),
165	.siclk(siclk),
166	.soclk(soclk)
167	);
168
169	ncu_ssiui4_ctl_msff_ctl_macro__width_1 stall_ff
170	(
171	.scan_in(stall_ff_scanin),
172	.scan_out(stall_ff_scanout),
173	.dout (stall),
174	.l1clk (l1clk),
175	.din (stall_a1),
176	.siclk(siclk),
177	.soclk(soclk)
178	);
179
180	ncu_ssiui4_ctl_msff_ctl_macro__width_1 stall_d1_ff
181	(
182	.scan_in(stall_d1_ff_scanin),
183	.scan_out(stall_d1_ff_scanout),
184	.dout (stall_d1),
185	.l1clk (l1clk),
186	.din (stall),
187	.siclk(siclk),
188	.soclk(soclk)
189	);
190
191
192	/************************************************************
193	* Skid buffer
194	* We need a two deep skid buffer to handle stalling.
195	************************************************************/
196	// Assertion: stall has to be deasserted for more than 1 cycle
197	// ie time between two separate stalls has to be
198	// at least two cycles. Otherwise, contents from
199	// skid buffer will be lost.
200
201	// Buffer 0
202	assign skid_buf0_en = stall_a1 & ~stall;
203
204	ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 vld_buf0_ff
205	(
206	.scan_in(vld_buf0_ff_scanin),
207	.scan_out(vld_buf0_ff_scanout),
208	.dout (vld_buf0),
209	.l1clk (l1clk),
210	.en (skid_buf0_en),
211	.din (vld_d1),
212	.siclk(siclk),
213	.soclk(soclk)
214	);
215
216	ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_4 data_buf0_ff
217	(
218	.scan_in(data_buf0_ff_scanin),
219	.scan_out(data_buf0_ff_scanout),
220	.dout (data_buf0[`UCB_BUS_WIDTH_M1 :0]),
221	.l1clk (l1clk),
222	.en (skid_buf0_en),
223	.din (data_d1[`UCB_BUS_WIDTH_M1 :0]),
224	.siclk(siclk),
225	.soclk(soclk)
226	);
227
228	// Buffer 1
229	ncu_ssiui4_ctl_msff_ctl_macro__width_1 skid_buf1_en_ff
230	(
231	.scan_in(skid_buf1_en_ff_scanin),
232	.scan_out(skid_buf1_en_ff_scanout),
233	.dout (skid_buf1_en),
234	.l1clk (l1clk),
235	.din (skid_buf0_en),
236	.siclk(siclk),
237	.soclk(soclk)
238	);
239
240	ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 vld_buf1_ff
241	(
242	.scan_in(vld_buf1_ff_scanin),
243	.scan_out(vld_buf1_ff_scanout),
244	.dout (vld_buf1),
245	.l1clk (l1clk),
246	.en (skid_buf1_en),
247	.din (vld_d1),
248	.siclk(siclk),
249	.soclk(soclk)
250	);
251
252	ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_4 data_buf1_ff
253	(
254	.scan_in(data_buf1_ff_scanin),
255	.scan_out(data_buf1_ff_scanout),
256	.dout (data_buf1[`UCB_BUS_WIDTH_M1 :0]),
257	.l1clk (l1clk),
258	.en (skid_buf1_en),
259	.din (data_d1[`UCB_BUS_WIDTH_M1 :0]),
260	.siclk(siclk),
261	.soclk(soclk)
262	);
263
264
265	/************************************************************
266	* Mux between skid buffer and interface flop
267	************************************************************/
268	// Assertion: stall has to be deasserted for more than 1 cycle
269	// ie time between two separate stalls has to be
270	// at least two cycles. Otherwise, contents from
271	// skid buffer will be lost.
272
273	assign skid_buf0_sel = ~stall_a1 & stall;
274
275	ncu_ssiui4_ctl_msff_ctl_macro__width_1 skid_buf1_sel_ff
276	(
277	.scan_in(skid_buf1_sel_ff_scanin),
278	.scan_out(skid_buf1_sel_ff_scanout),
279	.dout (skid_buf1_sel),
280	.l1clk (l1clk),
281	.din (skid_buf0_sel),
282	.siclk(siclk),
283	.soclk(soclk)
284	);
285
286	assign vld_mux = skid_buf0_sel ? vld_buf0 :
287	skid_buf1_sel ? vld_buf1 :
288	vld_d1;
289
290	assign data_mux[`UCB_BUS_WIDTH_M1 :0] = skid_buf0_sel ? data_buf0[`UCB_BUS_WIDTH_M1 :0] :
291	skid_buf1_sel ? data_buf1[`UCB_BUS_WIDTH_M1 :0] :
292	data_d1[`UCB_BUS_WIDTH_M1 :0];
293
294
295	/************************************************************
296	* Assemble inbound data
297	************************************************************/
298	// valid vector
299	assign indata_vec_next[`CYC_NUM_M1:0] = {vld_mux, indata_vec[`CYC_NUM_M1 :1]};
300
301	assign stall_a1_n = ~stall_a1;
302	ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_32 indata_vec_ff
303	(
304	.scan_in(indata_vec_ff_scanin),
305	.scan_out(indata_vec_ff_scanout),
306	.dout (indata_vec[`CYC_NUM_M1 :0]),
307	.l1clk (l1clk),
308	.en (stall_a1_n),
309	.din (indata_vec_next[`CYC_NUM_M1 :0]),
310	.siclk(siclk),
311	.soclk(soclk)
312	);
313
314	// data buffer
315	assign indata_buf_next[127:0] = {data_mux[`UCB_BUS_WIDTH_M1 :0], indata_buf[127:`UCB_BUS_WIDTH ]};
316	ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_128 indata_buf_ff
317	(
318	.scan_in(indata_buf_ff_scanin),
319	.scan_out(indata_buf_ff_scanout),
320	.dout (indata_buf[127:0]),
321	.l1clk (l1clk),
322	.en (stall_a1_n),
323	.din (indata_buf_next[127:0]),
324	.siclk(siclk),
325	.soclk(soclk)
326	);
327
328	// detect a new packet
329	ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 indata_vec0_d1_ff
330	(
331	.scan_in(indata_vec0_d1_ff_scanin),
332	.scan_out(indata_vec0_d1_ff_scanout),
333	.dout (indata_vec0_d1),
334	.l1clk (l1clk),
335	.en (stall_a1_n),
336	.din (indata_vec[0]),
337	.siclk(siclk),
338	.soclk(soclk)
339	);
340
341	assign indata_buf_vld = indata_vec[0] & ~indata_vec0_d1;
342
343
344
345
346
347	/** adding clock header **/
348	ncu_ssiui4_ctl_l1clkhdr_ctl_macro clkgen (
349	.l2clk (iol2clk),
350	.l1en (1'b1),
351	.l1clk (l1clk),
352	.pce_ov(pce_ov),
353	.stop(stop),
354	.se(se)
355	);
356
357	/* building tcu port */
358	assign siclk = tcu_aclk;
359	assign soclk = tcu_bclk;
360	assign se = tcu_scan_en;
361	assign pce_ov = tcu_pce_ov;
362	assign stop = tcu_clk_stop;
363
364	// fixscan start:
365	assign vld_d1_ff_scanin = scan_in ;
366	assign data_d1_ff_scanin = vld_d1_ff_scanout ;
367	assign stall_ff_scanin = data_d1_ff_scanout ;
368	assign stall_d1_ff_scanin = stall_ff_scanout ;
369	assign vld_buf0_ff_scanin = stall_d1_ff_scanout ;
370	assign data_buf0_ff_scanin = vld_buf0_ff_scanout ;
371	assign skid_buf1_en_ff_scanin = data_buf0_ff_scanout ;
372	assign vld_buf1_ff_scanin = skid_buf1_en_ff_scanout ;
373	assign data_buf1_ff_scanin = vld_buf1_ff_scanout ;
374	assign skid_buf1_sel_ff_scanin = data_buf1_ff_scanout ;
375	assign indata_vec_ff_scanin = skid_buf1_sel_ff_scanout ;
376	assign indata_buf_ff_scanin = indata_vec_ff_scanout ;
377	assign indata_vec0_d1_ff_scanin = indata_buf_ff_scanout ;
378	assign scan_out = indata_vec0_d1_ff_scanout;
379	// fixscan end:
380	endmodule // ucb_bus_in
381
382
383
384
385
386
387	// any PARAMS parms go into naming of macro
388
389	module ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_1 (
390	din,
391	en,
392	l1clk,
393	scan_in,
394	siclk,
395	soclk,
396	dout,
397	scan_out);
398	wire [0:0] fdin;
399
400	input [0:0] din;
401	input en;
402	input l1clk;
403	input scan_in;
404
405
406	input siclk;
407	input soclk;
408
409	output [0:0] dout;
410	output scan_out;
411	assign fdin[0:0] = (din[0:0] & {1{en}}) \| (dout[0:0] & ~{1{en}});
412
413
414
415
416
417
418	dff #(1) d0_0 (
419	.l1clk(l1clk),
420	.siclk(siclk),
421	.soclk(soclk),
422	.d(fdin[0:0]),
423	.si(scan_in),
424	.so(scan_out),
425	.q(dout[0:0])
426	);
427
428
429
430
431
432
433
434
435
436
437
438
439	endmodule
440
441
442
443
444
445
446
447
448
449
450
451
452
453	// any PARAMS parms go into naming of macro
454
455	module ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_4 (
456	din,
457	en,
458	l1clk,
459	scan_in,
460	siclk,
461	soclk,
462	dout,
463	scan_out);
464	wire [3:0] fdin;
465	wire [2:0] so;
466
467	input [3:0] din;
468	input en;
469	input l1clk;
470	input scan_in;
471
472
473	input siclk;
474	input soclk;
475
476	output [3:0] dout;
477	output scan_out;
478	assign fdin[3:0] = (din[3:0] & {4{en}}) \| (dout[3:0] & ~{4{en}});
479
480
481
482
483
484
485	dff #(4) d0_0 (
486	.l1clk(l1clk),
487	.siclk(siclk),
488	.soclk(soclk),
489	.d(fdin[3:0]),
490	.si({scan_in,so[2:0]}),
491	.so({so[2:0],scan_out}),
492	.q(dout[3:0])
493	);
494
495
496
497
498
499
500
501
502
503
504
505
506	endmodule
507
508
509
510
511
512
513
514
515
516
517
518
519
520	// any PARAMS parms go into naming of macro
521
522	module ncu_ssiui4_ctl_msff_ctl_macro__width_1 (
523	din,
524	l1clk,
525	scan_in,
526	siclk,
527	soclk,
528	dout,
529	scan_out);
530	wire [0:0] fdin;
531
532	input [0:0] din;
533	input l1clk;
534	input scan_in;
535
536
537	input siclk;
538	input soclk;
539
540	output [0:0] dout;
541	output scan_out;
542	assign fdin[0:0] = din[0:0];
543
544
545
546
547
548
549	dff #(1) d0_0 (
550	.l1clk(l1clk),
551	.siclk(siclk),
552	.soclk(soclk),
553	.d(fdin[0:0]),
554	.si(scan_in),
555	.so(scan_out),
556	.q(dout[0:0])
557	);
558
559
560
561
562
563
564
565
566
567
568
569
570	endmodule
571
572
573
574
575
576
577
578
579
580
581
582
583
584	// any PARAMS parms go into naming of macro
585
586	module ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_32 (
587	din,
588	en,
589	l1clk,
590	scan_in,
591	siclk,
592	soclk,
593	dout,
594	scan_out);
595	wire [31:0] fdin;
596	wire [30:0] so;
597
598	input [31:0] din;
599	input en;
600	input l1clk;
601	input scan_in;
602
603
604	input siclk;
605	input soclk;
606
607	output [31:0] dout;
608	output scan_out;
609	assign fdin[31:0] = (din[31:0] & {32{en}}) \| (dout[31:0] & ~{32{en}});
610
611
612
613
614
615
616	dff #(32) d0_0 (
617	.l1clk(l1clk),
618	.siclk(siclk),
619	.soclk(soclk),
620	.d(fdin[31:0]),
621	.si({scan_in,so[30:0]}),
622	.so({so[30:0],scan_out}),
623	.q(dout[31:0])
624	);
625
626
627
628
629
630
631
632
633
634
635
636
637	endmodule
638
639
640
641
642
643
644
645
646
647
648
649
650
651	// any PARAMS parms go into naming of macro
652
653	module ncu_ssiui4_ctl_msff_ctl_macro__en_1__width_128 (
654	din,
655	en,
656	l1clk,
657	scan_in,
658	siclk,
659	soclk,
660	dout,
661	scan_out);
662	wire [127:0] fdin;
663	wire [126:0] so;
664
665	input [127:0] din;
666	input en;
667	input l1clk;
668	input scan_in;
669
670
671	input siclk;
672	input soclk;
673
674	output [127:0] dout;
675	output scan_out;
676	assign fdin[127:0] = (din[127:0] & {128{en}}) \| (dout[127:0] & ~{128{en}});
677
678
679
680
681
682
683	dff #(128) d0_0 (
684	.l1clk(l1clk),
685	.siclk(siclk),
686	.soclk(soclk),
687	.d(fdin[127:0]),
688	.si({scan_in,so[126:0]}),
689	.so({so[126:0],scan_out}),
690	.q(dout[127:0])
691	);
692
693
694
695
696
697
698
699
700
701
702
703
704	endmodule
705
706
707
708
709
710
711
712
713
714
715
716
717
718	// any PARAMS parms go into naming of macro
719
720	module ncu_ssiui4_ctl_l1clkhdr_ctl_macro (
721	l2clk,
722	l1en,
723	pce_ov,
724	stop,
725	se,
726	l1clk);
727
728
729	input l2clk;
730	input l1en;
731	input pce_ov;
732	input stop;
733	input se;
734	output l1clk;
735
736
737
738
739
740	cl_sc1_l1hdr_8x c_0 (
741
742
743	.l2clk(l2clk),
744	.pce(l1en),
745	.l1clk(l1clk),
746	.se(se),
747	.pce_ov(pce_ov),
748	.stop(stop)
749	);
750
751
752
753	endmodule
754
755
756
757
758
759
760
761