projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: fflp_sync2sys_clk.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | /**********************************************************************/ | |
| 36 | /*project name: N2 */ | |
| 37 | /*module name: fflp_sync2sys_clk */ | |
| 38 | /*description: syncronization between fcram clk and core clk */ | |
| 39 | /* */ | |
| 40 | /*parent module in: */ | |
| 41 | /*child modules in: */ | |
| 42 | /* */ | |
| 43 | /*interface modules: */ | |
| 44 | /*author name: Jeanne Cai */ | |
| 45 | /*date created: 04-08-04 */ | |
| 46 | /* */ | |
| 47 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ | |
| 48 | /* Sun Proprietary and Confidential */ | |
| 49 | /* */ | |
| 50 | /*modifications: */ | |
| 51 | /* */ | |
| 52 | /* */ | |
| 53 | ||
| 54 | module fflp_sync2sys_clk ( | |
| 55 | cclk, //core clk | |
| 56 | cpu_fc_req_done, | |
| 57 | cpu_fio_req_done, | |
| 58 | fc_fifo_ren, | |
| 59 | zcp_wr, | |
| 60 | ||
| 61 | cpu_fc_req_done_sync, | |
| 62 | cpu_fio_req_done_sync, | |
| 63 | fc_fifo_ren_sync, | |
| 64 | fflp_zcp_wr_p, | |
| 65 | fflp_zcp_wr | |
| 66 | ); | |
| 67 | ||
| 68 | ||
| 69 | input cclk; | |
| 70 | input cpu_fc_req_done; | |
| 71 | input cpu_fio_req_done; | |
| 72 | input fc_fifo_ren; | |
| 73 | input zcp_wr; | |
| 74 | ||
| 75 | output cpu_fc_req_done_sync; | |
| 76 | output cpu_fio_req_done_sync; | |
| 77 | output fc_fifo_ren_sync; | |
| 78 | output fflp_zcp_wr_p; | |
| 79 | output[4:0] fflp_zcp_wr; | |
| 80 | ||
| 81 | ||
| 82 | wire cpu_fc_req_done1; | |
| 83 | wire cpu_fio_req_done1; | |
| 84 | wire zcp_wr1; | |
| 85 | ||
| 86 | wire cpu_fc_req_done_sync; | |
| 87 | wire cpu_fio_req_done_sync; | |
| 88 | wire fc_fifo_ren_sync; | |
| 89 | wire zcp_wr_sync; | |
| 90 | wire zcp_wr_sync_dly; | |
| 91 | ||
| 92 | wire fflp_zcp_wr_p; | |
| 93 | wire[4:0] fflp_zcp_wr_bits; | |
| 94 | wire[4:0] fflp_zcp_wr; | |
| 95 | ||
| 96 | niu_dff #(1) cpu_fc_req_done1_reg (cclk, cpu_fc_req_done, cpu_fc_req_done1); | |
| 97 | niu_dff #(1) cpu_fio_req_done1_reg (cclk, cpu_fio_req_done, cpu_fio_req_done1); | |
| 98 | niu_dff #(1) zcp_wr1_reg (cclk, zcp_wr, zcp_wr1); | |
| 99 | ||
| 100 | /* | |
| 101 | Need to put it back if fcram_clk is different from niu_clk. | |
| 102 | This is due to cutting fc fifo to two entries to save gates | |
| 103 | for adding one pipeline for new fio read latency. | |
| 104 | ||
| 105 | wire fc_fifo_ren1; | |
| 106 | niu_dff #(1) fc_fifo_ren1_reg (cclk, fc_fifo_ren, fc_fifo_ren1); | |
| 107 | niu_dff #(1) fc_fifo_ren2_reg (cclk, fc_fifo_ren1, fc_fifo_ren_sync); | |
| 108 | */ | |
| 109 | ||
| 110 | assign fc_fifo_ren_sync = fc_fifo_ren; | |
| 111 | ||
| 112 | niu_dff #(1) cpu_fc_req_done2_reg (cclk, cpu_fc_req_done1, cpu_fc_req_done_sync); | |
| 113 | niu_dff #(1) cpu_fio_req_done2_reg (cclk, cpu_fio_req_done1, cpu_fio_req_done_sync); | |
| 114 | niu_dff #(1) zcp_wr2_reg (cclk, zcp_wr1, zcp_wr_sync); | |
| 115 | ||
| 116 | niu_dff #(1) zcp_wr3_reg (cclk, zcp_wr_sync, zcp_wr_sync_dly); | |
| 117 | ||
| 118 | assign fflp_zcp_wr_p = zcp_wr_sync & !zcp_wr_sync_dly; | |
| 119 | assign fflp_zcp_wr_bits = {5{fflp_zcp_wr_p}}; | |
| 120 | ||
| 121 | niu_dff #(5) fflp_zcp_wr_reg (cclk, fflp_zcp_wr_bits, fflp_zcp_wr); | |
| 122 | ||
| 123 | ||
| 124 | endmodule | |
| 125 | ||
| 126 |