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// OpenSPARC T2 Processor File: fflp_sync2sys_clk.v
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/**********************************************************************/
/*module name: fflp_sync2sys_clk */
/*description: syncronization between fcram clk and core clk */
/*author name: Jeanne Cai */
/*date created: 04-08-04 */
/* Copyright (c) 2004, Sun Microsystems, Inc. */
/* Sun Proprietary and Confidential */
module fflp_sync2sys_clk (
output cpu_fc_req_done_sync;
output cpu_fio_req_done_sync;
wire cpu_fc_req_done_sync;
wire cpu_fio_req_done_sync;
wire[4:0] fflp_zcp_wr_bits;
niu_dff #(1) cpu_fc_req_done1_reg (cclk, cpu_fc_req_done, cpu_fc_req_done1);
niu_dff #(1) cpu_fio_req_done1_reg (cclk, cpu_fio_req_done, cpu_fio_req_done1);
niu_dff #(1) zcp_wr1_reg (cclk, zcp_wr, zcp_wr1);
Need to put it back if fcram_clk is different from niu_clk.
This is due to cutting fc fifo to two entries to save gates
for adding one pipeline for new fio read latency.
niu_dff #(1) fc_fifo_ren1_reg (cclk, fc_fifo_ren, fc_fifo_ren1);
niu_dff #(1) fc_fifo_ren2_reg (cclk, fc_fifo_ren1, fc_fifo_ren_sync);
assign fc_fifo_ren_sync = fc_fifo_ren;
niu_dff #(1) cpu_fc_req_done2_reg (cclk, cpu_fc_req_done1, cpu_fc_req_done_sync);
niu_dff #(1) cpu_fio_req_done2_reg (cclk, cpu_fio_req_done1, cpu_fio_req_done_sync);
niu_dff #(1) zcp_wr2_reg (cclk, zcp_wr1, zcp_wr_sync);
niu_dff #(1) zcp_wr3_reg (cclk, zcp_wr_sync, zcp_wr_sync_dly);
assign fflp_zcp_wr_p = zcp_wr_sync & !zcp_wr_sync_dly;
assign fflp_zcp_wr_bits = {5{fflp_zcp_wr_p}};
niu_dff #(5) fflp_zcp_wr_reg (cclk, fflp_zcp_wr_bits, fflp_zcp_wr);