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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mif_control_sm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mif_control_sm | |
36 | (/*AUTOARG*/ | |
37 | // Outputs | |
38 | fetch_instr, poll_instr, ld_output_reg, ld_poll_status, | |
39 | ctl_state, | |
40 | // Inputs | |
41 | clk, reset, instr_pnd, poll_en, mif_pio_intr, wr_done, rd_done, | |
42 | illegal_instr | |
43 | ); | |
44 | ||
45 | ||
46 | input clk; | |
47 | input reset; | |
48 | input instr_pnd; | |
49 | input poll_en; | |
50 | input mif_pio_intr; | |
51 | input wr_done; | |
52 | input rd_done; | |
53 | input illegal_instr; | |
54 | output fetch_instr; | |
55 | output poll_instr; | |
56 | output ld_output_reg; | |
57 | output ld_poll_status; | |
58 | output [2:0] ctl_state; | |
59 | ||
60 | wire [2:0] new_ctl_state; | |
61 | wire d_ld_poll_status; | |
62 | ||
63 | parameter IDLE = 3'h0, | |
64 | FETCH = 3'h1, | |
65 | EX1 = 3'h2, | |
66 | RD1 = 3'h3, | |
67 | POLL = 3'h4, | |
68 | EX2 = 3'h5, | |
69 | RD2 = 3'h6; | |
70 | ||
71 | function [6:0] control_state_transitions; | |
72 | input reset; | |
73 | input d_ld_poll_status; | |
74 | input instr_pnd; | |
75 | input poll_en; | |
76 | input mif_pio_intr; | |
77 | input wr_done; | |
78 | input rd_done; | |
79 | input illegal_instr; | |
80 | input [2:0] ctl_state; | |
81 | reg fetch_instr; | |
82 | reg poll_instr; | |
83 | reg ld_output_reg; | |
84 | reg ld_poll_status; | |
85 | reg [2:0] new_ctl_state; | |
86 | ||
87 | begin | |
88 | if (reset) | |
89 | begin | |
90 | fetch_instr = 0; | |
91 | poll_instr = 0; | |
92 | ld_output_reg = 0; | |
93 | ld_poll_status= 0; | |
94 | new_ctl_state = IDLE; | |
95 | end | |
96 | else | |
97 | begin | |
98 | fetch_instr = 0; | |
99 | poll_instr = 0; | |
100 | ld_output_reg = 0; | |
101 | ld_poll_status= 0; | |
102 | new_ctl_state = IDLE; | |
103 | ||
104 | case (ctl_state) //synopsys parallel_case | |
105 | ||
106 | IDLE: | |
107 | begin | |
108 | if (instr_pnd) new_ctl_state = FETCH; | |
109 | else if (!d_ld_poll_status & poll_en & !mif_pio_intr) | |
110 | new_ctl_state = POLL; | |
111 | else new_ctl_state = IDLE; | |
112 | end | |
113 | ||
114 | FETCH: | |
115 | begin | |
116 | fetch_instr = 1; | |
117 | new_ctl_state = EX1; | |
118 | end | |
119 | ||
120 | EX1: | |
121 | begin | |
122 | if (illegal_instr | wr_done) | |
123 | begin | |
124 | ld_output_reg = 1; | |
125 | new_ctl_state = IDLE; | |
126 | end | |
127 | else if (rd_done) new_ctl_state = RD1; | |
128 | else new_ctl_state = EX1; | |
129 | end | |
130 | ||
131 | RD1: | |
132 | begin | |
133 | ld_output_reg = 1; | |
134 | new_ctl_state = IDLE; | |
135 | end | |
136 | ||
137 | POLL: | |
138 | begin | |
139 | poll_instr = 1; | |
140 | new_ctl_state = EX2; | |
141 | end | |
142 | ||
143 | EX2: | |
144 | begin | |
145 | if (rd_done) new_ctl_state = RD2; | |
146 | else new_ctl_state = EX2; | |
147 | end | |
148 | ||
149 | RD2: | |
150 | begin | |
151 | ld_poll_status = 1; | |
152 | new_ctl_state = IDLE; | |
153 | end | |
154 | endcase | |
155 | end | |
156 | control_state_transitions = {fetch_instr,poll_instr,ld_output_reg, | |
157 | ld_poll_status,new_ctl_state}; | |
158 | end | |
159 | endfunction | |
160 | ||
161 | assign {fetch_instr,poll_instr,ld_output_reg,ld_poll_status,new_ctl_state} = | |
162 | control_state_transitions(reset,d_ld_poll_status,instr_pnd,poll_en, | |
163 | mif_pio_intr,wr_done,rd_done, | |
164 | illegal_instr,ctl_state); | |
165 | ||
166 | RegDff #(3) _RegDff (.din(new_ctl_state[2:0]),.clk(clk), | |
167 | .qout(ctl_state[2:0])); | |
168 | ||
169 | FD1 LD_STATUS(.D(ld_poll_status),.CP(clk),.Q(d_ld_poll_status)); | |
170 | ||
171 | endmodule |