[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_ipp_sum_data.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu_ipp_sum_data.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================

`timescale 1ns/10ps

/**********************************************************
***********************************************************

    Project         : Niu

    File name       : niu_ipp_sum_data.v

    Module(s) name  : niu_ipp_sum_data
    Original:       : sum_data.v main.2, label:               

    Parent modules  : niu_ipp_sum.v

    Child modules   : niu_ipp_sum_lib.v, niu_ipp_sum_lib.h, 

    Author's name   : George Chu

    Date            : March. 2004

    Description     : Data logic of the ipp checksum.

    Synthesis Notes:

    Modification History:

    Date       Description
    ----       -----------

************************************************************
***********************************************************/

module niu_ipp_sum_data (din_wrd, hdr_off,
                 byt_ena, sel_awd, 
                 sel_asw7,
                 sel_asw6,
                 sel_asw5,
                 sel_asw3,
                 sel_asw2,
                 sel_asw1,
                 sel_bwd7,
                 sel_bwd5,
                 sel_bwd4,
                 sel_bwd3,
                 sel_bwd1,
                 sel_add,
                 inp_uln,
                 get_uln,
                 add_uln,
                 clr,     clk,
                 sum_prt_cksum, c_dsum_fail);

input  [127:0] din_wrd;
input    [3:0] hdr_off;
input   [15:0] byt_ena;
input    [1:0] sel_awd;
input          sel_asw7;
input          sel_asw6;
input          sel_asw5;
input          sel_asw3;
input          sel_asw2;
input          sel_asw1;
input          sel_bwd7;
input          sel_bwd5;
input          sel_bwd4;
input          sel_bwd3;
input          sel_bwd1;
input          sel_add;
input   [15:0] inp_uln;
input          get_uln;
input          add_uln;
input          clr;
input          clk;
output  [15:0] sum_prt_cksum;
output         c_dsum_fail;

wire    [15:0] sum_prt_cksum;
wire           c_dsum_fail;

wire    [15:0] sum_wrd1;
wire    [15:0] sum_wrd2;
wire    [15:0] sum_wrd3;
wire    [15:0] sum_wrd4;
wire    [15:0] sum_wrd5;
wire    [15:0] sum_wrd6;
wire    [15:0] sum_wrd7;

wire           sel_add_q = sel_add || add_uln;

  ipp_sum_dev_01_0q su_dev_01_0q_0 (
                               .inp_wd3    (sum_wrd4[15:0]),
                               .inp_wd2    (sum_wrd2[15:0]),
                               .inp_wd1    (sum_wrd1[15:0]),
                               .inp_wrd    (din_wrd[15:00]),
                               .byt_ena    (byt_ena[01:00]),
                               .sel_awd    (sel_awd[1:0]),
                               .sel_add    (sel_add_q),
                               .clr        (clr),
                               .clk        (clk),
                               .prt_cksum  (sum_prt_cksum[15:0]),
                               .cksum_fail (c_dsum_fail) 
                              );

  ipp_sum_dev_01_ut su_dev_01_ut_1 (
                               .inp_uln    (inp_uln[15:00]),
                               .inp_wrd    (din_wrd[31:16]),
                               .hdr_off    (hdr_off[03:0]),
                               .byt_ena    (byt_ena[03:02]),
                               .sel_asw    (sel_asw1),
                               .sel_bwd    (sel_bwd1),
                               .sel_add    (sel_add),
                               .get_uln    (get_uln),
                               .clr        (clr),
                               .clk        (clk),
                               .sum_wrd    (sum_wrd1[15:0])
                              );

  ipp_sum_dev_01_0s su_dev_01_0s_2 (
                               .inp_wd1    (sum_wrd3[15:0]),
                               .inp_wrd    (din_wrd[47:32]),
                               .byt_ena    (byt_ena[05:04]),
                               .sel_awd    (sel_awd[0]),
                               .sel_asw    (sel_asw2),
                               .sel_add    (sel_add),
                               .clr        (clr),
                               .clk        (clk),
                               .sum_wrd    (sum_wrd2[15:0])
                              );

  ipp_sum_dev_01_0t su_dev_01_0t_3 (
                               .inp_wrd    (din_wrd[63:48]),
                               .hdr_off    (hdr_off[03:0]),
                               .byt_ena    (byt_ena[07:06]),
                               .sel_asw    (sel_asw3),
                               .sel_bwd    (sel_bwd3),
                               .sel_add    (sel_add),
                               .clr        (clr),
                               .clk        (clk),
                               .sum_wrd    (sum_wrd3[15:0])
                              );

  ipp_sum_dev_01_0r su_dev_01_0r_4 (
                               .inp_wd2    (sum_wrd6[15:0]),
                               .inp_wd1    (sum_wrd5[15:0]),
                               .inp_wrd    (din_wrd[79:64]),
                               .hdr_off    (hdr_off[03:0]),
                               .byt_ena    (byt_ena[09:08]),
                               .sel_awd    (sel_awd[1:0]),
                               .sel_bwd    (sel_bwd4),
                               .sel_add    (sel_add),
                               .clr        (clr),
                               .clk        (clk),
                               .sum_wrd    (sum_wrd4[15:0])
                              );

  ipp_sum_dev_01_0t su_dev_01_0t_5 (
                               .inp_wrd    (din_wrd[95:80]),
                               .hdr_off    (hdr_off[03:0]),
                               .byt_ena    (byt_ena[11:10]),
                               .sel_asw    (sel_asw5),
                               .sel_bwd    (sel_bwd5),
                               .sel_add    (sel_add),
                               .clr        (clr),
                               .clk        (clk),
                               .sum_wrd    (sum_wrd5[15:0])
                              );

  ipp_sum_dev_01_0s su_dev_01_0s_6 (
                               .inp_wd1    (sum_wrd7[15:0]),
                               .inp_wrd    (din_wrd[111:96]),
                               .byt_ena    (byt_ena[13:12]),
                               .sel_awd    (sel_awd[0]),
                               .sel_asw    (sel_asw6),
                               .sel_add    (sel_add),
                               .clr        (clr),
                               .clk        (clk),
                               .sum_wrd    (sum_wrd6[15:0])
                              );

  ipp_sum_dev_01_0t su_dev_01_0t_7 (
                               .inp_wrd    (din_wrd[127:112]),
                               .hdr_off    (hdr_off[03:0]),
                               .byt_ena    (byt_ena[15:14]),
                               .sel_asw    (sel_asw7),
                               .sel_bwd    (sel_bwd7),
                               .sel_add    (sel_add),
                               .clr        (clr),
                               .clk        (clk),
                               .sum_wrd    (sum_wrd7[15:0])
                              );

endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: niu_ipp_sum_data.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35
	36	`timescale 1ns/10ps
	37
	38	/**********************************************************
	39	***********************************************************
	40
	41	Project : Niu
	42
	43	File name : niu_ipp_sum_data.v
	44
	45	Module(s) name : niu_ipp_sum_data
	46	Original: : sum_data.v main.2, label:
	47
	48	Parent modules : niu_ipp_sum.v
	49
	50	Child modules : niu_ipp_sum_lib.v, niu_ipp_sum_lib.h,
	51
	52	Author's name : George Chu
	53
	54	Date : March. 2004
	55
	56	Description : Data logic of the ipp checksum.
	57
	58	Synthesis Notes:
	59
	60	Modification History:
	61
	62	Date Description
	63	---- -----------
	64
65	************************************************************
66	***********************************************************/
67
68	module niu_ipp_sum_data (din_wrd, hdr_off,
69	byt_ena, sel_awd,
70	sel_asw7,
71	sel_asw6,
72	sel_asw5,
73	sel_asw3,
74	sel_asw2,
75	sel_asw1,
76	sel_bwd7,
77	sel_bwd5,
78	sel_bwd4,
79	sel_bwd3,
80	sel_bwd1,
81	sel_add,
82	inp_uln,
83	get_uln,
84	add_uln,
85	clr, clk,
86	sum_prt_cksum, c_dsum_fail);
87
88	input [127:0] din_wrd;
89	input [3:0] hdr_off;
90	input [15:0] byt_ena;
91	input [1:0] sel_awd;
92	input sel_asw7;
93	input sel_asw6;
94	input sel_asw5;
95	input sel_asw3;
96	input sel_asw2;
97	input sel_asw1;
98	input sel_bwd7;
99	input sel_bwd5;
100	input sel_bwd4;
101	input sel_bwd3;
102	input sel_bwd1;
103	input sel_add;
104	input [15:0] inp_uln;
105	input get_uln;
106	input add_uln;
107	input clr;
108	input clk;
109	output [15:0] sum_prt_cksum;
110	output c_dsum_fail;
111
112	wire [15:0] sum_prt_cksum;
113	wire c_dsum_fail;
114
115	wire [15:0] sum_wrd1;
116	wire [15:0] sum_wrd2;
117	wire [15:0] sum_wrd3;
118	wire [15:0] sum_wrd4;
119	wire [15:0] sum_wrd5;
120	wire [15:0] sum_wrd6;
121	wire [15:0] sum_wrd7;
122
123	wire sel_add_q = sel_add \|\| add_uln;
124
125	ipp_sum_dev_01_0q su_dev_01_0q_0 (
126	.inp_wd3 (sum_wrd4[15:0]),
127	.inp_wd2 (sum_wrd2[15:0]),
128	.inp_wd1 (sum_wrd1[15:0]),
129	.inp_wrd (din_wrd[15:00]),
130	.byt_ena (byt_ena[01:00]),
131	.sel_awd (sel_awd[1:0]),
132	.sel_add (sel_add_q),
133	.clr (clr),
134	.clk (clk),
135	.prt_cksum (sum_prt_cksum[15:0]),
136	.cksum_fail (c_dsum_fail)
137	);
138
139	ipp_sum_dev_01_ut su_dev_01_ut_1 (
140	.inp_uln (inp_uln[15:00]),
141	.inp_wrd (din_wrd[31:16]),
142	.hdr_off (hdr_off[03:0]),
143	.byt_ena (byt_ena[03:02]),
144	.sel_asw (sel_asw1),
145	.sel_bwd (sel_bwd1),
146	.sel_add (sel_add),
147	.get_uln (get_uln),
148	.clr (clr),
149	.clk (clk),
150	.sum_wrd (sum_wrd1[15:0])
151	);
152
153	ipp_sum_dev_01_0s su_dev_01_0s_2 (
154	.inp_wd1 (sum_wrd3[15:0]),
155	.inp_wrd (din_wrd[47:32]),
156	.byt_ena (byt_ena[05:04]),
157	.sel_awd (sel_awd[0]),
158	.sel_asw (sel_asw2),
159	.sel_add (sel_add),
160	.clr (clr),
161	.clk (clk),
162	.sum_wrd (sum_wrd2[15:0])
163	);
164
165	ipp_sum_dev_01_0t su_dev_01_0t_3 (
166	.inp_wrd (din_wrd[63:48]),
167	.hdr_off (hdr_off[03:0]),
168	.byt_ena (byt_ena[07:06]),
169	.sel_asw (sel_asw3),
170	.sel_bwd (sel_bwd3),
171	.sel_add (sel_add),
172	.clr (clr),
173	.clk (clk),
174	.sum_wrd (sum_wrd3[15:0])
175	);
176
177	ipp_sum_dev_01_0r su_dev_01_0r_4 (
178	.inp_wd2 (sum_wrd6[15:0]),
179	.inp_wd1 (sum_wrd5[15:0]),
180	.inp_wrd (din_wrd[79:64]),
181	.hdr_off (hdr_off[03:0]),
182	.byt_ena (byt_ena[09:08]),
183	.sel_awd (sel_awd[1:0]),
184	.sel_bwd (sel_bwd4),
185	.sel_add (sel_add),
186	.clr (clr),
187	.clk (clk),
188	.sum_wrd (sum_wrd4[15:0])
189	);
190
191	ipp_sum_dev_01_0t su_dev_01_0t_5 (
192	.inp_wrd (din_wrd[95:80]),
193	.hdr_off (hdr_off[03:0]),
194	.byt_ena (byt_ena[11:10]),
195	.sel_asw (sel_asw5),
196	.sel_bwd (sel_bwd5),
197	.sel_add (sel_add),
198	.clr (clr),
199	.clk (clk),
200	.sum_wrd (sum_wrd5[15:0])
201	);
202
203	ipp_sum_dev_01_0s su_dev_01_0s_6 (
204	.inp_wd1 (sum_wrd7[15:0]),
205	.inp_wrd (din_wrd[111:96]),
206	.byt_ena (byt_ena[13:12]),
207	.sel_awd (sel_awd[0]),
208	.sel_asw (sel_asw6),
209	.sel_add (sel_add),
210	.clr (clr),
211	.clk (clk),
212	.sum_wrd (sum_wrd6[15:0])
213	);
214
215	ipp_sum_dev_01_0t su_dev_01_0t_7 (
216	.inp_wrd (din_wrd[127:112]),
217	.hdr_off (hdr_off[03:0]),
218	.byt_ena (byt_ena[15:14]),
219	.sel_asw (sel_asw7),
220	.sel_bwd (sel_bwd7),
221	.sel_add (sel_add),
222	.clr (clr),
223	.clk (clk),
224	.sum_wrd (sum_wrd7[15:0])
225	);
226
227	endmodule
228