Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_pio_debug.v

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// OpenSPARC T2 Processor File: niu_pio_debug.v
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/*********************************************************************
 *
 *  niu_pio_debug..v
 *
 *  NIU TDMC Top Level Debug Module
 *
 *  Orignal Author(s):   Maya Suresh
 *  Modifier(s):
 *  Project(s):          Neptune/Niagara 2
 *
 *  Copyright (c) 2004   Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  This verilog model is the confidential and proprietary property of
 *  Sun Microsystems, Inc., and the possession or use of this model
 *  requires a written license from Sun Microsystems, Inc.
 *
 **********************************************************************/

module niu_pio_debug( 
        SysClk,
        Reset_L,
        TrainingVector,
        pio_debug_port,
        rd_ptr,
        wr_ptr,
        pio_rw_state,
        accepted_state,
        ig_state,
        debug_select
       );

// Global Signals
input         SysClk;
input         Reset_L;
input [4:0]   rd_ptr ;
input [4:0]   wr_ptr ;
input [2:0]   pio_rw_state ;
input [1:0]   accepted_state ;
input [2:0]   ig_state ;

// To Debug Module
output [31:0] pio_debug_port;

reg    [31:0] pio_debug_port;

// From Control Regs
input  [5:0]  debug_select ;
input  [31:0] TrainingVector ;

/*--------------------------------------------------------------*/
// Debug Block
/*--------------------------------------------------------------*/

always @(posedge SysClk)
  if (!Reset_L) pio_debug_port  <= 32'h0;
  else
   case(debug_select)
     6'h0: pio_debug_port <= {22'b0,rd_ptr[4:0],wr_ptr[4:0]};
     6'h1: pio_debug_port <= {24'b0,ig_state[2:0],pio_rw_state[2:0],accepted_state[1:0]};
     6'h2: pio_debug_port <= ~pio_debug_port;
     6'h3: pio_debug_port <= TrainingVector;
  
  default: pio_debug_port <= 32'h0;

  endcase

endmodule