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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_zcp_ram_access_sm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /*%W% %G%*/ | |
36 | ||
37 | /*************************************************************** | |
38 | * | |
39 | * File Name : niu_zcp_ram_access_sm.v | |
40 | * Author Name : John Lo | |
41 | * Description : buffer response state machine | |
42 | * for unloading response fifo data. | |
43 | * | |
44 | * Parent Module: niu_zcp_rsp_intf | |
45 | * Child Module: | |
46 | * Interface Mod: | |
47 | * Date Created : 7/22/2004 | |
48 | * | |
49 | * Copyright (c) 2020, Sun Microsystems, Inc. | |
50 | * Sun Proprietary and Confidential | |
51 | * | |
52 | * Modification : | |
53 | * | |
54 | * Synthesis Notes: | |
55 | * | |
56 | * Design Notes: | |
57 | * | |
58 | **************************************************************/ | |
59 | ||
60 | ||
61 | module niu_zcp_ram_access_sm | |
62 | (/*AUTOARG*/ | |
63 | // Outputs | |
64 | ram_ren, ram_wen, slv_request, ld_ram2reg, ram_access_state, | |
65 | // Inputs | |
66 | clk, reset10, ld_ram_addr_trail, slv_accepted, rw | |
67 | ); | |
68 | ||
69 | input clk; | |
70 | input reset10; | |
71 | input ld_ram_addr_trail; | |
72 | input slv_accepted; | |
73 | input rw; | |
74 | output ram_ren; | |
75 | output ram_wen; | |
76 | output slv_request; | |
77 | output ld_ram2reg; | |
78 | output [2:0] ram_access_state; | |
79 | ||
80 | ||
81 | wire slv_accepted; | |
82 | wire [2:0] ram_access_state; | |
83 | reg [2:0] nx_ram_access_state; | |
84 | reg slv_request; | |
85 | reg ram_ren; | |
86 | reg ram_wen; | |
87 | reg p1_ld_ram2reg; | |
88 | ||
89 | parameter IDLE = 3'd0, | |
90 | ARB = 3'd1, | |
91 | DLY1 = 3'd2, | |
92 | D_RDY = 3'd3, // data ready | |
93 | P_CHK = 3'd4; // parity check and latch into reg | |
94 | ||
95 | ||
96 | // comb part | |
97 | always @ (/*AUTOSENSE*/ld_ram_addr_trail or ram_access_state or rw | |
98 | or slv_accepted) | |
99 | begin | |
100 | nx_ram_access_state = IDLE; | |
101 | slv_request = 0; | |
102 | ram_ren = 0; | |
103 | ram_wen = 0; | |
104 | p1_ld_ram2reg = 0; | |
105 | ||
106 | casex (ram_access_state) // synopsys parallel_case full_case infer_mux | |
107 | IDLE: if (ld_ram_addr_trail) | |
108 | nx_ram_access_state = ARB; | |
109 | else nx_ram_access_state = ram_access_state; // stay | |
110 | ||
111 | ARB: begin | |
112 | slv_request = 1; | |
113 | if (~slv_accepted) | |
114 | nx_ram_access_state = ram_access_state; // stay | |
115 | else begin | |
116 | nx_ram_access_state = DLY1; | |
117 | ram_ren = rw; // ram_ren is a pulse | |
118 | ram_wen = ~rw; // ram_wen is a pulse | |
119 | end | |
120 | end // case: ARB | |
121 | DLY1: begin | |
122 | nx_ram_access_state = D_RDY; // register the ram_ren and ram_wen. | |
123 | end | |
124 | ||
125 | D_RDY: begin // latch RAM output data time -> ld_ram_rdata == 1 | |
126 | nx_ram_access_state = P_CHK; | |
127 | p1_ld_ram2reg = 1; | |
128 | end | |
129 | ||
130 | P_CHK: begin // parity check and latch result into Reg. -> ld_ram2reg == 1 | |
131 | nx_ram_access_state = IDLE; | |
132 | end | |
133 | ||
134 | default: | |
135 | begin | |
136 | nx_ram_access_state = IDLE; | |
137 | // synopsys translate_off | |
138 | // verilint translate off | |
139 | $display("(* ERROR: at sim time = %d, niu_zcp_ram_access_sm is in forbidden state *) \n", $time); | |
140 | // verilint translate on | |
141 | // synopsys translate_on | |
142 | end | |
143 | endcase // casex(ram_access_state) | |
144 | end // always @ (... | |
145 | ||
146 | ||
147 | // seq part | |
148 | zcp_RegRst #(3) ram_access_state_RegRst(.din(nx_ram_access_state), | |
149 | .clk(clk), | |
150 | .reset(reset10), | |
151 | .qout(ram_access_state)); | |
152 | ||
153 | zcp_RegDff #(1) ld_ram2reg_RegDff (.din(p1_ld_ram2reg), .clk(clk),.qout(ld_ram2reg)); // in P_CHK state | |
154 | ||
155 | endmodule // niu_zcp_ram_access_sm | |
156 |