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// OpenSPARC T2 Processor File: niu_zcp_ram_access_sm.v
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/***************************************************************
* File Name : niu_zcp_ram_access_sm.v
* Description : buffer response state machine
* for unloading response fifo data.
* Parent Module: niu_zcp_rsp_intf
* Date Created : 7/22/2004
* Copyright (c) 2020, Sun Microsystems, Inc.
* Sun Proprietary and Confidential
**************************************************************/
module niu_zcp_ram_access_sm
ram_ren, ram_wen, slv_request, ld_ram2reg, ram_access_state,
clk, reset10, ld_ram_addr_trail, slv_accepted, rw
output [2:0] ram_access_state;
wire [2:0] ram_access_state;
reg [2:0] nx_ram_access_state;
D_RDY = 3'd3, // data ready
P_CHK = 3'd4; // parity check and latch into reg
always @ (/*AUTOSENSE*/ld_ram_addr_trail or ram_access_state or rw
nx_ram_access_state = IDLE;
casex (ram_access_state) // synopsys parallel_case full_case infer_mux
IDLE: if (ld_ram_addr_trail)
nx_ram_access_state = ARB;
else nx_ram_access_state = ram_access_state; // stay
nx_ram_access_state = ram_access_state; // stay
nx_ram_access_state = DLY1;
ram_ren = rw; // ram_ren is a pulse
ram_wen = ~rw; // ram_wen is a pulse
nx_ram_access_state = D_RDY; // register the ram_ren and ram_wen.
D_RDY: begin // latch RAM output data time -> ld_ram_rdata == 1
nx_ram_access_state = P_CHK;
P_CHK: begin // parity check and latch result into Reg. -> ld_ram2reg == 1
nx_ram_access_state = IDLE;
nx_ram_access_state = IDLE;
// synopsys translate_off
// verilint translate off
$display("(* ERROR: at sim time = %d, niu_zcp_ram_access_sm is in forbidden state *) \n", $time);
endcase // casex(ram_access_state)
zcp_RegRst #(3) ram_access_state_RegRst(.din(nx_ram_access_state),
.qout(ram_access_state));
zcp_RegDff #(1) ld_ram2reg_RegDff (.din(p1_ld_ram2reg), .clk(clk),.qout(ld_ram2reg)); // in P_CHK state
endmodule // niu_zcp_ram_access_sm