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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: pcs_lfsr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | // @(#)pcs_lfsr.v 1.1G | |
36 | /**********************************************************************/ | |
37 | /* Project Name : CASSINI */ | |
38 | /* Module Name : PCS 10 ms timer */ | |
39 | /* Description : A LFSR is used to create a 50% duty cycle clock */ | |
40 | /* which has a 4.2 ms cycle time. */ | |
41 | /* */ | |
42 | /* Assumptions : none. */ | |
43 | /* */ | |
44 | /* Parent module : pcs_link_config.v */ | |
45 | /* Child modules : none. */ | |
46 | /* Author Name : Linda Chen */ | |
47 | /* Date Created : 11/6/97 */ | |
48 | /* */ | |
49 | /* Copyright (c) 1994, Sun Microsystems, Inc. */ | |
50 | /* Sun Proprietary and Confidential */ | |
51 | /* */ | |
52 | /* Modifications : none yet */ | |
53 | /* Synthesis Notes : delay cells are added to meet hold time given */ | |
54 | /* 400 ps clock skew. */ | |
55 | /**********************************************************************/ | |
56 | ||
57 | module pcs_lfsr (txclk,timer_override,reset_tx,timer_tick); | |
58 | ||
59 | input txclk; | |
60 | input timer_override; | |
61 | input reset_tx; | |
62 | ||
63 | output timer_tick; | |
64 | wire slow_clk; // ticks every 2.1 ms | |
65 | ||
66 | reg [17:0] pat; // pseudo random pattern generated by LFSR | |
67 | ||
68 | wire feedback; // feedback loop to input of LFSR | |
69 | wire at_end; // to toggle slow clk high for 50% duty cycle | |
70 | // ticks every 2.1 ms | |
71 | wire nxt_slow_clk; // input to slow clk register | |
72 | wire [17:0] del_pat; // delay for hold time for lfsr | |
73 | ||
74 | assign at_end = (pat == 18'h1), | |
75 | feedback = pat[0], | |
76 | nxt_slow_clk = (reset_tx)? 1'h0 : (at_end)? | |
77 | ~slow_clk: slow_clk, | |
78 | /* | |
79 | ** If timer override is asserted the slow clk ticks | |
80 | ** about every 8 txclk ticks. | |
81 | */ | |
82 | timer_tick = (timer_override)? (pat[0] & pat[1]): slow_clk; | |
83 | ||
84 | ||
85 | /* | |
86 | ** Primitive polynomial | |
87 | ** 1 + x^1 + x^2 + x^5 + x^19 | |
88 | ** 1 + x^7 + x^18 | |
89 | */ | |
90 | always @(posedge txclk) | |
91 | begin | |
92 | if (reset_tx) pat <= 18'h1; | |
93 | else begin | |
94 | pat[0] <= del_pat[0]; | |
95 | pat[1] <= del_pat[1]; | |
96 | pat[2] <= del_pat[2]; | |
97 | pat[3] <= del_pat[3]; | |
98 | pat[4] <= del_pat[4]; | |
99 | pat[5] <= del_pat[5]; | |
100 | pat[6] <= del_pat[6]; | |
101 | pat[7] <= del_pat[7]; | |
102 | pat[8] <= del_pat[8]; | |
103 | pat[9] <= del_pat[9]; | |
104 | pat[10] <= del_pat[10]; | |
105 | pat[11] <= del_pat[11]; | |
106 | pat[12] <= del_pat[12]; | |
107 | pat[13] <= del_pat[13]; | |
108 | pat[14] <= del_pat[14]; | |
109 | pat[15] <= del_pat[15]; | |
110 | pat[16] <= del_pat[16]; | |
111 | pat[17] <= del_pat[17]; | |
112 | end | |
113 | end | |
114 | ||
115 | // for hold time requirement | |
116 | DEL2ns_PAT delay_pattern( | |
117 | del_pat, | |
118 | {feedback, // x^18 | |
119 | pat[17], | |
120 | pat[16], | |
121 | pat[15], | |
122 | pat[14], | |
123 | pat[13], | |
124 | pat[12], | |
125 | pat[11], | |
126 | pat[10], | |
127 | pat[9], | |
128 | pat[8], | |
129 | pat[7] ^ feedback, | |
130 | pat[6], | |
131 | pat[5], // ^ feedback, // x^5 | |
132 | pat[4], | |
133 | pat[3], | |
134 | pat[2], // ^ feedback, // x^2 | |
135 | pat[1]});// ^ feedback});// x | |
136 | ||
137 | ||
138 | REG #(1) r_slow_clk(slow_clk,txclk,nxt_slow_clk); | |
139 | ||
140 | endmodule | |
141 | ||
142 | ||
143 | ||
144 | ||
145 | ||
146 | ||
147 |