Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / pcie_common / rtl / pcie_common_srq_qcp.v

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// 
// OpenSPARC T2 Processor File: pcie_common_srq_qcp.v
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module pcie_common_srq_qcp (
			    clk,
			    rst_l,
			    enq,
			    deq,
			    ld,
			    ds,
			    vld );
     
// ----------------------------------------------------------------------------
// Parameters
// ----------------------------------------------------------------------------
  parameter	QD = 4;				// queue depth	

// ----------------------------------------------------------------------------
// Ports
// ----------------------------------------------------------------------------
  input			clk;			// clock
  input 		rst_l;			// reset

  input 		enq;			// enqueue
  input 		deq;			// dequeue

  output [QD-1:0]	ld;			// load
  output [QD-2:0]	ds;			// data select
  output [QD-1:0]	vld;			// valid bits

// ----------------------------------------------------------------------------
// Variables
// ----------------------------------------------------------------------------
  reg  [QD-1:0]		ld;
  reg  [QD-2:0]		ds;
  reg  [QD-1:0]		vld, nxt_vld;

  integer 		i;

// ----------------------------------------------------------------------------
// Combinational
// ----------------------------------------------------------------------------

// data selects
  always @ (vld) begin
    for (i = 0; i < QD - 1; i = i + 1) ds[i] = vld[i+1];
  end

// loads
  always @ (rst_l or enq or deq or vld) begin
    case ({enq, deq})
      2'b00 : ld = ~{ QD { rst_l } };
      2'b01 : ld =  vld;
      2'b10 : ld = ~vld;
      2'b11 : ld =  vld;
    endcase
  end

// next valid bits
  always @ (enq or deq or vld) begin
    case ({enq, deq})
      2'b00 : nxt_vld = vld;
      2'b01 : nxt_vld = { 1'b0, vld[QD-1:1] };
      2'b10 : nxt_vld = { vld[QD-2:0], 1'b1 };
      2'b11 : nxt_vld = vld;
    endcase
  end

// ----------------------------------------------------------------------------
// Sequential
// ----------------------------------------------------------------------------

// valid bits
  always @ (posedge clk) begin
    if (!rst_l) begin 
      vld <= 0;
    end
    else begin
      vld <= nxt_vld;
    end
  end

endmodule // pcie_common_srq_qcp