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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: rtx_dmo_mux.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module rtx_dmo_mux (clk, in0, in1, in2, in3, in4, in5, in6, out, sel); | |
36 | ||
37 | input clk; | |
38 | input [39:0] in0, in1, in2, in3, in4, in5, in6; | |
39 | input [2:0] sel; | |
40 | output [39:0] out; | |
41 | ||
42 | reg [39:0] mux_out, out; | |
43 | ||
44 | always @(in0 or in1 or in2 or in3 or in4 or in5 or in6 or sel) | |
45 | case(sel) // synopsys parallel_case full_case | |
46 | 3'b000: mux_out = in0; | |
47 | 3'b001: mux_out = in1; | |
48 | 3'b010: mux_out = in2; | |
49 | 3'b011: mux_out = in3; | |
50 | 3'b100: mux_out = in4; | |
51 | 3'b101: mux_out = in5; | |
52 | 3'b110: mux_out = in6; | |
53 | default: mux_out = in0; | |
54 | endcase | |
55 | ||
56 | ||
57 | always @(posedge clk) | |
58 | out <= mux_out; | |
59 | ||
60 | endmodule |