design/sys/iop/rtx/rtl/rtx_dmo_mux.v

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// OpenSPARC T2 Processor File: rtx_dmo_mux.v
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module rtx_dmo_mux (clk, in0, in1, in2, in3, in4, in5, in6, out, sel);

input           clk;
input  [39:0]   in0, in1, in2, in3, in4, in5, in6;
input  [2:0]    sel;
output [39:0]  out;

reg [39:0]  mux_out, out;

always @(in0 or in1 or in2 or in3 or in4 or in5 or in6 or sel)
   case(sel) // synopsys parallel_case full_case
      3'b000: mux_out = in0;
      3'b001: mux_out = in1;
      3'b010: mux_out = in2;
      3'b011: mux_out = in3;
      3'b100: mux_out = in4;
      3'b101: mux_out = in5;
      3'b110: mux_out = in6;
     default: mux_out = in0;
   endcase


always @(posedge clk)
        out <= mux_out;

endmodule