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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_sbd_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_sbd_dp ( | |
36 | const_cpuid, | |
37 | lsu_va_m, | |
38 | exu_lsu_store_data_e, | |
39 | fgu_lsu_fst_data_fx1, | |
40 | tlb_pgnum_crit, | |
41 | tlb_tte_ie_b, | |
42 | sbc_st_int_sel_m, | |
43 | sbc_bst_offset, | |
44 | sbc_bst_in_prog_m, | |
45 | sbc_load_bst_addr, | |
46 | sec_st_sz_dw_std_le_b, | |
47 | sec_st_sz_dw_le_not_ie_b, | |
48 | sec_st_sz_dw_be_not_ie_b, | |
49 | sec_st_sz_word_le_not_ie_b, | |
50 | sec_st_sz_word_be_not_ie_b, | |
51 | sec_st_sz_hw_le_not_ie_b, | |
52 | sec_st_sz_hw_be_not_ie_b, | |
53 | sec_st_sz_dw_le_if_ie_b, | |
54 | sec_st_sz_dw_be_if_ie_b, | |
55 | sec_st_sz_word_le_if_ie_b, | |
56 | sec_st_sz_word_be_if_ie_b, | |
57 | sec_st_sz_hw_le_if_ie_b, | |
58 | sec_st_sz_hw_be_if_ie_b, | |
59 | sec_st_sz_byte_b, | |
60 | dcc_tid_m, | |
61 | dcc_asi_m, | |
62 | dcc_sbd_e_clken, | |
63 | dcc_sbd_m_clken, | |
64 | dcc_std_inst_m, | |
65 | dcc_fp32b_sel_m, | |
66 | dcc_asi_iomap_m, | |
67 | dcc_cache_diag_wr_m, | |
68 | dcc_demap_asi_m, | |
69 | dcc_ldstub_inst_m, | |
70 | stb_cam_data, | |
71 | dcs_memref_m, | |
72 | mbi_run, | |
73 | mbi_cambist_run, | |
74 | mbi_wdata, | |
75 | mbi_ptag_data, | |
76 | mbi_init_to_zero, | |
77 | mbi_cambist_shift, | |
78 | sbd_st_data_b, | |
79 | sbd_st_data2_b, | |
80 | sbd_st_datab_b, | |
81 | sbd_st_predata_b, | |
82 | sbd_st_addr_b, | |
83 | stb_st_addr_m, | |
84 | stb_st_addr_b, | |
85 | l2clk, | |
86 | scan_in, | |
87 | tcu_pce_ov, | |
88 | tcu_scan_en, | |
89 | spc_aclk, | |
90 | spc_bclk, | |
91 | scan_out); | |
92 | wire stop; | |
93 | wire se; | |
94 | wire pce_ov; | |
95 | wire siclk; | |
96 | wire soclk; | |
97 | wire dff_st_data_m_0_scanin; | |
98 | wire dff_st_data_m_0_scanout; | |
99 | wire [63:0] pre_st_data_m; | |
100 | wire dff_st_data_m_1_scanin; | |
101 | wire dff_st_data_m_1_scanout; | |
102 | wire ldstub_inst_m_0; | |
103 | wire ldstub_inst_m_1; | |
104 | wire [63:0] pre_st_data2_m; | |
105 | wire [63:0] st_data_m; | |
106 | wire dff_st_data_b_0_scanin; | |
107 | wire dff_st_data_b_0_scanout; | |
108 | wire [63:0] st_data_b; | |
109 | wire dff_st_data_b_1_scanin; | |
110 | wire dff_st_data_b_1_scanout; | |
111 | wire [7:0] byte0; | |
112 | wire [7:0] byte1; | |
113 | wire [7:0] byte2; | |
114 | wire [7:0] byte3; | |
115 | wire [7:0] byte4; | |
116 | wire [7:0] byte5; | |
117 | wire [7:0] byte6; | |
118 | wire [7:0] byte7; | |
119 | wire [63:0] st_data_ie0_b; | |
120 | wire [63:0] st_data_ie1_b; | |
121 | wire [39:3] st_addr_b; | |
122 | wire [39:3] bist_data; | |
123 | wire [39:6] bst_addr; | |
124 | wire [39:3] st_addr_m; | |
125 | wire dff_st_addr_scanin; | |
126 | wire dff_st_addr_scanout; | |
127 | wire dff_bst_addr_scanin; | |
128 | wire dff_bst_addr_scanout; | |
129 | ||
130 | ||
131 | input [2:0] const_cpuid; | |
132 | ||
133 | input [47:3] lsu_va_m; | |
134 | ||
135 | input [63:0] exu_lsu_store_data_e; | |
136 | ||
137 | input [63:0] fgu_lsu_fst_data_fx1; | |
138 | ||
139 | input [39:13] tlb_pgnum_crit; | |
140 | input tlb_tte_ie_b; | |
141 | ||
142 | input sbc_st_int_sel_m; | |
143 | input [2:0] sbc_bst_offset; | |
144 | input sbc_bst_in_prog_m; | |
145 | input sbc_load_bst_addr; | |
146 | ||
147 | input sec_st_sz_dw_std_le_b; | |
148 | input sec_st_sz_dw_le_not_ie_b; | |
149 | input sec_st_sz_dw_be_not_ie_b; | |
150 | input sec_st_sz_word_le_not_ie_b; | |
151 | input sec_st_sz_word_be_not_ie_b; | |
152 | input sec_st_sz_hw_le_not_ie_b; | |
153 | input sec_st_sz_hw_be_not_ie_b; | |
154 | input sec_st_sz_dw_le_if_ie_b; | |
155 | input sec_st_sz_dw_be_if_ie_b; | |
156 | input sec_st_sz_word_le_if_ie_b; | |
157 | input sec_st_sz_word_be_if_ie_b; | |
158 | input sec_st_sz_hw_le_if_ie_b; | |
159 | input sec_st_sz_hw_be_if_ie_b; | |
160 | input sec_st_sz_byte_b; | |
161 | ||
162 | input [2:0] dcc_tid_m; | |
163 | input [7:0] dcc_asi_m; | |
164 | input dcc_sbd_e_clken; | |
165 | input dcc_sbd_m_clken; | |
166 | input dcc_std_inst_m; | |
167 | input dcc_fp32b_sel_m; | |
168 | input dcc_asi_iomap_m; | |
169 | input dcc_cache_diag_wr_m; | |
170 | input dcc_demap_asi_m; | |
171 | input dcc_ldstub_inst_m; | |
172 | ||
173 | input [44:11] stb_cam_data; | |
174 | ||
175 | input dcs_memref_m; | |
176 | ||
177 | input mbi_run; | |
178 | input mbi_cambist_run; | |
179 | input [7:0] mbi_wdata; | |
180 | input mbi_ptag_data; | |
181 | input mbi_init_to_zero; | |
182 | input mbi_cambist_shift; | |
183 | ||
184 | output [63:0] sbd_st_data_b; // Final formatted data | |
185 | output [63:0] sbd_st_data2_b; // Final formatted data | |
186 | output [63:0] sbd_st_datab_b; // Final formatted data with bist | |
187 | output [47:0] sbd_st_predata_b; // Unformatted store data (ok for ASI writes) | |
188 | output [39:3] sbd_st_addr_b; | |
189 | output [39:3] stb_st_addr_m; | |
190 | output [39:13] stb_st_addr_b; | |
191 | ||
192 | // Globals | |
193 | input l2clk; | |
194 | input scan_in; | |
195 | input tcu_pce_ov; // scan signals | |
196 | input tcu_scan_en; | |
197 | input spc_aclk; | |
198 | input spc_bclk; | |
199 | output scan_out; | |
200 | ||
201 | // scan renames | |
202 | assign stop = 1'b0; | |
203 | // end scan | |
204 | ||
205 | lsu_sbd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 ( | |
206 | .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}), | |
207 | .dout({se,pce_ov,siclk,soclk}) | |
208 | ); | |
209 | ||
210 | //////////////////////////////////////////////////////////////////////////////// | |
211 | // Mux different sources of store data. FGU data gets muxed spearately in M | |
212 | // because it comes in that cycle. | |
213 | ||
214 | lsu_sbd_dp_msff_macro__mux_aope__ports_2__stack_32c__width_32 dff_st_data_m_0 ( | |
215 | .scan_in(dff_st_data_m_0_scanin), | |
216 | .scan_out(dff_st_data_m_0_scanout), | |
217 | .din0 (pre_st_data_m[31:0]), // std | |
218 | .din1 (exu_lsu_store_data_e[63:32]), // default | |
219 | .sel0 (dcc_std_inst_m), | |
220 | .dout (pre_st_data_m[63:32]), | |
221 | .clk (l2clk), | |
222 | .en (dcc_sbd_e_clken), | |
223 | .se(se), | |
224 | .siclk(siclk), | |
225 | .soclk(soclk), | |
226 | .pce_ov(pce_ov), | |
227 | .stop(stop) // enable on stores, second half of STD/CAS | |
228 | ); | |
229 | lsu_sbd_dp_msff_macro__mux_aope__ports_2__stack_32c__width_32 dff_st_data_m_1 ( | |
230 | .scan_in(dff_st_data_m_1_scanin), | |
231 | .scan_out(dff_st_data_m_1_scanout), | |
232 | .din0 (exu_lsu_store_data_e[31:0]), // std | |
233 | .din1 (exu_lsu_store_data_e[31:0]), // default | |
234 | .sel0 (dcc_std_inst_m), | |
235 | .dout (pre_st_data_m[31:0]), | |
236 | .clk (l2clk), | |
237 | .en (dcc_sbd_e_clken), | |
238 | .se(se), | |
239 | .siclk(siclk), | |
240 | .soclk(soclk), | |
241 | .pce_ov(pce_ov), | |
242 | .stop(stop) // enable on stores, second half of STD/CAS | |
243 | ); | |
244 | ||
245 | lsu_sbd_dp_buff_macro__rep_1__width_2 ldstub_buf ( | |
246 | .din ({2{dcc_ldstub_inst_m}}), | |
247 | .dout ({ldstub_inst_m_0,ldstub_inst_m_1}) | |
248 | ); | |
249 | ||
250 | lsu_sbd_dp_or_macro__ports_2__stack_32c__width_32 ldstub_or_0 ( | |
251 | .din0 (pre_st_data_m[63:32]), | |
252 | .din1 ({32{ldstub_inst_m_0}}), | |
253 | .dout (pre_st_data2_m[63:32]) | |
254 | ); | |
255 | ||
256 | lsu_sbd_dp_or_macro__ports_2__stack_32c__width_32 ldstub_or_1 ( | |
257 | .din0 (pre_st_data_m[31:0]), | |
258 | .din1 ({32{ldstub_inst_m_1}}), | |
259 | .dout (pre_st_data2_m[31:0]) | |
260 | ); | |
261 | ||
262 | lsu_sbd_dp_mux_macro__mux_aope__ports_4__stack_32c__width_32 mx_data_m_0 ( | |
263 | .din0 ({16'b0,lsu_va_m[47:32]}), | |
264 | .din1 (pre_st_data2_m[63:32]), | |
265 | .din2 (fgu_lsu_fst_data_fx1[63:32]), | |
266 | .din3 (fgu_lsu_fst_data_fx1[63:32]), | |
267 | .sel0 (dcc_demap_asi_m), | |
268 | .sel1 (sbc_st_int_sel_m), | |
269 | .sel2 (dcc_fp32b_sel_m), | |
270 | .dout (st_data_m[63:32]) | |
271 | ); | |
272 | lsu_sbd_dp_mux_macro__mux_aope__ports_4__stack_32c__width_32 mx_data_m_1 ( | |
273 | .din0 ({lsu_va_m[31:3],3'b0}), | |
274 | .din1 (pre_st_data2_m[31:0]), | |
275 | .din2 (fgu_lsu_fst_data_fx1[63:32]), | |
276 | .din3 (fgu_lsu_fst_data_fx1[31:0]), | |
277 | .sel0 (dcc_demap_asi_m), | |
278 | .sel1 (sbc_st_int_sel_m), | |
279 | .sel2 (dcc_fp32b_sel_m), | |
280 | .dout (st_data_m[31:0]) | |
281 | ); | |
282 | ||
283 | lsu_sbd_dp_msff_macro__stack_32c__width_32 dff_st_data_b_0 ( | |
284 | .scan_in(dff_st_data_b_0_scanin), | |
285 | .scan_out(dff_st_data_b_0_scanout), | |
286 | .din (st_data_m[63:32]), | |
287 | .dout (st_data_b[63:32]), | |
288 | .clk (l2clk), | |
289 | .en (dcc_sbd_m_clken), | |
290 | .se(se), | |
291 | .siclk(siclk), | |
292 | .soclk(soclk), | |
293 | .pce_ov(pce_ov), | |
294 | .stop(stop) | |
295 | ); | |
296 | lsu_sbd_dp_msff_macro__stack_32c__width_32 dff_st_data_b_1 ( | |
297 | .scan_in(dff_st_data_b_1_scanin), | |
298 | .scan_out(dff_st_data_b_1_scanout), | |
299 | .din (st_data_m[31:0]), | |
300 | .dout (st_data_b[31:0]), | |
301 | .clk (l2clk), | |
302 | .en (dcc_sbd_m_clken), | |
303 | .se(se), | |
304 | .siclk(siclk), | |
305 | .soclk(soclk), | |
306 | .pce_ov(pce_ov), | |
307 | .stop(stop) | |
308 | ); | |
309 | ||
310 | lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_16 st_predata_buf_0 ( | |
311 | .din (st_data_b[47:32]), | |
312 | .dout (sbd_st_predata_b[47:32]) | |
313 | ); | |
314 | lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_32 st_predata_buf_1 ( | |
315 | .din (st_data_b[31:0]), | |
316 | .dout (sbd_st_predata_b[31:0]) | |
317 | ); | |
318 | ||
319 | //////////////////////////////////////////////////////////////////////////////// | |
320 | // Little endian swapping and data fill | |
321 | ||
322 | assign byte0[7:0] = st_data_b[7:0]; | |
323 | assign byte1[7:0] = st_data_b[15:8]; | |
324 | assign byte2[7:0] = st_data_b[23:16]; | |
325 | assign byte3[7:0] = st_data_b[31:24]; | |
326 | assign byte4[7:0] = st_data_b[39:32]; | |
327 | assign byte5[7:0] = st_data_b[47:40]; | |
328 | assign byte6[7:0] = st_data_b[55:48]; | |
329 | assign byte7[7:0] = st_data_b[63:56]; | |
330 | ||
331 | // Replicate data of size <64b to fill the line. | |
332 | ||
333 | lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie0_0 ( | |
334 | .din0 ({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}), | |
335 | .din1 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}), | |
336 | .din2 ({byte7[7:0],byte6[7:0],byte5[7:0],byte4[7:0]}), | |
337 | .din3 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}), | |
338 | .din4 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}), | |
339 | .din5 ({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}), | |
340 | .din6 ({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}), | |
341 | .din7 ({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}), | |
342 | .sel0 (sec_st_sz_dw_std_le_b), | |
343 | .sel1 (sec_st_sz_dw_le_not_ie_b), | |
344 | .sel2 (sec_st_sz_dw_be_not_ie_b), | |
345 | .sel3 (sec_st_sz_word_le_not_ie_b), | |
346 | .sel4 (sec_st_sz_word_be_not_ie_b), | |
347 | .sel5 (sec_st_sz_hw_le_not_ie_b), | |
348 | .sel6 (sec_st_sz_hw_be_not_ie_b), | |
349 | .sel7 (sec_st_sz_byte_b), | |
350 | .dout (st_data_ie0_b[63:32]) | |
351 | ); | |
352 | ||
353 | lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie0_1 ( | |
354 | .din0 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}), | |
355 | .din1 ({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}), | |
356 | .din2 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}), | |
357 | .din3 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}), | |
358 | .din4 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}), | |
359 | .din5 ({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}), | |
360 | .din6 ({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}), | |
361 | .din7 ({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}), | |
362 | .sel0 (sec_st_sz_dw_std_le_b), | |
363 | .sel1 (sec_st_sz_dw_le_not_ie_b), | |
364 | .sel2 (sec_st_sz_dw_be_not_ie_b), | |
365 | .sel3 (sec_st_sz_word_le_not_ie_b), | |
366 | .sel4 (sec_st_sz_word_be_not_ie_b), | |
367 | .sel5 (sec_st_sz_hw_le_not_ie_b), | |
368 | .sel6 (sec_st_sz_hw_be_not_ie_b), | |
369 | .sel7 (sec_st_sz_byte_b), | |
370 | .dout (st_data_ie0_b[31:0]) | |
371 | ); | |
372 | ||
373 | lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie1_0 ( | |
374 | .din0 ({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}), | |
375 | .din1 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}), | |
376 | .din2 ({byte7[7:0],byte6[7:0],byte5[7:0],byte4[7:0]}), | |
377 | .din3 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}), | |
378 | .din4 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}), | |
379 | .din5 ({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}), | |
380 | .din6 ({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}), | |
381 | .din7 ({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}), | |
382 | .sel0 (sec_st_sz_dw_std_le_b), | |
383 | .sel1 (sec_st_sz_dw_le_if_ie_b), | |
384 | .sel2 (sec_st_sz_dw_be_if_ie_b), | |
385 | .sel3 (sec_st_sz_word_le_if_ie_b), | |
386 | .sel4 (sec_st_sz_word_be_if_ie_b), | |
387 | .sel5 (sec_st_sz_hw_le_if_ie_b), | |
388 | .sel6 (sec_st_sz_hw_be_if_ie_b), | |
389 | .sel7 (sec_st_sz_byte_b), | |
390 | .dout (st_data_ie1_b[63:32]) | |
391 | ); | |
392 | ||
393 | lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie1_1 ( | |
394 | .din0 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}), | |
395 | .din1 ({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}), | |
396 | .din2 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}), | |
397 | .din3 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}), | |
398 | .din4 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}), | |
399 | .din5 ({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}), | |
400 | .din6 ({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}), | |
401 | .din7 ({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}), | |
402 | .sel0 (sec_st_sz_dw_std_le_b), | |
403 | .sel1 (sec_st_sz_dw_le_if_ie_b), | |
404 | .sel2 (sec_st_sz_dw_be_if_ie_b), | |
405 | .sel3 (sec_st_sz_word_le_if_ie_b), | |
406 | .sel4 (sec_st_sz_word_be_if_ie_b), | |
407 | .sel5 (sec_st_sz_hw_le_if_ie_b), | |
408 | .sel6 (sec_st_sz_hw_be_if_ie_b), | |
409 | .sel7 (sec_st_sz_byte_b), | |
410 | .dout (st_data_ie1_b[31:0]) | |
411 | ); | |
412 | ||
413 | lsu_sbd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_endian_0 ( | |
414 | .din0 (st_data_ie1_b[63:32]), | |
415 | .din1 (st_data_ie0_b[63:32]), | |
416 | .sel0 (tlb_tte_ie_b), | |
417 | .dout (sbd_st_data_b[63:32]) | |
418 | ); | |
419 | lsu_sbd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_endian_1 ( | |
420 | .din0 (st_data_ie1_b[31:0]), | |
421 | .din1 (st_data_ie0_b[31:0]), | |
422 | .sel0 (tlb_tte_ie_b), | |
423 | .dout (sbd_st_data_b[31:0]) | |
424 | ); | |
425 | ||
426 | lsu_sbd_dp_buff_macro__dbuff_16x__rep_1__stack_32c__width_32 st_data_buf_0 ( | |
427 | .din (sbd_st_data_b[63:32]), | |
428 | .dout (sbd_st_data2_b[63:32]) | |
429 | ); | |
430 | lsu_sbd_dp_buff_macro__dbuff_16x__rep_1__stack_32c__width_32 st_data_buf_1 ( | |
431 | .din (sbd_st_data_b[31:0]), | |
432 | .dout (sbd_st_data2_b[31:0]) | |
433 | ); | |
434 | ||
435 | lsu_sbd_dp_mux_macro__mux_aope__ports_2__stack_32c__width_32 mx_bist_0 ( | |
436 | .din0 ({4{mbi_wdata[7:0]}}), | |
437 | .din1 (sbd_st_data2_b[63:32]), | |
438 | .sel0 (mbi_run), | |
439 | .dout (sbd_st_datab_b[63:32]) | |
440 | ); | |
441 | lsu_sbd_dp_mux_macro__mux_aope__ports_2__stack_32c__width_32 mx_bist_1 ( | |
442 | .din0 ({4{mbi_wdata[7:0]}}), | |
443 | .din1 (sbd_st_data2_b[31:0]), | |
444 | .sel0 (mbi_run), | |
445 | .dout (sbd_st_datab_b[31:0]) | |
446 | ); | |
447 | ||
448 | //////////////////////////////////////////////////////////////////////////////// | |
449 | // Block store address flop and address mux. | |
450 | // When a block store initiates, load the address in the mux. With each step of | |
451 | // the store, increment the address. Store addresses either come from the tlb | |
452 | // or from the block store address flop. | |
453 | ||
454 | lsu_sbd_dp_mux_macro__left_1__mux_aope__ports_4__stack_38l__width_37 sbd_bist_mux ( | |
455 | .din0 ({{36{1'b0}},1'b1}), | |
456 | .din1 ({st_addr_b[38:3],1'b0}), | |
457 | .din2 ({37{mbi_ptag_data}}), | |
458 | .din3 ({{4{mbi_wdata[7:0]}},mbi_wdata[7:3]}), | |
459 | .sel0 (mbi_init_to_zero), | |
460 | .sel1 (mbi_cambist_shift), | |
461 | .sel2 (mbi_cambist_run), | |
462 | .dout ({bist_data[39:3]}) | |
463 | ); | |
464 | ||
465 | // During Lbist, dcc_asi_iomap_m is forced high. This prevents the tlb_pgnum_crit | |
466 | // from propagating. | |
467 | lsu_sbd_dp_mux_macro__dmux_8x__left_1__mux_aope__ports_5__stack_38l__width_37 st_addr_mux ( | |
468 | .din0 (bist_data[39:3]), | |
469 | .din1 ({bst_addr[39:6],sbc_bst_offset[2:0]}), | |
470 | .din2 ({8'h90,const_cpuid[2:0],dcc_tid_m[2:0],dcc_asi_m[7:0],lsu_va_m[17:3]}), | |
471 | .din3 ({pre_st_data_m[30:2],lsu_va_m[10:3]}), | |
472 | .din4 ({tlb_pgnum_crit[39:13],lsu_va_m[12:3]}), | |
473 | .sel0 (mbi_run), | |
474 | .sel1 (sbc_bst_in_prog_m), | |
475 | .sel2 (dcc_asi_iomap_m), | |
476 | .sel3 (dcc_cache_diag_wr_m), | |
477 | .dout ({st_addr_m[39:3]}) | |
478 | ); | |
479 | ||
480 | assign stb_st_addr_m[39:3] = st_addr_m[39:3]; // to stb_cam | |
481 | ||
482 | lsu_sbd_dp_msff_macro__left_1__stack_38l__width_37 dff_st_addr ( | |
483 | .scan_in(dff_st_addr_scanin), | |
484 | .scan_out(dff_st_addr_scanout), | |
485 | .din (st_addr_m[39:3]), | |
486 | .dout (st_addr_b[39:3]), | |
487 | .clk (l2clk), | |
488 | .en (dcs_memref_m), | |
489 | .se(se), | |
490 | .siclk(siclk), | |
491 | .soclk(soclk), | |
492 | .pce_ov(pce_ov), | |
493 | .stop(stop) | |
494 | ); | |
495 | ||
496 | lsu_sbd_dp_buff_macro__left_1__rep_1__stack_38l__width_37 st_addr_b_buf ( | |
497 | .din (st_addr_b[39:3]), | |
498 | .dout (sbd_st_addr_b[39:3]) | |
499 | ); | |
500 | ||
501 | lsu_sbd_dp_buff_macro__left_10__rep_1__stack_40c__width_27 stb_st_addr_b_buf ( | |
502 | .din (st_addr_b[39:13]), | |
503 | .dout (stb_st_addr_b[39:13]) | |
504 | ); | |
505 | ||
506 | lsu_sbd_dp_msff_macro__left_4__minbuff_1__stack_38l__width_34 dff_bst_addr ( | |
507 | .scan_in(dff_bst_addr_scanin), | |
508 | .scan_out(dff_bst_addr_scanout), | |
509 | .din (stb_cam_data[44:11]), | |
510 | .dout (bst_addr[39:6]), | |
511 | .clk (l2clk), | |
512 | .en (sbc_load_bst_addr), | |
513 | .se(se), | |
514 | .siclk(siclk), | |
515 | .soclk(soclk), | |
516 | .pce_ov(pce_ov), | |
517 | .stop(stop) | |
518 | ); | |
519 | ||
520 | ||
521 | ||
522 | // fixscan start: | |
523 | assign dff_st_data_m_0_scanin = scan_in ; | |
524 | assign dff_st_data_m_1_scanin = dff_st_data_m_0_scanout ; | |
525 | assign dff_st_data_b_0_scanin = dff_st_data_m_1_scanout ; | |
526 | assign dff_st_data_b_1_scanin = dff_st_data_b_0_scanout ; | |
527 | assign dff_st_addr_scanin = dff_st_data_b_1_scanout ; | |
528 | assign dff_bst_addr_scanin = dff_st_addr_scanout ; | |
529 | assign scan_out = dff_bst_addr_scanout ; | |
530 | // fixscan end: | |
531 | endmodule | |
532 | ||
533 | ||
534 | ||
535 | // | |
536 | // buff macro | |
537 | // | |
538 | // | |
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | module lsu_sbd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 ( | |
545 | din, | |
546 | dout); | |
547 | input [3:0] din; | |
548 | output [3:0] dout; | |
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | ||
555 | buff #(4) d0_0 ( | |
556 | .in(din[3:0]), | |
557 | .out(dout[3:0]) | |
558 | ); | |
559 | ||
560 | ||
561 | ||
562 | ||
563 | ||
564 | ||
565 | ||
566 | ||
567 | endmodule | |
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | ||
574 | ||
575 | ||
576 | ||
577 | // any PARAMS parms go into naming of macro | |
578 | ||
579 | module lsu_sbd_dp_msff_macro__mux_aope__ports_2__stack_32c__width_32 ( | |
580 | din0, | |
581 | din1, | |
582 | sel0, | |
583 | clk, | |
584 | en, | |
585 | se, | |
586 | scan_in, | |
587 | siclk, | |
588 | soclk, | |
589 | pce_ov, | |
590 | stop, | |
591 | dout, | |
592 | scan_out); | |
593 | wire psel0; | |
594 | wire psel1; | |
595 | wire [31:0] muxout; | |
596 | wire l1clk; | |
597 | wire siclk_out; | |
598 | wire soclk_out; | |
599 | wire [30:0] so; | |
600 | ||
601 | input [31:0] din0; | |
602 | input [31:0] din1; | |
603 | input sel0; | |
604 | ||
605 | ||
606 | input clk; | |
607 | input en; | |
608 | input se; | |
609 | input scan_in; | |
610 | input siclk; | |
611 | input soclk; | |
612 | input pce_ov; | |
613 | input stop; | |
614 | ||
615 | ||
616 | ||
617 | output [31:0] dout; | |
618 | ||
619 | ||
620 | output scan_out; | |
621 | ||
622 | ||
623 | ||
624 | ||
625 | cl_dp1_penc2_8x c1_0 ( | |
626 | .sel0(sel0), | |
627 | .psel0(psel0), | |
628 | .psel1(psel1) | |
629 | ); | |
630 | ||
631 | mux2s #(32) d1_0 ( | |
632 | .sel0(psel0), | |
633 | .sel1(psel1), | |
634 | .in0(din0[31:0]), | |
635 | .in1(din1[31:0]), | |
636 | .dout(muxout[31:0]) | |
637 | ); | |
638 | cl_dp1_l1hdr_8x c0_0 ( | |
639 | .l2clk(clk), | |
640 | .pce(en), | |
641 | .aclk(siclk), | |
642 | .bclk(soclk), | |
643 | .l1clk(l1clk), | |
644 | .se(se), | |
645 | .pce_ov(pce_ov), | |
646 | .stop(stop), | |
647 | .siclk_out(siclk_out), | |
648 | .soclk_out(soclk_out) | |
649 | ); | |
650 | dff #(32) d0_0 ( | |
651 | .l1clk(l1clk), | |
652 | .siclk(siclk_out), | |
653 | .soclk(soclk_out), | |
654 | .d(muxout[31:0]), | |
655 | .si({scan_in,so[30:0]}), | |
656 | .so({so[30:0],scan_out}), | |
657 | .q(dout[31:0]) | |
658 | ); | |
659 | ||
660 | ||
661 | ||
662 | ||
663 | ||
664 | ||
665 | ||
666 | ||
667 | ||
668 | ||
669 | ||
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | ||
678 | ||
679 | endmodule | |
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | ||
688 | ||
689 | // | |
690 | // buff macro | |
691 | // | |
692 | // | |
693 | ||
694 | ||
695 | ||
696 | ||
697 | ||
698 | module lsu_sbd_dp_buff_macro__rep_1__width_2 ( | |
699 | din, | |
700 | dout); | |
701 | input [1:0] din; | |
702 | output [1:0] dout; | |
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | ||
709 | buff #(2) d0_0 ( | |
710 | .in(din[1:0]), | |
711 | .out(dout[1:0]) | |
712 | ); | |
713 | ||
714 | ||
715 | ||
716 | ||
717 | ||
718 | ||
719 | ||
720 | ||
721 | endmodule | |
722 | ||
723 | ||
724 | ||
725 | ||
726 | ||
727 | // | |
728 | // or macro for ports = 2,3 | |
729 | // | |
730 | // | |
731 | ||
732 | ||
733 | ||
734 | ||
735 | ||
736 | module lsu_sbd_dp_or_macro__ports_2__stack_32c__width_32 ( | |
737 | din0, | |
738 | din1, | |
739 | dout); | |
740 | input [31:0] din0; | |
741 | input [31:0] din1; | |
742 | output [31:0] dout; | |
743 | ||
744 | ||
745 | ||
746 | ||
747 | ||
748 | ||
749 | or2 #(32) d0_0 ( | |
750 | .in0(din0[31:0]), | |
751 | .in1(din1[31:0]), | |
752 | .out(dout[31:0]) | |
753 | ); | |
754 | ||
755 | ||
756 | ||
757 | ||
758 | ||
759 | ||
760 | ||
761 | ||
762 | ||
763 | endmodule | |
764 | ||
765 | ||
766 | ||
767 | ||
768 | ||
769 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
770 | // also for pass-gate with decoder | |
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | // any PARAMS parms go into naming of macro | |
777 | ||
778 | module lsu_sbd_dp_mux_macro__mux_aope__ports_4__stack_32c__width_32 ( | |
779 | din0, | |
780 | din1, | |
781 | din2, | |
782 | din3, | |
783 | sel0, | |
784 | sel1, | |
785 | sel2, | |
786 | dout); | |
787 | wire psel0; | |
788 | wire psel1; | |
789 | wire psel2; | |
790 | wire psel3; | |
791 | ||
792 | input [31:0] din0; | |
793 | input [31:0] din1; | |
794 | input [31:0] din2; | |
795 | input [31:0] din3; | |
796 | input sel0; | |
797 | input sel1; | |
798 | input sel2; | |
799 | output [31:0] dout; | |
800 | ||
801 | ||
802 | ||
803 | ||
804 | ||
805 | cl_dp1_penc4_8x c0_0 ( | |
806 | .test(1'b1), | |
807 | .sel0(sel0), | |
808 | .sel1(sel1), | |
809 | .sel2(sel2), | |
810 | .psel0(psel0), | |
811 | .psel1(psel1), | |
812 | .psel2(psel2), | |
813 | .psel3(psel3) | |
814 | ); | |
815 | ||
816 | mux4s #(32) d0_0 ( | |
817 | .sel0(psel0), | |
818 | .sel1(psel1), | |
819 | .sel2(psel2), | |
820 | .sel3(psel3), | |
821 | .in0(din0[31:0]), | |
822 | .in1(din1[31:0]), | |
823 | .in2(din2[31:0]), | |
824 | .in3(din3[31:0]), | |
825 | .dout(dout[31:0]) | |
826 | ); | |
827 | ||
828 | ||
829 | ||
830 | ||
831 | ||
832 | ||
833 | ||
834 | ||
835 | ||
836 | ||
837 | ||
838 | ||
839 | ||
840 | endmodule | |
841 | ||
842 | ||
843 | ||
844 | ||
845 | ||
846 | ||
847 | // any PARAMS parms go into naming of macro | |
848 | ||
849 | module lsu_sbd_dp_msff_macro__stack_32c__width_32 ( | |
850 | din, | |
851 | clk, | |
852 | en, | |
853 | se, | |
854 | scan_in, | |
855 | siclk, | |
856 | soclk, | |
857 | pce_ov, | |
858 | stop, | |
859 | dout, | |
860 | scan_out); | |
861 | wire l1clk; | |
862 | wire siclk_out; | |
863 | wire soclk_out; | |
864 | wire [30:0] so; | |
865 | ||
866 | input [31:0] din; | |
867 | ||
868 | ||
869 | input clk; | |
870 | input en; | |
871 | input se; | |
872 | input scan_in; | |
873 | input siclk; | |
874 | input soclk; | |
875 | input pce_ov; | |
876 | input stop; | |
877 | ||
878 | ||
879 | ||
880 | output [31:0] dout; | |
881 | ||
882 | ||
883 | output scan_out; | |
884 | ||
885 | ||
886 | ||
887 | ||
888 | cl_dp1_l1hdr_8x c0_0 ( | |
889 | .l2clk(clk), | |
890 | .pce(en), | |
891 | .aclk(siclk), | |
892 | .bclk(soclk), | |
893 | .l1clk(l1clk), | |
894 | .se(se), | |
895 | .pce_ov(pce_ov), | |
896 | .stop(stop), | |
897 | .siclk_out(siclk_out), | |
898 | .soclk_out(soclk_out) | |
899 | ); | |
900 | dff #(32) d0_0 ( | |
901 | .l1clk(l1clk), | |
902 | .siclk(siclk_out), | |
903 | .soclk(soclk_out), | |
904 | .d(din[31:0]), | |
905 | .si({scan_in,so[30:0]}), | |
906 | .so({so[30:0],scan_out}), | |
907 | .q(dout[31:0]) | |
908 | ); | |
909 | ||
910 | ||
911 | ||
912 | ||
913 | ||
914 | ||
915 | ||
916 | ||
917 | ||
918 | ||
919 | ||
920 | ||
921 | ||
922 | ||
923 | ||
924 | ||
925 | ||
926 | ||
927 | ||
928 | ||
929 | endmodule | |
930 | ||
931 | ||
932 | ||
933 | ||
934 | ||
935 | ||
936 | ||
937 | ||
938 | ||
939 | // | |
940 | // buff macro | |
941 | // | |
942 | // | |
943 | ||
944 | ||
945 | ||
946 | ||
947 | ||
948 | module lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_16 ( | |
949 | din, | |
950 | dout); | |
951 | input [15:0] din; | |
952 | output [15:0] dout; | |
953 | ||
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | buff #(16) d0_0 ( | |
960 | .in(din[15:0]), | |
961 | .out(dout[15:0]) | |
962 | ); | |
963 | ||
964 | ||
965 | ||
966 | ||
967 | ||
968 | ||
969 | ||
970 | ||
971 | endmodule | |
972 | ||
973 | ||
974 | ||
975 | ||
976 | ||
977 | // | |
978 | // buff macro | |
979 | // | |
980 | // | |
981 | ||
982 | ||
983 | ||
984 | ||
985 | ||
986 | module lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_32 ( | |
987 | din, | |
988 | dout); | |
989 | input [31:0] din; | |
990 | output [31:0] dout; | |
991 | ||
992 | ||
993 | ||
994 | ||
995 | ||
996 | ||
997 | buff #(32) d0_0 ( | |
998 | .in(din[31:0]), | |
999 | .out(dout[31:0]) | |
1000 | ); | |
1001 | ||
1002 | ||
1003 | ||
1004 | ||
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | endmodule | |
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | ||
1015 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1016 | // also for pass-gate with decoder | |
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | // any PARAMS parms go into naming of macro | |
1023 | ||
1024 | module lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 ( | |
1025 | din0, | |
1026 | sel0, | |
1027 | din1, | |
1028 | sel1, | |
1029 | din2, | |
1030 | sel2, | |
1031 | din3, | |
1032 | sel3, | |
1033 | din4, | |
1034 | sel4, | |
1035 | din5, | |
1036 | sel5, | |
1037 | din6, | |
1038 | sel6, | |
1039 | din7, | |
1040 | sel7, | |
1041 | dout); | |
1042 | wire buffout0; | |
1043 | wire buffout1; | |
1044 | wire buffout2; | |
1045 | wire buffout3; | |
1046 | wire buffout4; | |
1047 | wire buffout5; | |
1048 | wire buffout6; | |
1049 | wire buffout7; | |
1050 | ||
1051 | input [31:0] din0; | |
1052 | input sel0; | |
1053 | input [31:0] din1; | |
1054 | input sel1; | |
1055 | input [31:0] din2; | |
1056 | input sel2; | |
1057 | input [31:0] din3; | |
1058 | input sel3; | |
1059 | input [31:0] din4; | |
1060 | input sel4; | |
1061 | input [31:0] din5; | |
1062 | input sel5; | |
1063 | input [31:0] din6; | |
1064 | input sel6; | |
1065 | input [31:0] din7; | |
1066 | input sel7; | |
1067 | output [31:0] dout; | |
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | cl_dp1_muxbuff8_8x c0_0 ( | |
1074 | .in0(sel0), | |
1075 | .in1(sel1), | |
1076 | .in2(sel2), | |
1077 | .in3(sel3), | |
1078 | .in4(sel4), | |
1079 | .in5(sel5), | |
1080 | .in6(sel6), | |
1081 | .in7(sel7), | |
1082 | .out0(buffout0), | |
1083 | .out1(buffout1), | |
1084 | .out2(buffout2), | |
1085 | .out3(buffout3), | |
1086 | .out4(buffout4), | |
1087 | .out5(buffout5), | |
1088 | .out6(buffout6), | |
1089 | .out7(buffout7) | |
1090 | ); | |
1091 | mux8s #(32) d0_0 ( | |
1092 | .sel0(buffout0), | |
1093 | .sel1(buffout1), | |
1094 | .sel2(buffout2), | |
1095 | .sel3(buffout3), | |
1096 | .sel4(buffout4), | |
1097 | .sel5(buffout5), | |
1098 | .sel6(buffout6), | |
1099 | .sel7(buffout7), | |
1100 | .in0(din0[31:0]), | |
1101 | .in1(din1[31:0]), | |
1102 | .in2(din2[31:0]), | |
1103 | .in3(din3[31:0]), | |
1104 | .in4(din4[31:0]), | |
1105 | .in5(din5[31:0]), | |
1106 | .in6(din6[31:0]), | |
1107 | .in7(din7[31:0]), | |
1108 | .dout(dout[31:0]) | |
1109 | ); | |
1110 | ||
1111 | ||
1112 | ||
1113 | ||
1114 | ||
1115 | ||
1116 | ||
1117 | ||
1118 | ||
1119 | ||
1120 | ||
1121 | ||
1122 | ||
1123 | endmodule | |
1124 | ||
1125 | ||
1126 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1127 | // also for pass-gate with decoder | |
1128 | ||
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | // any PARAMS parms go into naming of macro | |
1134 | ||
1135 | module lsu_sbd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 ( | |
1136 | din0, | |
1137 | din1, | |
1138 | sel0, | |
1139 | dout); | |
1140 | wire psel0_unused; | |
1141 | wire psel1; | |
1142 | ||
1143 | input [31:0] din0; | |
1144 | input [31:0] din1; | |
1145 | input sel0; | |
1146 | output [31:0] dout; | |
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | cl_dp1_penc2_8x c0_0 ( | |
1153 | .sel0(sel0), | |
1154 | .psel0(psel0_unused), | |
1155 | .psel1(psel1) | |
1156 | ); | |
1157 | ||
1158 | mux2e #(32) d0_0 ( | |
1159 | .sel(psel1), | |
1160 | .in0(din0[31:0]), | |
1161 | .in1(din1[31:0]), | |
1162 | .dout(dout[31:0]) | |
1163 | ); | |
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | ||
1170 | ||
1171 | ||
1172 | ||
1173 | ||
1174 | ||
1175 | ||
1176 | ||
1177 | endmodule | |
1178 | ||
1179 | ||
1180 | // | |
1181 | // buff macro | |
1182 | // | |
1183 | // | |
1184 | ||
1185 | ||
1186 | ||
1187 | ||
1188 | ||
1189 | module lsu_sbd_dp_buff_macro__dbuff_16x__rep_1__stack_32c__width_32 ( | |
1190 | din, | |
1191 | dout); | |
1192 | input [31:0] din; | |
1193 | output [31:0] dout; | |
1194 | ||
1195 | ||
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | buff #(32) d0_0 ( | |
1201 | .in(din[31:0]), | |
1202 | .out(dout[31:0]) | |
1203 | ); | |
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | endmodule | |
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1219 | // also for pass-gate with decoder | |
1220 | ||
1221 | ||
1222 | ||
1223 | ||
1224 | ||
1225 | // any PARAMS parms go into naming of macro | |
1226 | ||
1227 | module lsu_sbd_dp_mux_macro__mux_aope__ports_2__stack_32c__width_32 ( | |
1228 | din0, | |
1229 | din1, | |
1230 | sel0, | |
1231 | dout); | |
1232 | wire psel0; | |
1233 | wire psel1; | |
1234 | ||
1235 | input [31:0] din0; | |
1236 | input [31:0] din1; | |
1237 | input sel0; | |
1238 | output [31:0] dout; | |
1239 | ||
1240 | ||
1241 | ||
1242 | ||
1243 | ||
1244 | cl_dp1_penc2_8x c0_0 ( | |
1245 | .sel0(sel0), | |
1246 | .psel0(psel0), | |
1247 | .psel1(psel1) | |
1248 | ); | |
1249 | ||
1250 | mux2s #(32) d0_0 ( | |
1251 | .sel0(psel0), | |
1252 | .sel1(psel1), | |
1253 | .in0(din0[31:0]), | |
1254 | .in1(din1[31:0]), | |
1255 | .dout(dout[31:0]) | |
1256 | ); | |
1257 | ||
1258 | ||
1259 | ||
1260 | ||
1261 | ||
1262 | ||
1263 | ||
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | ||
1269 | ||
1270 | endmodule | |
1271 | ||
1272 | ||
1273 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1274 | // also for pass-gate with decoder | |
1275 | ||
1276 | ||
1277 | ||
1278 | ||
1279 | ||
1280 | // any PARAMS parms go into naming of macro | |
1281 | ||
1282 | module lsu_sbd_dp_mux_macro__left_1__mux_aope__ports_4__stack_38l__width_37 ( | |
1283 | din0, | |
1284 | din1, | |
1285 | din2, | |
1286 | din3, | |
1287 | sel0, | |
1288 | sel1, | |
1289 | sel2, | |
1290 | dout); | |
1291 | wire psel0; | |
1292 | wire psel1; | |
1293 | wire psel2; | |
1294 | wire psel3; | |
1295 | ||
1296 | input [36:0] din0; | |
1297 | input [36:0] din1; | |
1298 | input [36:0] din2; | |
1299 | input [36:0] din3; | |
1300 | input sel0; | |
1301 | input sel1; | |
1302 | input sel2; | |
1303 | output [36:0] dout; | |
1304 | ||
1305 | ||
1306 | ||
1307 | ||
1308 | ||
1309 | cl_dp1_penc4_8x c0_0 ( | |
1310 | .test(1'b1), | |
1311 | .sel0(sel0), | |
1312 | .sel1(sel1), | |
1313 | .sel2(sel2), | |
1314 | .psel0(psel0), | |
1315 | .psel1(psel1), | |
1316 | .psel2(psel2), | |
1317 | .psel3(psel3) | |
1318 | ); | |
1319 | ||
1320 | mux4s #(37) d0_0 ( | |
1321 | .sel0(psel0), | |
1322 | .sel1(psel1), | |
1323 | .sel2(psel2), | |
1324 | .sel3(psel3), | |
1325 | .in0(din0[36:0]), | |
1326 | .in1(din1[36:0]), | |
1327 | .in2(din2[36:0]), | |
1328 | .in3(din3[36:0]), | |
1329 | .dout(dout[36:0]) | |
1330 | ); | |
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | ||
1343 | ||
1344 | endmodule | |
1345 | ||
1346 | ||
1347 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1348 | // also for pass-gate with decoder | |
1349 | ||
1350 | ||
1351 | ||
1352 | ||
1353 | ||
1354 | // any PARAMS parms go into naming of macro | |
1355 | ||
1356 | module lsu_sbd_dp_mux_macro__dmux_8x__left_1__mux_aope__ports_5__stack_38l__width_37 ( | |
1357 | din0, | |
1358 | din1, | |
1359 | din2, | |
1360 | din3, | |
1361 | din4, | |
1362 | sel0, | |
1363 | sel1, | |
1364 | sel2, | |
1365 | sel3, | |
1366 | dout); | |
1367 | wire psel0; | |
1368 | wire psel1; | |
1369 | wire psel2; | |
1370 | wire psel3; | |
1371 | wire psel4; | |
1372 | ||
1373 | input [36:0] din0; | |
1374 | input [36:0] din1; | |
1375 | input [36:0] din2; | |
1376 | input [36:0] din3; | |
1377 | input [36:0] din4; | |
1378 | input sel0; | |
1379 | input sel1; | |
1380 | input sel2; | |
1381 | input sel3; | |
1382 | output [36:0] dout; | |
1383 | ||
1384 | ||
1385 | ||
1386 | ||
1387 | ||
1388 | cl_dp1_penc5_8x c0_0 ( | |
1389 | .test(1'b1), | |
1390 | .sel0(sel0), | |
1391 | .sel1(sel1), | |
1392 | .sel2(sel2), | |
1393 | .sel3(sel3), | |
1394 | .psel0(psel0), | |
1395 | .psel1(psel1), | |
1396 | .psel2(psel2), | |
1397 | .psel3(psel3), | |
1398 | .psel4(psel4) | |
1399 | ); | |
1400 | ||
1401 | mux5s #(37) d0_0 ( | |
1402 | .sel0(psel0), | |
1403 | .sel1(psel1), | |
1404 | .sel2(psel2), | |
1405 | .sel3(psel3), | |
1406 | .sel4(psel4), | |
1407 | .in0(din0[36:0]), | |
1408 | .in1(din1[36:0]), | |
1409 | .in2(din2[36:0]), | |
1410 | .in3(din3[36:0]), | |
1411 | .in4(din4[36:0]), | |
1412 | .dout(dout[36:0]) | |
1413 | ); | |
1414 | ||
1415 | ||
1416 | ||
1417 | ||
1418 | ||
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | ||
1425 | ||
1426 | ||
1427 | endmodule | |
1428 | ||
1429 | ||
1430 | ||
1431 | ||
1432 | ||
1433 | ||
1434 | // any PARAMS parms go into naming of macro | |
1435 | ||
1436 | module lsu_sbd_dp_msff_macro__left_1__stack_38l__width_37 ( | |
1437 | din, | |
1438 | clk, | |
1439 | en, | |
1440 | se, | |
1441 | scan_in, | |
1442 | siclk, | |
1443 | soclk, | |
1444 | pce_ov, | |
1445 | stop, | |
1446 | dout, | |
1447 | scan_out); | |
1448 | wire l1clk; | |
1449 | wire siclk_out; | |
1450 | wire soclk_out; | |
1451 | wire [35:0] so; | |
1452 | ||
1453 | input [36:0] din; | |
1454 | ||
1455 | ||
1456 | input clk; | |
1457 | input en; | |
1458 | input se; | |
1459 | input scan_in; | |
1460 | input siclk; | |
1461 | input soclk; | |
1462 | input pce_ov; | |
1463 | input stop; | |
1464 | ||
1465 | ||
1466 | ||
1467 | output [36:0] dout; | |
1468 | ||
1469 | ||
1470 | output scan_out; | |
1471 | ||
1472 | ||
1473 | ||
1474 | ||
1475 | cl_dp1_l1hdr_8x c0_0 ( | |
1476 | .l2clk(clk), | |
1477 | .pce(en), | |
1478 | .aclk(siclk), | |
1479 | .bclk(soclk), | |
1480 | .l1clk(l1clk), | |
1481 | .se(se), | |
1482 | .pce_ov(pce_ov), | |
1483 | .stop(stop), | |
1484 | .siclk_out(siclk_out), | |
1485 | .soclk_out(soclk_out) | |
1486 | ); | |
1487 | dff #(37) d0_0 ( | |
1488 | .l1clk(l1clk), | |
1489 | .siclk(siclk_out), | |
1490 | .soclk(soclk_out), | |
1491 | .d(din[36:0]), | |
1492 | .si({scan_in,so[35:0]}), | |
1493 | .so({so[35:0],scan_out}), | |
1494 | .q(dout[36:0]) | |
1495 | ); | |
1496 | ||
1497 | ||
1498 | ||
1499 | ||
1500 | ||
1501 | ||
1502 | ||
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | ||
1508 | ||
1509 | ||
1510 | ||
1511 | ||
1512 | ||
1513 | ||
1514 | ||
1515 | ||
1516 | endmodule | |
1517 | ||
1518 | ||
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | // | |
1527 | // buff macro | |
1528 | // | |
1529 | // | |
1530 | ||
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | module lsu_sbd_dp_buff_macro__left_1__rep_1__stack_38l__width_37 ( | |
1536 | din, | |
1537 | dout); | |
1538 | input [36:0] din; | |
1539 | output [36:0] dout; | |
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | ||
1545 | ||
1546 | buff #(37) d0_0 ( | |
1547 | .in(din[36:0]), | |
1548 | .out(dout[36:0]) | |
1549 | ); | |
1550 | ||
1551 | ||
1552 | ||
1553 | ||
1554 | ||
1555 | ||
1556 | ||
1557 | ||
1558 | endmodule | |
1559 | ||
1560 | ||
1561 | ||
1562 | ||
1563 | ||
1564 | // | |
1565 | // buff macro | |
1566 | // | |
1567 | // | |
1568 | ||
1569 | ||
1570 | ||
1571 | ||
1572 | ||
1573 | module lsu_sbd_dp_buff_macro__left_10__rep_1__stack_40c__width_27 ( | |
1574 | din, | |
1575 | dout); | |
1576 | input [26:0] din; | |
1577 | output [26:0] dout; | |
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | ||
1583 | ||
1584 | buff #(27) d0_0 ( | |
1585 | .in(din[26:0]), | |
1586 | .out(dout[26:0]) | |
1587 | ); | |
1588 | ||
1589 | ||
1590 | ||
1591 | ||
1592 | ||
1593 | ||
1594 | ||
1595 | ||
1596 | endmodule | |
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | // any PARAMS parms go into naming of macro | |
1607 | ||
1608 | module lsu_sbd_dp_msff_macro__left_4__minbuff_1__stack_38l__width_34 ( | |
1609 | din, | |
1610 | clk, | |
1611 | en, | |
1612 | se, | |
1613 | scan_in, | |
1614 | siclk, | |
1615 | soclk, | |
1616 | pce_ov, | |
1617 | stop, | |
1618 | dout, | |
1619 | scan_out); | |
1620 | wire l1clk; | |
1621 | wire siclk_out; | |
1622 | wire soclk_out; | |
1623 | wire [32:0] so; | |
1624 | ||
1625 | input [33:0] din; | |
1626 | ||
1627 | ||
1628 | input clk; | |
1629 | input en; | |
1630 | input se; | |
1631 | input scan_in; | |
1632 | input siclk; | |
1633 | input soclk; | |
1634 | input pce_ov; | |
1635 | input stop; | |
1636 | ||
1637 | ||
1638 | ||
1639 | output [33:0] dout; | |
1640 | ||
1641 | ||
1642 | output scan_out; | |
1643 | ||
1644 | ||
1645 | ||
1646 | ||
1647 | cl_dp1_l1hdr_8x c0_0 ( | |
1648 | .l2clk(clk), | |
1649 | .pce(en), | |
1650 | .aclk(siclk), | |
1651 | .bclk(soclk), | |
1652 | .l1clk(l1clk), | |
1653 | .se(se), | |
1654 | .pce_ov(pce_ov), | |
1655 | .stop(stop), | |
1656 | .siclk_out(siclk_out), | |
1657 | .soclk_out(soclk_out) | |
1658 | ); | |
1659 | dff #(34) d0_0 ( | |
1660 | .l1clk(l1clk), | |
1661 | .siclk(siclk_out), | |
1662 | .soclk(soclk_out), | |
1663 | .d(din[33:0]), | |
1664 | .si({scan_in,so[32:0]}), | |
1665 | .so({so[32:0],scan_out}), | |
1666 | .q(dout[33:0]) | |
1667 | ); | |
1668 | ||
1669 | ||
1670 | ||
1671 | ||
1672 | ||
1673 | ||
1674 | ||
1675 | ||
1676 | ||
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | ||
1682 | ||
1683 | ||
1684 | ||
1685 | ||
1686 | ||
1687 | ||
1688 | endmodule | |
1689 | ||
1690 | ||
1691 | ||
1692 | ||
1693 | ||
1694 | ||
1695 | ||
1696 |