// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: lsu_sbd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
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// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
sec_st_sz_dw_le_not_ie_b,
sec_st_sz_dw_be_not_ie_b,
sec_st_sz_word_le_not_ie_b,
sec_st_sz_word_be_not_ie_b,
sec_st_sz_hw_le_not_ie_b,
sec_st_sz_hw_be_not_ie_b,
sec_st_sz_word_le_if_ie_b,
sec_st_sz_word_be_if_ie_b,
wire dff_st_data_m_0_scanin;
wire dff_st_data_m_0_scanout;
wire [63:0] pre_st_data_m;
wire dff_st_data_m_1_scanin;
wire dff_st_data_m_1_scanout;
wire [63:0] pre_st_data2_m;
wire dff_st_data_b_0_scanin;
wire dff_st_data_b_0_scanout;
wire dff_st_data_b_1_scanin;
wire dff_st_data_b_1_scanout;
wire [63:0] st_data_ie0_b;
wire [63:0] st_data_ie1_b;
wire dff_st_addr_scanout;
wire dff_bst_addr_scanin;
wire dff_bst_addr_scanout;
input [63:0] exu_lsu_store_data_e;
input [63:0] fgu_lsu_fst_data_fx1;
input [39:13] tlb_pgnum_crit;
input [2:0] sbc_bst_offset;
input sec_st_sz_dw_std_le_b;
input sec_st_sz_dw_le_not_ie_b;
input sec_st_sz_dw_be_not_ie_b;
input sec_st_sz_word_le_not_ie_b;
input sec_st_sz_word_be_not_ie_b;
input sec_st_sz_hw_le_not_ie_b;
input sec_st_sz_hw_be_not_ie_b;
input sec_st_sz_dw_le_if_ie_b;
input sec_st_sz_dw_be_if_ie_b;
input sec_st_sz_word_le_if_ie_b;
input sec_st_sz_word_be_if_ie_b;
input sec_st_sz_hw_le_if_ie_b;
input sec_st_sz_hw_be_if_ie_b;
input dcc_cache_diag_wr_m;
input [44:11] stb_cam_data;
output [63:0] sbd_st_data_b; // Final formatted data
output [63:0] sbd_st_data2_b; // Final formatted data
output [63:0] sbd_st_datab_b; // Final formatted data with bist
output [47:0] sbd_st_predata_b; // Unformatted store data (ok for ASI writes)
output [39:3] sbd_st_addr_b;
output [39:3] stb_st_addr_m;
output [39:13] stb_st_addr_b;
input tcu_pce_ov; // scan signals
lsu_sbd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 (
.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
////////////////////////////////////////////////////////////////////////////////
// Mux different sources of store data. FGU data gets muxed spearately in M
// because it comes in that cycle.
lsu_sbd_dp_msff_macro__mux_aope__ports_2__stack_32c__width_32 dff_st_data_m_0 (
.scan_in(dff_st_data_m_0_scanin),
.scan_out(dff_st_data_m_0_scanout),
.din0 (pre_st_data_m[31:0]), // std
.din1 (exu_lsu_store_data_e[63:32]), // default
.dout (pre_st_data_m[63:32]),
.stop(stop) // enable on stores, second half of STD/CAS
lsu_sbd_dp_msff_macro__mux_aope__ports_2__stack_32c__width_32 dff_st_data_m_1 (
.scan_in(dff_st_data_m_1_scanin),
.scan_out(dff_st_data_m_1_scanout),
.din0 (exu_lsu_store_data_e[31:0]), // std
.din1 (exu_lsu_store_data_e[31:0]), // default
.dout (pre_st_data_m[31:0]),
.stop(stop) // enable on stores, second half of STD/CAS
lsu_sbd_dp_buff_macro__rep_1__width_2 ldstub_buf (
.din ({2{dcc_ldstub_inst_m}}),
.dout ({ldstub_inst_m_0,ldstub_inst_m_1})
lsu_sbd_dp_or_macro__ports_2__stack_32c__width_32 ldstub_or_0 (
.din0 (pre_st_data_m[63:32]),
.din1 ({32{ldstub_inst_m_0}}),
.dout (pre_st_data2_m[63:32])
lsu_sbd_dp_or_macro__ports_2__stack_32c__width_32 ldstub_or_1 (
.din0 (pre_st_data_m[31:0]),
.din1 ({32{ldstub_inst_m_1}}),
.dout (pre_st_data2_m[31:0])
lsu_sbd_dp_mux_macro__mux_aope__ports_4__stack_32c__width_32 mx_data_m_0 (
.din0 ({16'b0,lsu_va_m[47:32]}),
.din1 (pre_st_data2_m[63:32]),
.din2 (fgu_lsu_fst_data_fx1[63:32]),
.din3 (fgu_lsu_fst_data_fx1[63:32]),
.sel1 (sbc_st_int_sel_m),
lsu_sbd_dp_mux_macro__mux_aope__ports_4__stack_32c__width_32 mx_data_m_1 (
.din0 ({lsu_va_m[31:3],3'b0}),
.din1 (pre_st_data2_m[31:0]),
.din2 (fgu_lsu_fst_data_fx1[63:32]),
.din3 (fgu_lsu_fst_data_fx1[31:0]),
.sel1 (sbc_st_int_sel_m),
lsu_sbd_dp_msff_macro__stack_32c__width_32 dff_st_data_b_0 (
.scan_in(dff_st_data_b_0_scanin),
.scan_out(dff_st_data_b_0_scanout),
.dout (st_data_b[63:32]),
lsu_sbd_dp_msff_macro__stack_32c__width_32 dff_st_data_b_1 (
.scan_in(dff_st_data_b_1_scanin),
.scan_out(dff_st_data_b_1_scanout),
lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_16 st_predata_buf_0 (
.dout (sbd_st_predata_b[47:32])
lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_32 st_predata_buf_1 (
.dout (sbd_st_predata_b[31:0])
////////////////////////////////////////////////////////////////////////////////
// Little endian swapping and data fill
assign byte0[7:0] = st_data_b[7:0];
assign byte1[7:0] = st_data_b[15:8];
assign byte2[7:0] = st_data_b[23:16];
assign byte3[7:0] = st_data_b[31:24];
assign byte4[7:0] = st_data_b[39:32];
assign byte5[7:0] = st_data_b[47:40];
assign byte6[7:0] = st_data_b[55:48];
assign byte7[7:0] = st_data_b[63:56];
// Replicate data of size <64b to fill the line.
lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie0_0 (
.din0 ({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}),
.din1 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
.din2 ({byte7[7:0],byte6[7:0],byte5[7:0],byte4[7:0]}),
.din3 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
.din4 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
.din5 ({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}),
.din6 ({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}),
.din7 ({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}),
.sel0 (sec_st_sz_dw_std_le_b),
.sel1 (sec_st_sz_dw_le_not_ie_b),
.sel2 (sec_st_sz_dw_be_not_ie_b),
.sel3 (sec_st_sz_word_le_not_ie_b),
.sel4 (sec_st_sz_word_be_not_ie_b),
.sel5 (sec_st_sz_hw_le_not_ie_b),
.sel6 (sec_st_sz_hw_be_not_ie_b),
.sel7 (sec_st_sz_byte_b),
.dout (st_data_ie0_b[63:32])
lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie0_1 (
.din0 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
.din1 ({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}),
.din2 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
.din3 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
.din4 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
.din5 ({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}),
.din6 ({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}),
.din7 ({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}),
.sel0 (sec_st_sz_dw_std_le_b),
.sel1 (sec_st_sz_dw_le_not_ie_b),
.sel2 (sec_st_sz_dw_be_not_ie_b),
.sel3 (sec_st_sz_word_le_not_ie_b),
.sel4 (sec_st_sz_word_be_not_ie_b),
.sel5 (sec_st_sz_hw_le_not_ie_b),
.sel6 (sec_st_sz_hw_be_not_ie_b),
.sel7 (sec_st_sz_byte_b),
.dout (st_data_ie0_b[31:0])
lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie1_0 (
.din0 ({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}),
.din1 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
.din2 ({byte7[7:0],byte6[7:0],byte5[7:0],byte4[7:0]}),
.din3 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
.din4 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
.din5 ({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}),
.din6 ({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}),
.din7 ({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}),
.sel0 (sec_st_sz_dw_std_le_b),
.sel1 (sec_st_sz_dw_le_if_ie_b),
.sel2 (sec_st_sz_dw_be_if_ie_b),
.sel3 (sec_st_sz_word_le_if_ie_b),
.sel4 (sec_st_sz_word_be_if_ie_b),
.sel5 (sec_st_sz_hw_le_if_ie_b),
.sel6 (sec_st_sz_hw_be_if_ie_b),
.sel7 (sec_st_sz_byte_b),
.dout (st_data_ie1_b[63:32])
lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie1_1 (
.din0 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
.din1 ({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}),
.din2 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
.din3 ({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
.din4 ({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
.din5 ({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}),
.din6 ({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}),
.din7 ({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}),
.sel0 (sec_st_sz_dw_std_le_b),
.sel1 (sec_st_sz_dw_le_if_ie_b),
.sel2 (sec_st_sz_dw_be_if_ie_b),
.sel3 (sec_st_sz_word_le_if_ie_b),
.sel4 (sec_st_sz_word_be_if_ie_b),
.sel5 (sec_st_sz_hw_le_if_ie_b),
.sel6 (sec_st_sz_hw_be_if_ie_b),
.sel7 (sec_st_sz_byte_b),
.dout (st_data_ie1_b[31:0])
lsu_sbd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_endian_0 (
.din0 (st_data_ie1_b[63:32]),
.din1 (st_data_ie0_b[63:32]),
.dout (sbd_st_data_b[63:32])
lsu_sbd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_endian_1 (
.din0 (st_data_ie1_b[31:0]),
.din1 (st_data_ie0_b[31:0]),
.dout (sbd_st_data_b[31:0])
lsu_sbd_dp_buff_macro__dbuff_16x__rep_1__stack_32c__width_32 st_data_buf_0 (
.din (sbd_st_data_b[63:32]),
.dout (sbd_st_data2_b[63:32])
lsu_sbd_dp_buff_macro__dbuff_16x__rep_1__stack_32c__width_32 st_data_buf_1 (
.din (sbd_st_data_b[31:0]),
.dout (sbd_st_data2_b[31:0])
lsu_sbd_dp_mux_macro__mux_aope__ports_2__stack_32c__width_32 mx_bist_0 (
.din0 ({4{mbi_wdata[7:0]}}),
.din1 (sbd_st_data2_b[63:32]),
.dout (sbd_st_datab_b[63:32])
lsu_sbd_dp_mux_macro__mux_aope__ports_2__stack_32c__width_32 mx_bist_1 (
.din0 ({4{mbi_wdata[7:0]}}),
.din1 (sbd_st_data2_b[31:0]),
.dout (sbd_st_datab_b[31:0])
////////////////////////////////////////////////////////////////////////////////
// Block store address flop and address mux.
// When a block store initiates, load the address in the mux. With each step of
// the store, increment the address. Store addresses either come from the tlb
// or from the block store address flop.
lsu_sbd_dp_mux_macro__left_1__mux_aope__ports_4__stack_38l__width_37 sbd_bist_mux (
.din0 ({{36{1'b0}},1'b1}),
.din1 ({st_addr_b[38:3],1'b0}),
.din2 ({37{mbi_ptag_data}}),
.din3 ({{4{mbi_wdata[7:0]}},mbi_wdata[7:3]}),
.sel0 (mbi_init_to_zero),
.sel1 (mbi_cambist_shift),
.dout ({bist_data[39:3]})
// During Lbist, dcc_asi_iomap_m is forced high. This prevents the tlb_pgnum_crit
lsu_sbd_dp_mux_macro__dmux_8x__left_1__mux_aope__ports_5__stack_38l__width_37 st_addr_mux (
.din1 ({bst_addr[39:6],sbc_bst_offset[2:0]}),
.din2 ({8'h90,const_cpuid[2:0],dcc_tid_m[2:0],dcc_asi_m[7:0],lsu_va_m[17:3]}),
.din3 ({pre_st_data_m[30:2],lsu_va_m[10:3]}),
.din4 ({tlb_pgnum_crit[39:13],lsu_va_m[12:3]}),
.sel1 (sbc_bst_in_prog_m),
.sel3 (dcc_cache_diag_wr_m),
.dout ({st_addr_m[39:3]})
assign stb_st_addr_m[39:3] = st_addr_m[39:3]; // to stb_cam
lsu_sbd_dp_msff_macro__left_1__stack_38l__width_37 dff_st_addr (
.scan_in(dff_st_addr_scanin),
.scan_out(dff_st_addr_scanout),
lsu_sbd_dp_buff_macro__left_1__rep_1__stack_38l__width_37 st_addr_b_buf (
.dout (sbd_st_addr_b[39:3])
lsu_sbd_dp_buff_macro__left_10__rep_1__stack_40c__width_27 stb_st_addr_b_buf (
.dout (stb_st_addr_b[39:13])
lsu_sbd_dp_msff_macro__left_4__minbuff_1__stack_38l__width_34 dff_bst_addr (
.scan_in(dff_bst_addr_scanin),
.scan_out(dff_bst_addr_scanout),
.din (stb_cam_data[44:11]),
assign dff_st_data_m_0_scanin = scan_in ;
assign dff_st_data_m_1_scanin = dff_st_data_m_0_scanout ;
assign dff_st_data_b_0_scanin = dff_st_data_m_1_scanout ;
assign dff_st_data_b_1_scanin = dff_st_data_b_0_scanout ;
assign dff_st_addr_scanin = dff_st_data_b_1_scanout ;
assign dff_bst_addr_scanin = dff_st_addr_scanout ;
assign scan_out = dff_bst_addr_scanout ;
module lsu_sbd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_msff_macro__mux_aope__ports_2__stack_32c__width_32 (
.so({so[30:0],scan_out}),
module lsu_sbd_dp_buff_macro__rep_1__width_2 (
// or macro for ports = 2,3
module lsu_sbd_dp_or_macro__ports_2__stack_32c__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_mux_macro__mux_aope__ports_4__stack_32c__width_32 (
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_msff_macro__stack_32c__width_32 (
.so({so[30:0],scan_out}),
module lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_16 (
module lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 (
cl_dp1_muxbuff8_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 (
module lsu_sbd_dp_buff_macro__dbuff_16x__rep_1__stack_32c__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_mux_macro__mux_aope__ports_2__stack_32c__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_mux_macro__left_1__mux_aope__ports_4__stack_38l__width_37 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_mux_macro__dmux_8x__left_1__mux_aope__ports_5__stack_38l__width_37 (
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_msff_macro__left_1__stack_38l__width_37 (
.so({so[35:0],scan_out}),
module lsu_sbd_dp_buff_macro__left_1__rep_1__stack_38l__width_37 (
module lsu_sbd_dp_buff_macro__left_10__rep_1__stack_40c__width_27 (
// any PARAMS parms go into naming of macro
module lsu_sbd_dp_msff_macro__left_4__minbuff_1__stack_38l__width_34 (
.so({so[32:0],scan_out}),