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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mmu_ase_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mmu_ase_dp ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | spc_aclk, | |
40 | spc_bclk, | |
41 | tcu_scan_en, | |
42 | tcu_dectest, | |
43 | tcu_muxtest, | |
44 | lsu_va_b, | |
45 | lsu_context_b, | |
46 | asi_rd_tsb_cfg_0_2, | |
47 | asi_rd_tsb_cfg_1_3, | |
48 | asi_rd_real_range, | |
49 | asi_rd_physical_offset, | |
50 | asi_sel_mra_0_in, | |
51 | asi_mra_wr_en_next, | |
52 | asi_mra_wr_data, | |
53 | asd0_rd_data, | |
54 | asd1_rd_data, | |
55 | asd0_itte_tag_data_, | |
56 | asd1_itte_tag_data_, | |
57 | asi_mbist_run, | |
58 | asi_ecc_cmpsel_in, | |
59 | asi_ase_cmpsel_in, | |
60 | asi_mbist_wdata, | |
61 | asi_ase_compare_data, | |
62 | mel0_parity, | |
63 | mel1_parity, | |
64 | scan_out, | |
65 | ase_mra_wr_data, | |
66 | ase_mra_wr_data_minbuf, | |
67 | ase_mra_rd_data, | |
68 | ase_lsu_va_w, | |
69 | ase_lsu_context_w, | |
70 | ase_mbd_mbist_data, | |
71 | mmu_itte_tag_data); | |
72 | wire en; | |
73 | wire clk; | |
74 | wire stop; | |
75 | wire test; | |
76 | wire pce_ov; | |
77 | wire se; | |
78 | wire siclk; | |
79 | wire soclk; | |
80 | wire lsu_context_w_lat_scanin; | |
81 | wire lsu_context_w_lat_scanout; | |
82 | wire [7:0] compare_data; | |
83 | wire [1:0] mbist_cmpsel; | |
84 | wire ecc_cmpsel; | |
85 | wire sel_mra_0; | |
86 | wire lsu_va_w_lat_scanin; | |
87 | wire lsu_va_w_lat_scanout; | |
88 | wire [47:13] lsu_va_w; | |
89 | wire [81:0] mra_rd_data; | |
90 | wire [60:54] wr_data_unused; | |
91 | wire wr_1_mux_scanin; | |
92 | wire wr_1_mux_scanout; | |
93 | wire wr_0_mux_scanin; | |
94 | wire wr_0_mux_scanout; | |
95 | wire [1:0] mra_parity; | |
96 | wire tcu_muxtest_rep0; | |
97 | ||
98 | ||
99 | ||
100 | input l2clk; | |
101 | input scan_in; | |
102 | input tcu_pce_ov; | |
103 | input spc_aclk; | |
104 | input spc_bclk; | |
105 | input tcu_scan_en; | |
106 | input tcu_dectest; | |
107 | input tcu_muxtest; | |
108 | ||
109 | input [47:0] lsu_va_b; | |
110 | input [12:0] lsu_context_b; | |
111 | ||
112 | input asi_rd_tsb_cfg_0_2; | |
113 | input asi_rd_tsb_cfg_1_3; | |
114 | input asi_rd_real_range; | |
115 | input asi_rd_physical_offset; | |
116 | input asi_sel_mra_0_in; | |
117 | input asi_mra_wr_en_next; | |
118 | ||
119 | input [63:0] asi_mra_wr_data; | |
120 | ||
121 | input [81:0] asd0_rd_data; | |
122 | input [81:0] asd1_rd_data; | |
123 | ||
124 | input [47:0] asd0_itte_tag_data_; | |
125 | input [47:0] asd1_itte_tag_data_; | |
126 | ||
127 | input asi_mbist_run; // MBIST | |
128 | input asi_ecc_cmpsel_in; // MBIST | |
129 | input [1:0] asi_ase_cmpsel_in; // MBIST | |
130 | input [7:0] asi_mbist_wdata; // MBIST | |
131 | input [7:0] asi_ase_compare_data; // MBIST | |
132 | input [1:0] mel0_parity; // MBIST | |
133 | input [1:0] mel1_parity; // MBIST | |
134 | ||
135 | ||
136 | ||
137 | output scan_out; | |
138 | ||
139 | output [81:0] ase_mra_wr_data; | |
140 | output [81:0] ase_mra_wr_data_minbuf; | |
141 | ||
142 | output [63:0] ase_mra_rd_data; | |
143 | ||
144 | output [47:13] ase_lsu_va_w; | |
145 | output [12:0] ase_lsu_context_w; | |
146 | ||
147 | output [31:0] ase_mbd_mbist_data; // MBIST | |
148 | ||
149 | output [47:0] mmu_itte_tag_data; | |
150 | ||
151 | ||
152 | ||
153 | ////////////////////////////////////////////////////////////////////// | |
154 | ||
155 | assign en = 1'b1; | |
156 | assign clk = l2clk; | |
157 | assign stop = 1'b0; | |
158 | assign test = tcu_dectest; | |
159 | ||
160 | mmu_ase_dp_buff_macro__width_4 clk_control_buf ( | |
161 | .din ({tcu_pce_ov , | |
162 | tcu_scan_en , | |
163 | spc_aclk , | |
164 | spc_bclk }), | |
165 | .dout ({pce_ov , | |
166 | se , | |
167 | siclk , | |
168 | soclk }) | |
169 | ); | |
170 | ||
171 | ||
172 | ||
173 | ||
174 | ||
175 | ||
176 | mmu_ase_dp_msff_macro__stack_58c__width_25 lsu_context_w_lat ( | |
177 | .scan_in(lsu_context_w_lat_scanin), | |
178 | .scan_out(lsu_context_w_lat_scanout), | |
179 | .din ({asi_ase_compare_data [7:0], | |
180 | asi_ase_cmpsel_in [1:0], | |
181 | asi_ecc_cmpsel_in , | |
182 | asi_sel_mra_0_in , | |
183 | lsu_context_b [12:0]}), | |
184 | .dout ({compare_data [7:0], | |
185 | mbist_cmpsel [1:0], | |
186 | ecc_cmpsel , | |
187 | sel_mra_0 , | |
188 | ase_lsu_context_w [12:0]}), | |
189 | .clk(clk), | |
190 | .en(en), | |
191 | .se(se), | |
192 | .siclk(siclk), | |
193 | .soclk(soclk), | |
194 | .pce_ov(pce_ov), | |
195 | .stop(stop) | |
196 | ); | |
197 | ||
198 | mmu_ase_dp_msff_macro__left_13__stack_58c__width_35 lsu_va_w_lat ( | |
199 | .scan_in(lsu_va_w_lat_scanin), | |
200 | .scan_out(lsu_va_w_lat_scanout), | |
201 | .din ({lsu_va_b [47:13]}), | |
202 | .dout ({lsu_va_w [47:13]}), | |
203 | .clk(clk), | |
204 | .en(en), | |
205 | .se(se), | |
206 | .siclk(siclk), | |
207 | .soclk(soclk), | |
208 | .pce_ov(pce_ov), | |
209 | .stop(stop) | |
210 | ); | |
211 | ||
212 | assign ase_lsu_va_w[47:13] = | |
213 | lsu_va_w[47:13]; | |
214 | ||
215 | ||
216 | ////////////////////////////////////////////////////////////////////// | |
217 | // | |
218 | // Mux the two thread groups together | |
219 | // | |
220 | mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_24 mra_rd_data_1_mux ( | |
221 | .din0 (asd0_rd_data [81:58]), | |
222 | .din1 (asd1_rd_data [81:58]), | |
223 | .sel0 (sel_mra_0 ), | |
224 | .dout (mra_rd_data [81:58]) | |
225 | ); | |
226 | ||
227 | mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_58 mra_rd_data_0_mux ( | |
228 | .din0 (asd0_rd_data [57:0] ), | |
229 | .din1 (asd1_rd_data [57:0] ), | |
230 | .sel0 (sel_mra_0 ), | |
231 | .dout (mra_rd_data [57:0] ) | |
232 | ); | |
233 | ||
234 | ||
235 | ||
236 | ||
237 | ////////////////////////////////////////////////////////////////////// | |
238 | // | |
239 | // Extract and format read data | |
240 | // | |
241 | ||
242 | mmu_ase_dp_mux_macro__mux_aonpe__ports_4__width_64 mra_rd_mux ( | |
243 | .din0 ({mra_rd_data [77:75], // TSB config 63:61 | |
244 | {21 {1'b0}} , | |
245 | mra_rd_data [74:48], // TSB config 39:13 | |
246 | { 4 {1'b0}} , | |
247 | mra_rd_data [47:39]}), // TSB config 08:00 | |
248 | .din1 ({mra_rd_data [38:36], // TSB config 63:61 | |
249 | {21 {1'b0}} , | |
250 | mra_rd_data [35:9], // TSB config 39:13 | |
251 | { 4 {1'b0}} , | |
252 | mra_rd_data [8:0]}), // TSB config 08:00 | |
253 | .din2 ({mra_rd_data [81 ], // Real range 63 | |
254 | { 9 {1'b0}} , | |
255 | mra_rd_data [80:27]}), // Real range 53:00 | |
256 | .din3 ({{24 {1'b0}} , | |
257 | mra_rd_data [26:0], // Physical offset 39:13 | |
258 | {13 {1'b0}} }), | |
259 | .sel0 (asi_rd_tsb_cfg_0_2 ), | |
260 | .sel1 (asi_rd_tsb_cfg_1_3 ), | |
261 | .sel2 (asi_rd_real_range ), | |
262 | .sel3 (asi_rd_physical_offset ), | |
263 | .dout (ase_mra_rd_data [63:0] ) | |
264 | ); | |
265 | ||
266 | ||
267 | ||
268 | ////////////////////////////////////////////////////////////////////// | |
269 | // | |
270 | // Modify data for write | |
271 | // | |
272 | ||
273 | assign wr_data_unused[60:54] = | |
274 | asi_mra_wr_data[60:54]; | |
275 | ||
276 | mmu_ase_dp_msff_macro__mux_aope__ports_4__stack_58c__width_24 wr_1_mux ( | |
277 | .scan_in(wr_1_mux_scanin), | |
278 | .scan_out(wr_1_mux_scanout), | |
279 | .din0 ({asi_mbist_wdata [1:0], // 81:80 | |
280 | asi_mbist_wdata [7:0], // 79:72 | |
281 | asi_mbist_wdata [7:0], // 71:64 | |
282 | asi_mbist_wdata [7:2]}), // 63:58 | |
283 | .din1 ({{4 {1'b0}} , // 81:78 | |
284 | asi_mra_wr_data [63:61], // TSB config 0,2 77:75 | |
285 | asi_mra_wr_data [39:29], // TSB config 0,2 74:64 | |
286 | asi_mra_wr_data [28:23]}), // TSB config 0,2 63:58 | |
287 | .din2 ({asi_mra_wr_data [63 ], // Real range 81 | |
288 | asi_mra_wr_data [53:31]}), // Real range 80:58 | |
289 | .din3 (mra_rd_data [81:58] ), | |
290 | .sel0 (asi_mbist_run ), | |
291 | .sel1 (asi_rd_tsb_cfg_0_2 ), | |
292 | .sel2 (asi_rd_real_range ), | |
293 | .en (asi_mra_wr_en_next ), | |
294 | .dout (ase_mra_wr_data [81:58] ), | |
295 | .clk(clk), | |
296 | .se(se), | |
297 | .siclk(siclk), | |
298 | .soclk(soclk), | |
299 | .pce_ov(pce_ov), | |
300 | .stop(stop) | |
301 | ); | |
302 | ||
303 | mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_24 wr_1_minbuf ( | |
304 | .din (ase_mra_wr_data[81:58]), | |
305 | .dout (ase_mra_wr_data_minbuf[81:58]) | |
306 | ); | |
307 | ||
308 | ||
309 | mmu_ase_dp_msff_macro__mux_aope__ports_5__stack_58c__width_58 wr_0_mux ( | |
310 | .scan_in(wr_0_mux_scanin), | |
311 | .scan_out(wr_0_mux_scanout), | |
312 | .din0 ({asi_mbist_wdata [1:0], | |
313 | {7 {asi_mbist_wdata [7:0]}}}), | |
314 | .din1 ({asi_mra_wr_data [22:13], // TSB config 0,2 57:48 | |
315 | asi_mra_wr_data [8:0], // TSB config 0,2 47:39 | |
316 | mra_rd_data [38:0]}), // TSB config 1,3 | |
317 | .din2 ({mra_rd_data [57:39], // TSB config 0,2 | |
318 | asi_mra_wr_data [63:61], // TSB config 1,3 38:36 | |
319 | asi_mra_wr_data [39:13], // TSB config 1,3 35:09 | |
320 | asi_mra_wr_data [8:0]}), // TSB config 1,3 08:00 | |
321 | .din3 ({asi_mra_wr_data [30:0], // Real range 57:27 | |
322 | mra_rd_data [26:0]}), // Physical offset | |
323 | .din4 ({mra_rd_data [57:27], // Real range | |
324 | asi_mra_wr_data [39:13]}), // Physical offset 26:00 | |
325 | .sel0 (asi_mbist_run ), | |
326 | .sel1 (asi_rd_tsb_cfg_0_2 ), | |
327 | .sel2 (asi_rd_tsb_cfg_1_3 ), | |
328 | .sel3 (asi_rd_real_range ), | |
329 | .en (asi_mra_wr_en_next ), | |
330 | .dout (ase_mra_wr_data [57:0] ), | |
331 | .clk(clk), | |
332 | .se(se), | |
333 | .siclk(siclk), | |
334 | .soclk(soclk), | |
335 | .pce_ov(pce_ov), | |
336 | .stop(stop) | |
337 | ); | |
338 | ||
339 | mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_58 wr_0_minbuf ( | |
340 | .din (ase_mra_wr_data[57:0]), | |
341 | .dout (ase_mra_wr_data_minbuf[57:0]) | |
342 | ); | |
343 | ||
344 | ||
345 | ||
346 | ////////////////////////////////////////////////////////////////////////////// | |
347 | // | |
348 | // Merge ITLB reload buses together | |
349 | // | |
350 | ||
351 | mmu_ase_dp_nand_macro__ports_2__stack_58c__width_48 itte_tag_data_nand ( | |
352 | .din0 (asd0_itte_tag_data_ [47:0] ), | |
353 | .din1 (asd1_itte_tag_data_ [47:0] ), | |
354 | .dout (mmu_itte_tag_data [47:0] ) | |
355 | ); | |
356 | ||
357 | ||
358 | ||
359 | ////////////////////////////////////////////////////////////////////////////// | |
360 | // | |
361 | // MBIST muxing | |
362 | // | |
363 | ||
364 | mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_2 mbist_ecc_mux ( | |
365 | .din0 (mel0_parity [1:0] ), | |
366 | .din1 (mel1_parity [1:0] ), | |
367 | .sel0 (ecc_cmpsel ), | |
368 | .dout (mra_parity [1:0] ) | |
369 | ); | |
370 | ||
371 | mmu_ase_dp_buff_macro__dbuff_32x__width_1 tst_mux_rep0 ( | |
372 | .din (tcu_muxtest ), | |
373 | .dout (tcu_muxtest_rep0 ) | |
374 | ); | |
375 | ||
376 | mmu_ase_dp_mux_macro__mux_pgdec__ports_8__stack_58c__width_32 mbist_mux ( | |
377 | .din0 (asd1_rd_data [31:0] ), | |
378 | .din1 (asd1_rd_data [63:32] ), | |
379 | .din2 ({compare_data [7:0], | |
380 | compare_data [7:2], | |
381 | asd1_rd_data [81:64]}), | |
382 | .din3 ({{3 {compare_data [7:0]}}, | |
383 | compare_data [7:4], | |
384 | mra_parity [1:0], | |
385 | compare_data [1:0]}), | |
386 | .din4 (asd0_rd_data [31:0] ), | |
387 | .din5 (asd0_rd_data [63:32] ), | |
388 | .din6 ({compare_data [7:0], | |
389 | compare_data [7:2], | |
390 | asd0_rd_data [81:64]}), | |
391 | .din7 ({{3 {compare_data [7:0]}}, | |
392 | compare_data [7:4], | |
393 | mra_parity [1:0], | |
394 | compare_data [1:0]}), | |
395 | .sel ({sel_mra_0 , | |
396 | mbist_cmpsel [1:0]}), | |
397 | .muxtst (tcu_muxtest_rep0 ), | |
398 | .dout (ase_mbd_mbist_data [31:0] ), | |
399 | .test(test) | |
400 | ); | |
401 | ||
402 | ||
403 | ||
404 | // fixscan start: | |
405 | assign lsu_context_w_lat_scanin = scan_in ; | |
406 | assign lsu_va_w_lat_scanin = lsu_context_w_lat_scanout; | |
407 | assign wr_1_mux_scanin = lsu_va_w_lat_scanout ; | |
408 | assign wr_0_mux_scanin = wr_1_mux_scanout ; | |
409 | assign scan_out = wr_0_mux_scanout ; | |
410 | // fixscan end: | |
411 | endmodule | |
412 | ||
413 | ||
414 | ||
415 | ||
416 | // | |
417 | // buff macro | |
418 | // | |
419 | // | |
420 | ||
421 | ||
422 | ||
423 | ||
424 | ||
425 | module mmu_ase_dp_buff_macro__width_4 ( | |
426 | din, | |
427 | dout); | |
428 | input [3:0] din; | |
429 | output [3:0] dout; | |
430 | ||
431 | ||
432 | ||
433 | ||
434 | ||
435 | ||
436 | buff #(4) d0_0 ( | |
437 | .in(din[3:0]), | |
438 | .out(dout[3:0]) | |
439 | ); | |
440 | ||
441 | ||
442 | ||
443 | ||
444 | ||
445 | ||
446 | ||
447 | ||
448 | endmodule | |
449 | ||
450 | ||
451 | ||
452 | ||
453 | ||
454 | ||
455 | ||
456 | ||
457 | ||
458 | // any PARAMS parms go into naming of macro | |
459 | ||
460 | module mmu_ase_dp_msff_macro__stack_58c__width_25 ( | |
461 | din, | |
462 | clk, | |
463 | en, | |
464 | se, | |
465 | scan_in, | |
466 | siclk, | |
467 | soclk, | |
468 | pce_ov, | |
469 | stop, | |
470 | dout, | |
471 | scan_out); | |
472 | wire l1clk; | |
473 | wire siclk_out; | |
474 | wire soclk_out; | |
475 | wire [23:0] so; | |
476 | ||
477 | input [24:0] din; | |
478 | ||
479 | ||
480 | input clk; | |
481 | input en; | |
482 | input se; | |
483 | input scan_in; | |
484 | input siclk; | |
485 | input soclk; | |
486 | input pce_ov; | |
487 | input stop; | |
488 | ||
489 | ||
490 | ||
491 | output [24:0] dout; | |
492 | ||
493 | ||
494 | output scan_out; | |
495 | ||
496 | ||
497 | ||
498 | ||
499 | cl_dp1_l1hdr_8x c0_0 ( | |
500 | .l2clk(clk), | |
501 | .pce(en), | |
502 | .aclk(siclk), | |
503 | .bclk(soclk), | |
504 | .l1clk(l1clk), | |
505 | .se(se), | |
506 | .pce_ov(pce_ov), | |
507 | .stop(stop), | |
508 | .siclk_out(siclk_out), | |
509 | .soclk_out(soclk_out) | |
510 | ); | |
511 | dff #(25) d0_0 ( | |
512 | .l1clk(l1clk), | |
513 | .siclk(siclk_out), | |
514 | .soclk(soclk_out), | |
515 | .d(din[24:0]), | |
516 | .si({scan_in,so[23:0]}), | |
517 | .so({so[23:0],scan_out}), | |
518 | .q(dout[24:0]) | |
519 | ); | |
520 | ||
521 | ||
522 | ||
523 | ||
524 | ||
525 | ||
526 | ||
527 | ||
528 | ||
529 | ||
530 | ||
531 | ||
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | ||
539 | ||
540 | endmodule | |
541 | ||
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | // any PARAMS parms go into naming of macro | |
555 | ||
556 | module mmu_ase_dp_msff_macro__left_13__stack_58c__width_35 ( | |
557 | din, | |
558 | clk, | |
559 | en, | |
560 | se, | |
561 | scan_in, | |
562 | siclk, | |
563 | soclk, | |
564 | pce_ov, | |
565 | stop, | |
566 | dout, | |
567 | scan_out); | |
568 | wire l1clk; | |
569 | wire siclk_out; | |
570 | wire soclk_out; | |
571 | wire [33:0] so; | |
572 | ||
573 | input [34:0] din; | |
574 | ||
575 | ||
576 | input clk; | |
577 | input en; | |
578 | input se; | |
579 | input scan_in; | |
580 | input siclk; | |
581 | input soclk; | |
582 | input pce_ov; | |
583 | input stop; | |
584 | ||
585 | ||
586 | ||
587 | output [34:0] dout; | |
588 | ||
589 | ||
590 | output scan_out; | |
591 | ||
592 | ||
593 | ||
594 | ||
595 | cl_dp1_l1hdr_8x c0_0 ( | |
596 | .l2clk(clk), | |
597 | .pce(en), | |
598 | .aclk(siclk), | |
599 | .bclk(soclk), | |
600 | .l1clk(l1clk), | |
601 | .se(se), | |
602 | .pce_ov(pce_ov), | |
603 | .stop(stop), | |
604 | .siclk_out(siclk_out), | |
605 | .soclk_out(soclk_out) | |
606 | ); | |
607 | dff #(35) d0_0 ( | |
608 | .l1clk(l1clk), | |
609 | .siclk(siclk_out), | |
610 | .soclk(soclk_out), | |
611 | .d(din[34:0]), | |
612 | .si({scan_in,so[33:0]}), | |
613 | .so({so[33:0],scan_out}), | |
614 | .q(dout[34:0]) | |
615 | ); | |
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | ||
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | endmodule | |
637 | ||
638 | ||
639 | ||
640 | ||
641 | ||
642 | ||
643 | ||
644 | ||
645 | ||
646 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
647 | // also for pass-gate with decoder | |
648 | ||
649 | ||
650 | ||
651 | ||
652 | ||
653 | // any PARAMS parms go into naming of macro | |
654 | ||
655 | module mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_24 ( | |
656 | din0, | |
657 | din1, | |
658 | sel0, | |
659 | dout); | |
660 | wire psel0; | |
661 | wire psel1; | |
662 | ||
663 | input [23:0] din0; | |
664 | input [23:0] din1; | |
665 | input sel0; | |
666 | output [23:0] dout; | |
667 | ||
668 | ||
669 | ||
670 | ||
671 | ||
672 | cl_dp1_penc2_8x c0_0 ( | |
673 | .sel0(sel0), | |
674 | .psel0(psel0), | |
675 | .psel1(psel1) | |
676 | ); | |
677 | ||
678 | mux2s #(24) d0_0 ( | |
679 | .sel0(psel0), | |
680 | .sel1(psel1), | |
681 | .in0(din0[23:0]), | |
682 | .in1(din1[23:0]), | |
683 | .dout(dout[23:0]) | |
684 | ); | |
685 | ||
686 | ||
687 | ||
688 | ||
689 | ||
690 | ||
691 | ||
692 | ||
693 | ||
694 | ||
695 | ||
696 | ||
697 | ||
698 | endmodule | |
699 | ||
700 | ||
701 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
702 | // also for pass-gate with decoder | |
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | // any PARAMS parms go into naming of macro | |
709 | ||
710 | module mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_58 ( | |
711 | din0, | |
712 | din1, | |
713 | sel0, | |
714 | dout); | |
715 | wire psel0; | |
716 | wire psel1; | |
717 | ||
718 | input [57:0] din0; | |
719 | input [57:0] din1; | |
720 | input sel0; | |
721 | output [57:0] dout; | |
722 | ||
723 | ||
724 | ||
725 | ||
726 | ||
727 | cl_dp1_penc2_8x c0_0 ( | |
728 | .sel0(sel0), | |
729 | .psel0(psel0), | |
730 | .psel1(psel1) | |
731 | ); | |
732 | ||
733 | mux2s #(58) d0_0 ( | |
734 | .sel0(psel0), | |
735 | .sel1(psel1), | |
736 | .in0(din0[57:0]), | |
737 | .in1(din1[57:0]), | |
738 | .dout(dout[57:0]) | |
739 | ); | |
740 | ||
741 | ||
742 | ||
743 | ||
744 | ||
745 | ||
746 | ||
747 | ||
748 | ||
749 | ||
750 | ||
751 | ||
752 | ||
753 | endmodule | |
754 | ||
755 | ||
756 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
757 | // also for pass-gate with decoder | |
758 | ||
759 | ||
760 | ||
761 | ||
762 | ||
763 | // any PARAMS parms go into naming of macro | |
764 | ||
765 | module mmu_ase_dp_mux_macro__mux_aonpe__ports_4__width_64 ( | |
766 | din0, | |
767 | sel0, | |
768 | din1, | |
769 | sel1, | |
770 | din2, | |
771 | sel2, | |
772 | din3, | |
773 | sel3, | |
774 | dout); | |
775 | wire buffout0; | |
776 | wire buffout1; | |
777 | wire buffout2; | |
778 | wire buffout3; | |
779 | ||
780 | input [63:0] din0; | |
781 | input sel0; | |
782 | input [63:0] din1; | |
783 | input sel1; | |
784 | input [63:0] din2; | |
785 | input sel2; | |
786 | input [63:0] din3; | |
787 | input sel3; | |
788 | output [63:0] dout; | |
789 | ||
790 | ||
791 | ||
792 | ||
793 | ||
794 | cl_dp1_muxbuff4_8x c0_0 ( | |
795 | .in0(sel0), | |
796 | .in1(sel1), | |
797 | .in2(sel2), | |
798 | .in3(sel3), | |
799 | .out0(buffout0), | |
800 | .out1(buffout1), | |
801 | .out2(buffout2), | |
802 | .out3(buffout3) | |
803 | ); | |
804 | mux4s #(64) d0_0 ( | |
805 | .sel0(buffout0), | |
806 | .sel1(buffout1), | |
807 | .sel2(buffout2), | |
808 | .sel3(buffout3), | |
809 | .in0(din0[63:0]), | |
810 | .in1(din1[63:0]), | |
811 | .in2(din2[63:0]), | |
812 | .in3(din3[63:0]), | |
813 | .dout(dout[63:0]) | |
814 | ); | |
815 | ||
816 | ||
817 | ||
818 | ||
819 | ||
820 | ||
821 | ||
822 | ||
823 | ||
824 | ||
825 | ||
826 | ||
827 | ||
828 | endmodule | |
829 | ||
830 | ||
831 | ||
832 | ||
833 | ||
834 | ||
835 | // any PARAMS parms go into naming of macro | |
836 | ||
837 | module mmu_ase_dp_msff_macro__mux_aope__ports_4__stack_58c__width_24 ( | |
838 | din0, | |
839 | din1, | |
840 | din2, | |
841 | din3, | |
842 | sel0, | |
843 | sel1, | |
844 | sel2, | |
845 | clk, | |
846 | en, | |
847 | se, | |
848 | scan_in, | |
849 | siclk, | |
850 | soclk, | |
851 | pce_ov, | |
852 | stop, | |
853 | dout, | |
854 | scan_out); | |
855 | wire psel0; | |
856 | wire psel1; | |
857 | wire psel2; | |
858 | wire psel3; | |
859 | wire [23:0] muxout; | |
860 | wire l1clk; | |
861 | wire siclk_out; | |
862 | wire soclk_out; | |
863 | wire [22:0] so; | |
864 | ||
865 | input [23:0] din0; | |
866 | input [23:0] din1; | |
867 | input [23:0] din2; | |
868 | input [23:0] din3; | |
869 | input sel0; | |
870 | input sel1; | |
871 | input sel2; | |
872 | ||
873 | ||
874 | input clk; | |
875 | input en; | |
876 | input se; | |
877 | input scan_in; | |
878 | input siclk; | |
879 | input soclk; | |
880 | input pce_ov; | |
881 | input stop; | |
882 | ||
883 | ||
884 | ||
885 | output [23:0] dout; | |
886 | ||
887 | ||
888 | output scan_out; | |
889 | ||
890 | ||
891 | ||
892 | ||
893 | cl_dp1_penc4_8x c1_0 ( | |
894 | .test(1'b1), | |
895 | .sel0(sel0), | |
896 | .sel1(sel1), | |
897 | .sel2(sel2), | |
898 | .psel0(psel0), | |
899 | .psel1(psel1), | |
900 | .psel2(psel2), | |
901 | .psel3(psel3) | |
902 | ); | |
903 | ||
904 | mux4s #(24) d1_0 ( | |
905 | .sel0(psel0), | |
906 | .sel1(psel1), | |
907 | .sel2(psel2), | |
908 | .sel3(psel3), | |
909 | .in0(din0[23:0]), | |
910 | .in1(din1[23:0]), | |
911 | .in2(din2[23:0]), | |
912 | .in3(din3[23:0]), | |
913 | .dout(muxout[23:0]) | |
914 | ); | |
915 | cl_dp1_l1hdr_8x c0_0 ( | |
916 | .l2clk(clk), | |
917 | .pce(en), | |
918 | .aclk(siclk), | |
919 | .bclk(soclk), | |
920 | .l1clk(l1clk), | |
921 | .se(se), | |
922 | .pce_ov(pce_ov), | |
923 | .stop(stop), | |
924 | .siclk_out(siclk_out), | |
925 | .soclk_out(soclk_out) | |
926 | ); | |
927 | dff #(24) d0_0 ( | |
928 | .l1clk(l1clk), | |
929 | .siclk(siclk_out), | |
930 | .soclk(soclk_out), | |
931 | .d(muxout[23:0]), | |
932 | .si({scan_in,so[22:0]}), | |
933 | .so({so[22:0],scan_out}), | |
934 | .q(dout[23:0]) | |
935 | ); | |
936 | ||
937 | ||
938 | ||
939 | ||
940 | ||
941 | ||
942 | ||
943 | ||
944 | ||
945 | ||
946 | ||
947 | ||
948 | ||
949 | ||
950 | ||
951 | ||
952 | ||
953 | ||
954 | ||
955 | ||
956 | endmodule | |
957 | ||
958 | ||
959 | ||
960 | ||
961 | ||
962 | ||
963 | ||
964 | ||
965 | ||
966 | // | |
967 | // buff macro | |
968 | // | |
969 | // | |
970 | ||
971 | ||
972 | ||
973 | ||
974 | ||
975 | module mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_24 ( | |
976 | din, | |
977 | dout); | |
978 | input [23:0] din; | |
979 | output [23:0] dout; | |
980 | ||
981 | ||
982 | ||
983 | ||
984 | ||
985 | ||
986 | buff #(24) d0_0 ( | |
987 | .in(din[23:0]), | |
988 | .out(dout[23:0]) | |
989 | ); | |
990 | ||
991 | ||
992 | ||
993 | ||
994 | ||
995 | ||
996 | ||
997 | ||
998 | endmodule | |
999 | ||
1000 | ||
1001 | ||
1002 | ||
1003 | ||
1004 | ||
1005 | ||
1006 | ||
1007 | ||
1008 | // any PARAMS parms go into naming of macro | |
1009 | ||
1010 | module mmu_ase_dp_msff_macro__mux_aope__ports_5__stack_58c__width_58 ( | |
1011 | din0, | |
1012 | din1, | |
1013 | din2, | |
1014 | din3, | |
1015 | din4, | |
1016 | sel0, | |
1017 | sel1, | |
1018 | sel2, | |
1019 | sel3, | |
1020 | clk, | |
1021 | en, | |
1022 | se, | |
1023 | scan_in, | |
1024 | siclk, | |
1025 | soclk, | |
1026 | pce_ov, | |
1027 | stop, | |
1028 | dout, | |
1029 | scan_out); | |
1030 | wire psel0; | |
1031 | wire psel1; | |
1032 | wire psel2; | |
1033 | wire psel3; | |
1034 | wire psel4; | |
1035 | wire [57:0] muxout; | |
1036 | wire l1clk; | |
1037 | wire siclk_out; | |
1038 | wire soclk_out; | |
1039 | wire [56:0] so; | |
1040 | ||
1041 | input [57:0] din0; | |
1042 | input [57:0] din1; | |
1043 | input [57:0] din2; | |
1044 | input [57:0] din3; | |
1045 | input [57:0] din4; | |
1046 | input sel0; | |
1047 | input sel1; | |
1048 | input sel2; | |
1049 | input sel3; | |
1050 | ||
1051 | ||
1052 | input clk; | |
1053 | input en; | |
1054 | input se; | |
1055 | input scan_in; | |
1056 | input siclk; | |
1057 | input soclk; | |
1058 | input pce_ov; | |
1059 | input stop; | |
1060 | ||
1061 | ||
1062 | ||
1063 | output [57:0] dout; | |
1064 | ||
1065 | ||
1066 | output scan_out; | |
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | cl_dp1_penc5_8x c1_0 ( | |
1072 | .test(1'b1), | |
1073 | .sel0(sel0), | |
1074 | .sel1(sel1), | |
1075 | .sel2(sel2), | |
1076 | .sel3(sel3), | |
1077 | .psel0(psel0), | |
1078 | .psel1(psel1), | |
1079 | .psel2(psel2), | |
1080 | .psel3(psel3), | |
1081 | .psel4(psel4) | |
1082 | ); | |
1083 | ||
1084 | mux5s #(58) d1_0 ( | |
1085 | .sel0(psel0), | |
1086 | .sel1(psel1), | |
1087 | .sel2(psel2), | |
1088 | .sel3(psel3), | |
1089 | .sel4(psel4), | |
1090 | .in0(din0[57:0]), | |
1091 | .in1(din1[57:0]), | |
1092 | .in2(din2[57:0]), | |
1093 | .in3(din3[57:0]), | |
1094 | .in4(din4[57:0]), | |
1095 | .dout(muxout[57:0]) | |
1096 | ); | |
1097 | cl_dp1_l1hdr_8x c0_0 ( | |
1098 | .l2clk(clk), | |
1099 | .pce(en), | |
1100 | .aclk(siclk), | |
1101 | .bclk(soclk), | |
1102 | .l1clk(l1clk), | |
1103 | .se(se), | |
1104 | .pce_ov(pce_ov), | |
1105 | .stop(stop), | |
1106 | .siclk_out(siclk_out), | |
1107 | .soclk_out(soclk_out) | |
1108 | ); | |
1109 | dff #(58) d0_0 ( | |
1110 | .l1clk(l1clk), | |
1111 | .siclk(siclk_out), | |
1112 | .soclk(soclk_out), | |
1113 | .d(muxout[57:0]), | |
1114 | .si({scan_in,so[56:0]}), | |
1115 | .so({so[56:0],scan_out}), | |
1116 | .q(dout[57:0]) | |
1117 | ); | |
1118 | ||
1119 | ||
1120 | ||
1121 | ||
1122 | ||
1123 | ||
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | ||
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | endmodule | |
1139 | ||
1140 | ||
1141 | ||
1142 | ||
1143 | ||
1144 | ||
1145 | ||
1146 | ||
1147 | ||
1148 | // | |
1149 | // buff macro | |
1150 | // | |
1151 | // | |
1152 | ||
1153 | ||
1154 | ||
1155 | ||
1156 | ||
1157 | module mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_58 ( | |
1158 | din, | |
1159 | dout); | |
1160 | input [57:0] din; | |
1161 | output [57:0] dout; | |
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | buff #(58) d0_0 ( | |
1169 | .in(din[57:0]), | |
1170 | .out(dout[57:0]) | |
1171 | ); | |
1172 | ||
1173 | ||
1174 | ||
1175 | ||
1176 | ||
1177 | ||
1178 | ||
1179 | ||
1180 | endmodule | |
1181 | ||
1182 | ||
1183 | ||
1184 | ||
1185 | ||
1186 | // | |
1187 | // nand macro for ports = 2,3,4 | |
1188 | // | |
1189 | // | |
1190 | ||
1191 | ||
1192 | ||
1193 | ||
1194 | ||
1195 | module mmu_ase_dp_nand_macro__ports_2__stack_58c__width_48 ( | |
1196 | din0, | |
1197 | din1, | |
1198 | dout); | |
1199 | input [47:0] din0; | |
1200 | input [47:0] din1; | |
1201 | output [47:0] dout; | |
1202 | ||
1203 | ||
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | nand2 #(48) d0_0 ( | |
1209 | .in0(din0[47:0]), | |
1210 | .in1(din1[47:0]), | |
1211 | .out(dout[47:0]) | |
1212 | ); | |
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | ||
1220 | ||
1221 | ||
1222 | endmodule | |
1223 | ||
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1229 | // also for pass-gate with decoder | |
1230 | ||
1231 | ||
1232 | ||
1233 | ||
1234 | ||
1235 | // any PARAMS parms go into naming of macro | |
1236 | ||
1237 | module mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_2 ( | |
1238 | din0, | |
1239 | din1, | |
1240 | sel0, | |
1241 | dout); | |
1242 | wire psel0; | |
1243 | wire psel1; | |
1244 | ||
1245 | input [1:0] din0; | |
1246 | input [1:0] din1; | |
1247 | input sel0; | |
1248 | output [1:0] dout; | |
1249 | ||
1250 | ||
1251 | ||
1252 | ||
1253 | ||
1254 | cl_dp1_penc2_8x c0_0 ( | |
1255 | .sel0(sel0), | |
1256 | .psel0(psel0), | |
1257 | .psel1(psel1) | |
1258 | ); | |
1259 | ||
1260 | mux2s #(2) d0_0 ( | |
1261 | .sel0(psel0), | |
1262 | .sel1(psel1), | |
1263 | .in0(din0[1:0]), | |
1264 | .in1(din1[1:0]), | |
1265 | .dout(dout[1:0]) | |
1266 | ); | |
1267 | ||
1268 | ||
1269 | ||
1270 | ||
1271 | ||
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | ||
1278 | ||
1279 | ||
1280 | endmodule | |
1281 | ||
1282 | ||
1283 | // | |
1284 | // buff macro | |
1285 | // | |
1286 | // | |
1287 | ||
1288 | ||
1289 | ||
1290 | ||
1291 | ||
1292 | module mmu_ase_dp_buff_macro__dbuff_32x__width_1 ( | |
1293 | din, | |
1294 | dout); | |
1295 | input [0:0] din; | |
1296 | output [0:0] dout; | |
1297 | ||
1298 | ||
1299 | ||
1300 | ||
1301 | ||
1302 | ||
1303 | buff #(1) d0_0 ( | |
1304 | .in(din[0:0]), | |
1305 | .out(dout[0:0]) | |
1306 | ); | |
1307 | ||
1308 | ||
1309 | ||
1310 | ||
1311 | ||
1312 | ||
1313 | ||
1314 | ||
1315 | endmodule | |
1316 | ||
1317 | ||
1318 | ||
1319 | ||
1320 | ||
1321 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1322 | // also for pass-gate with decoder | |
1323 | ||
1324 | ||
1325 | ||
1326 | ||
1327 | ||
1328 | // any PARAMS parms go into naming of macro | |
1329 | ||
1330 | module mmu_ase_dp_mux_macro__mux_pgdec__ports_8__stack_58c__width_32 ( | |
1331 | din0, | |
1332 | din1, | |
1333 | din2, | |
1334 | din3, | |
1335 | din4, | |
1336 | din5, | |
1337 | din6, | |
1338 | din7, | |
1339 | sel, | |
1340 | muxtst, | |
1341 | test, | |
1342 | dout); | |
1343 | wire psel0; | |
1344 | wire psel1; | |
1345 | wire psel2; | |
1346 | wire psel3; | |
1347 | wire psel4; | |
1348 | wire psel5; | |
1349 | wire psel6; | |
1350 | wire psel7; | |
1351 | ||
1352 | input [31:0] din0; | |
1353 | input [31:0] din1; | |
1354 | input [31:0] din2; | |
1355 | input [31:0] din3; | |
1356 | input [31:0] din4; | |
1357 | input [31:0] din5; | |
1358 | input [31:0] din6; | |
1359 | input [31:0] din7; | |
1360 | input [2:0] sel; | |
1361 | input muxtst; | |
1362 | input test; | |
1363 | output [31:0] dout; | |
1364 | ||
1365 | ||
1366 | ||
1367 | ||
1368 | ||
1369 | cl_dp1_pdec8_8x c0_0 ( | |
1370 | .sel0(sel[0]), | |
1371 | .sel1(sel[1]), | |
1372 | .sel2(sel[2]), | |
1373 | .psel0(psel0), | |
1374 | .psel1(psel1), | |
1375 | .psel2(psel2), | |
1376 | .psel3(psel3), | |
1377 | .psel4(psel4), | |
1378 | .psel5(psel5), | |
1379 | .psel6(psel6), | |
1380 | .psel7(psel7), | |
1381 | .test(test) | |
1382 | ); | |
1383 | ||
1384 | mux8 #(32) d0_0 ( | |
1385 | .sel0(psel0), | |
1386 | .sel1(psel1), | |
1387 | .sel2(psel2), | |
1388 | .sel3(psel3), | |
1389 | .sel4(psel4), | |
1390 | .sel5(psel5), | |
1391 | .sel6(psel6), | |
1392 | .sel7(psel7), | |
1393 | .in0(din0[31:0]), | |
1394 | .in1(din1[31:0]), | |
1395 | .in2(din2[31:0]), | |
1396 | .in3(din3[31:0]), | |
1397 | .in4(din4[31:0]), | |
1398 | .in5(din5[31:0]), | |
1399 | .in6(din6[31:0]), | |
1400 | .in7(din7[31:0]), | |
1401 | .dout(dout[31:0]), | |
1402 | .muxtst(muxtst) | |
1403 | ); | |
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | ||
1415 | ||
1416 | ||
1417 | endmodule | |
1418 |