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// OpenSPARC T2 Processor File: mmu_ase_dp.v
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wire lsu_context_w_lat_scanin;
wire lsu_context_w_lat_scanout;
wire lsu_va_w_lat_scanin;
wire lsu_va_w_lat_scanout;
wire [60:54] wr_data_unused;
input [12:0] lsu_context_b;
input asi_rd_tsb_cfg_0_2;
input asi_rd_tsb_cfg_1_3;
input asi_rd_physical_offset;
input asi_mra_wr_en_next;
input [63:0] asi_mra_wr_data;
input [81:0] asd0_rd_data;
input [81:0] asd1_rd_data;
input [47:0] asd0_itte_tag_data_;
input [47:0] asd1_itte_tag_data_;
input asi_mbist_run; // MBIST
input asi_ecc_cmpsel_in; // MBIST
input [1:0] asi_ase_cmpsel_in; // MBIST
input [7:0] asi_mbist_wdata; // MBIST
input [7:0] asi_ase_compare_data; // MBIST
input [1:0] mel0_parity; // MBIST
input [1:0] mel1_parity; // MBIST
output [81:0] ase_mra_wr_data;
output [81:0] ase_mra_wr_data_minbuf;
output [63:0] ase_mra_rd_data;
output [47:13] ase_lsu_va_w;
output [12:0] ase_lsu_context_w;
output [31:0] ase_mbd_mbist_data; // MBIST
output [47:0] mmu_itte_tag_data;
//////////////////////////////////////////////////////////////////////
assign test = tcu_dectest;
mmu_ase_dp_buff_macro__width_4 clk_control_buf (
mmu_ase_dp_msff_macro__stack_58c__width_25 lsu_context_w_lat (
.scan_in(lsu_context_w_lat_scanin),
.scan_out(lsu_context_w_lat_scanout),
.din ({asi_ase_compare_data [7:0],
.dout ({compare_data [7:0],
ase_lsu_context_w [12:0]}),
mmu_ase_dp_msff_macro__left_13__stack_58c__width_35 lsu_va_w_lat (
.scan_in(lsu_va_w_lat_scanin),
.scan_out(lsu_va_w_lat_scanout),
.din ({lsu_va_b [47:13]}),
.dout ({lsu_va_w [47:13]}),
assign ase_lsu_va_w[47:13] =
//////////////////////////////////////////////////////////////////////
// Mux the two thread groups together
mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_24 mra_rd_data_1_mux (
.din0 (asd0_rd_data [81:58]),
.din1 (asd1_rd_data [81:58]),
.dout (mra_rd_data [81:58])
mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_58 mra_rd_data_0_mux (
.din0 (asd0_rd_data [57:0] ),
.din1 (asd1_rd_data [57:0] ),
.dout (mra_rd_data [57:0] )
//////////////////////////////////////////////////////////////////////
// Extract and format read data
mmu_ase_dp_mux_macro__mux_aonpe__ports_4__width_64 mra_rd_mux (
.din0 ({mra_rd_data [77:75], // TSB config 63:61
mra_rd_data [74:48], // TSB config 39:13
mra_rd_data [47:39]}), // TSB config 08:00
.din1 ({mra_rd_data [38:36], // TSB config 63:61
mra_rd_data [35:9], // TSB config 39:13
mra_rd_data [8:0]}), // TSB config 08:00
.din2 ({mra_rd_data [81 ], // Real range 63
mra_rd_data [80:27]}), // Real range 53:00
mra_rd_data [26:0], // Physical offset 39:13
.sel0 (asi_rd_tsb_cfg_0_2 ),
.sel1 (asi_rd_tsb_cfg_1_3 ),
.sel2 (asi_rd_real_range ),
.sel3 (asi_rd_physical_offset ),
.dout (ase_mra_rd_data [63:0] )
//////////////////////////////////////////////////////////////////////
assign wr_data_unused[60:54] =
mmu_ase_dp_msff_macro__mux_aope__ports_4__stack_58c__width_24 wr_1_mux (
.scan_in(wr_1_mux_scanin),
.scan_out(wr_1_mux_scanout),
.din0 ({asi_mbist_wdata [1:0], // 81:80
asi_mbist_wdata [7:0], // 79:72
asi_mbist_wdata [7:0], // 71:64
asi_mbist_wdata [7:2]}), // 63:58
.din1 ({{4 {1'b0}} , // 81:78
asi_mra_wr_data [63:61], // TSB config 0,2 77:75
asi_mra_wr_data [39:29], // TSB config 0,2 74:64
asi_mra_wr_data [28:23]}), // TSB config 0,2 63:58
.din2 ({asi_mra_wr_data [63 ], // Real range 81
asi_mra_wr_data [53:31]}), // Real range 80:58
.din3 (mra_rd_data [81:58] ),
.sel1 (asi_rd_tsb_cfg_0_2 ),
.sel2 (asi_rd_real_range ),
.en (asi_mra_wr_en_next ),
.dout (ase_mra_wr_data [81:58] ),
mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_24 wr_1_minbuf (
.din (ase_mra_wr_data[81:58]),
.dout (ase_mra_wr_data_minbuf[81:58])
mmu_ase_dp_msff_macro__mux_aope__ports_5__stack_58c__width_58 wr_0_mux (
.scan_in(wr_0_mux_scanin),
.scan_out(wr_0_mux_scanout),
.din0 ({asi_mbist_wdata [1:0],
{7 {asi_mbist_wdata [7:0]}}}),
.din1 ({asi_mra_wr_data [22:13], // TSB config 0,2 57:48
asi_mra_wr_data [8:0], // TSB config 0,2 47:39
mra_rd_data [38:0]}), // TSB config 1,3
.din2 ({mra_rd_data [57:39], // TSB config 0,2
asi_mra_wr_data [63:61], // TSB config 1,3 38:36
asi_mra_wr_data [39:13], // TSB config 1,3 35:09
asi_mra_wr_data [8:0]}), // TSB config 1,3 08:00
.din3 ({asi_mra_wr_data [30:0], // Real range 57:27
mra_rd_data [26:0]}), // Physical offset
.din4 ({mra_rd_data [57:27], // Real range
asi_mra_wr_data [39:13]}), // Physical offset 26:00
.sel1 (asi_rd_tsb_cfg_0_2 ),
.sel2 (asi_rd_tsb_cfg_1_3 ),
.sel3 (asi_rd_real_range ),
.en (asi_mra_wr_en_next ),
.dout (ase_mra_wr_data [57:0] ),
mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_58 wr_0_minbuf (
.din (ase_mra_wr_data[57:0]),
.dout (ase_mra_wr_data_minbuf[57:0])
//////////////////////////////////////////////////////////////////////////////
// Merge ITLB reload buses together
mmu_ase_dp_nand_macro__ports_2__stack_58c__width_48 itte_tag_data_nand (
.din0 (asd0_itte_tag_data_ [47:0] ),
.din1 (asd1_itte_tag_data_ [47:0] ),
.dout (mmu_itte_tag_data [47:0] )
//////////////////////////////////////////////////////////////////////////////
mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_2 mbist_ecc_mux (
.din0 (mel0_parity [1:0] ),
.din1 (mel1_parity [1:0] ),
.dout (mra_parity [1:0] )
mmu_ase_dp_buff_macro__dbuff_32x__width_1 tst_mux_rep0 (
.dout (tcu_muxtest_rep0 )
mmu_ase_dp_mux_macro__mux_pgdec__ports_8__stack_58c__width_32 mbist_mux (
.din0 (asd1_rd_data [31:0] ),
.din1 (asd1_rd_data [63:32] ),
.din2 ({compare_data [7:0],
.din3 ({{3 {compare_data [7:0]}},
.din4 (asd0_rd_data [31:0] ),
.din5 (asd0_rd_data [63:32] ),
.din6 ({compare_data [7:0],
.din7 ({{3 {compare_data [7:0]}},
.muxtst (tcu_muxtest_rep0 ),
.dout (ase_mbd_mbist_data [31:0] ),
assign lsu_context_w_lat_scanin = scan_in ;
assign lsu_va_w_lat_scanin = lsu_context_w_lat_scanout;
assign wr_1_mux_scanin = lsu_va_w_lat_scanout ;
assign wr_0_mux_scanin = wr_1_mux_scanout ;
assign scan_out = wr_0_mux_scanout ;
module mmu_ase_dp_buff_macro__width_4 (
// any PARAMS parms go into naming of macro
module mmu_ase_dp_msff_macro__stack_58c__width_25 (
.so({so[23:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_ase_dp_msff_macro__left_13__stack_58c__width_35 (
.so({so[33:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_24 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_58 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_ase_dp_mux_macro__mux_aonpe__ports_4__width_64 (
cl_dp1_muxbuff4_8x c0_0 (
// any PARAMS parms go into naming of macro
module mmu_ase_dp_msff_macro__mux_aope__ports_4__stack_58c__width_24 (
.so({so[22:0],scan_out}),
module mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_24 (
// any PARAMS parms go into naming of macro
module mmu_ase_dp_msff_macro__mux_aope__ports_5__stack_58c__width_58 (
.so({so[56:0],scan_out}),
module mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_58 (
// nand macro for ports = 2,3,4
module mmu_ase_dp_nand_macro__ports_2__stack_58c__width_48 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_2 (
module mmu_ase_dp_buff_macro__dbuff_32x__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_ase_dp_mux_macro__mux_pgdec__ports_8__stack_58c__width_32 (