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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tlu_cel_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module tlu_cel_dp ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | spc_aclk, | |
40 | spc_bclk, | |
41 | tcu_scan_en, | |
42 | tlu_cerer_tccp, | |
43 | tlu_cerer_tcup, | |
44 | tlu_cerer_tccd, | |
45 | tlu_cerer_tcud, | |
46 | ced_syndrome, | |
47 | tca_ecc, | |
48 | ced_cecc_err, | |
49 | ced_uecc_err, | |
50 | asi_tccup_in, | |
51 | asi_tccud_in, | |
52 | scan_out, | |
53 | cel_syndrome, | |
54 | cel_ecc, | |
55 | cel_crit_ecc, | |
56 | cel_tccp, | |
57 | cel_tcup, | |
58 | cel_tccd, | |
59 | cel_tcud); | |
60 | wire pce_ov; | |
61 | wire clk; | |
62 | wire stop; | |
63 | wire siclk; | |
64 | wire soclk; | |
65 | wire se; | |
66 | wire en; | |
67 | wire ecc_lat_scanin; | |
68 | wire ecc_lat_scanout; | |
69 | wire tccp_in; | |
70 | wire tcup_in; | |
71 | wire tccd_in; | |
72 | wire tcud_in; | |
73 | wire [7:0] syndrome_in; | |
74 | wire [7:0] rd_ecc; | |
75 | wire tccp; | |
76 | wire tcup; | |
77 | wire tccd; | |
78 | wire tcud; | |
79 | ||
80 | ||
81 | ||
82 | ||
83 | input l2clk; | |
84 | input scan_in; | |
85 | input tcu_pce_ov; | |
86 | input spc_aclk; | |
87 | input spc_bclk; | |
88 | input tcu_scan_en; | |
89 | ||
90 | input tlu_cerer_tccp; // Correctable precise enable | |
91 | input tlu_cerer_tcup; // Unorrectable precise enable | |
92 | input tlu_cerer_tccd; // Correctable disrupting enable | |
93 | input tlu_cerer_tcud; // Unorrectable disrupting enable | |
94 | ||
95 | input [7:0] ced_syndrome; | |
96 | input [7:0] tca_ecc; | |
97 | ||
98 | input ced_cecc_err; | |
99 | input ced_uecc_err; | |
100 | ||
101 | input asi_tccup_in; | |
102 | input asi_tccud_in; | |
103 | ||
104 | ||
105 | output scan_out; | |
106 | ||
107 | output [7:0] cel_syndrome; | |
108 | output [7:0] cel_ecc; | |
109 | output [7:0] cel_crit_ecc; | |
110 | ||
111 | output cel_tccp; | |
112 | output cel_tcup; | |
113 | output cel_tccd; | |
114 | output cel_tcud; | |
115 | ||
116 | ||
117 | ||
118 | //////////////////////////////////////////////////////////////////////////////// | |
119 | ||
120 | assign pce_ov = tcu_pce_ov; | |
121 | assign clk = l2clk; | |
122 | assign stop = 1'b0; | |
123 | assign siclk = spc_aclk; | |
124 | assign soclk = spc_bclk; | |
125 | assign se = tcu_scan_en; | |
126 | assign en = 1'b1; | |
127 | ||
128 | ||
129 | // Data is flopped, but ECC is not... so flop here | |
130 | ||
131 | tlu_cel_dp_msff_macro__minbuff_1__width_28 ecc_lat ( | |
132 | .scan_in(ecc_lat_scanin), | |
133 | .scan_out(ecc_lat_scanout), | |
134 | .din ({tca_ecc [7:0], | |
135 | tccp_in , | |
136 | tcup_in , | |
137 | tccd_in , | |
138 | tcud_in , | |
139 | ced_syndrome [7:0], | |
140 | syndrome_in [7:0]}), | |
141 | .dout ({rd_ecc [7:0], | |
142 | tccp , | |
143 | tcup , | |
144 | tccd , | |
145 | tcud , | |
146 | syndrome_in [7:0], | |
147 | cel_syndrome [7:0]}), | |
148 | .clk(clk), | |
149 | .en(en), | |
150 | .se(se), | |
151 | .siclk(siclk), | |
152 | .soclk(soclk), | |
153 | .pce_ov(pce_ov), | |
154 | .stop(stop) | |
155 | ); | |
156 | ||
157 | assign cel_crit_ecc[7:0] = | |
158 | rd_ecc[7:0]; | |
159 | ||
160 | tlu_cel_dp_buff_macro__rep_1__width_8 ecc_buf ( | |
161 | .din (rd_ecc [7:0] ), | |
162 | .dout (cel_ecc [7:0] ) | |
163 | ); | |
164 | ||
165 | ||
166 | // Merge error signals | |
167 | //assign tccp_in = | |
168 | // cecc_err & tlu_cerer_tccp; | |
169 | //assign tcup_in = | |
170 | // uecc_err & tlu_cerer_tcup; | |
171 | //assign tccd_in = | |
172 | // cecc_err & tlu_cerer_tccd; | |
173 | //assign tcud_in = | |
174 | // uecc_err & tlu_cerer_tcud; | |
175 | //assign tccp = | |
176 | // cel_tccp & asi_tccup_in; | |
177 | //assign tcup = | |
178 | // cel_tcup & asi_tccup_in; | |
179 | ||
180 | ||
181 | tlu_cel_dp_and_macro__ports_3__width_1 tccp_in_and ( | |
182 | .din0 (ced_cecc_err ), | |
183 | .din1 (tlu_cerer_tccp ), | |
184 | .din2 (asi_tccup_in ), | |
185 | .dout (tccp_in ) | |
186 | ); | |
187 | ||
188 | tlu_cel_dp_and_macro__ports_3__width_1 tcup_in_and ( | |
189 | .din0 (ced_uecc_err ), | |
190 | .din1 (tlu_cerer_tcup ), | |
191 | .din2 (asi_tccup_in ), | |
192 | .dout (tcup_in ) | |
193 | ); | |
194 | ||
195 | tlu_cel_dp_and_macro__ports_3__width_1 tccd_in_and ( | |
196 | .din0 (ced_cecc_err ), | |
197 | .din1 (tlu_cerer_tccd ), | |
198 | .din2 (asi_tccud_in ), | |
199 | .dout (tccd_in ) | |
200 | ); | |
201 | ||
202 | tlu_cel_dp_and_macro__ports_3__width_1 tcud_in_and ( | |
203 | .din0 (ced_uecc_err ), | |
204 | .din1 (tlu_cerer_tcud ), | |
205 | .din2 (asi_tccud_in ), | |
206 | .dout (tcud_in ) | |
207 | ); | |
208 | ||
209 | ||
210 | assign cel_tccp = | |
211 | tccp; | |
212 | ||
213 | assign cel_tcup = | |
214 | tcup; | |
215 | ||
216 | assign cel_tccd = | |
217 | tccd; | |
218 | ||
219 | assign cel_tcud = | |
220 | tcud; | |
221 | ||
222 | ||
223 | ||
224 | supply0 vss; // <- port for ground | |
225 | supply1 vdd; // <- port for power | |
226 | ||
227 | // fixscan start: | |
228 | assign ecc_lat_scanin = scan_in ; | |
229 | assign scan_out = ecc_lat_scanout ; | |
230 | // fixscan end: | |
231 | endmodule | |
232 | ||
233 | ||
234 | ||
235 | ||
236 | ||
237 | ||
238 | ||
239 | // any PARAMS parms go into naming of macro | |
240 | ||
241 | module tlu_cel_dp_msff_macro__minbuff_1__width_28 ( | |
242 | din, | |
243 | clk, | |
244 | en, | |
245 | se, | |
246 | scan_in, | |
247 | siclk, | |
248 | soclk, | |
249 | pce_ov, | |
250 | stop, | |
251 | dout, | |
252 | scan_out); | |
253 | wire l1clk; | |
254 | wire siclk_out; | |
255 | wire soclk_out; | |
256 | wire [26:0] so; | |
257 | ||
258 | input [27:0] din; | |
259 | ||
260 | ||
261 | input clk; | |
262 | input en; | |
263 | input se; | |
264 | input scan_in; | |
265 | input siclk; | |
266 | input soclk; | |
267 | input pce_ov; | |
268 | input stop; | |
269 | ||
270 | ||
271 | ||
272 | output [27:0] dout; | |
273 | ||
274 | ||
275 | output scan_out; | |
276 | ||
277 | ||
278 | ||
279 | ||
280 | cl_dp1_l1hdr_8x c0_0 ( | |
281 | .l2clk(clk), | |
282 | .pce(en), | |
283 | .aclk(siclk), | |
284 | .bclk(soclk), | |
285 | .l1clk(l1clk), | |
286 | .se(se), | |
287 | .pce_ov(pce_ov), | |
288 | .stop(stop), | |
289 | .siclk_out(siclk_out), | |
290 | .soclk_out(soclk_out) | |
291 | ); | |
292 | dff #(28) d0_0 ( | |
293 | .l1clk(l1clk), | |
294 | .siclk(siclk_out), | |
295 | .soclk(soclk_out), | |
296 | .d(din[27:0]), | |
297 | .si({scan_in,so[26:0]}), | |
298 | .so({so[26:0],scan_out}), | |
299 | .q(dout[27:0]) | |
300 | ); | |
301 | ||
302 | ||
303 | ||
304 | ||
305 | ||
306 | ||
307 | ||
308 | ||
309 | ||
310 | ||
311 | ||
312 | ||
313 | ||
314 | ||
315 | ||
316 | ||
317 | ||
318 | ||
319 | ||
320 | ||
321 | endmodule | |
322 | ||
323 | ||
324 | ||
325 | ||
326 | ||
327 | ||
328 | ||
329 | ||
330 | ||
331 | // | |
332 | // buff macro | |
333 | // | |
334 | // | |
335 | ||
336 | ||
337 | ||
338 | ||
339 | ||
340 | module tlu_cel_dp_buff_macro__rep_1__width_8 ( | |
341 | din, | |
342 | dout); | |
343 | input [7:0] din; | |
344 | output [7:0] dout; | |
345 | ||
346 | ||
347 | ||
348 | ||
349 | ||
350 | ||
351 | buff #(8) d0_0 ( | |
352 | .in(din[7:0]), | |
353 | .out(dout[7:0]) | |
354 | ); | |
355 | ||
356 | ||
357 | ||
358 | ||
359 | ||
360 | ||
361 | ||
362 | ||
363 | endmodule | |
364 | ||
365 | ||
366 | ||
367 | ||
368 | ||
369 | // | |
370 | // and macro for ports = 2,3,4 | |
371 | // | |
372 | // | |
373 | ||
374 | ||
375 | ||
376 | ||
377 | ||
378 | module tlu_cel_dp_and_macro__ports_3__width_1 ( | |
379 | din0, | |
380 | din1, | |
381 | din2, | |
382 | dout); | |
383 | input [0:0] din0; | |
384 | input [0:0] din1; | |
385 | input [0:0] din2; | |
386 | output [0:0] dout; | |
387 | ||
388 | ||
389 | ||
390 | ||
391 | ||
392 | ||
393 | and3 #(1) d0_0 ( | |
394 | .in0(din0[0:0]), | |
395 | .in1(din1[0:0]), | |
396 | .in2(din2[0:0]), | |
397 | .out(dout[0:0]) | |
398 | ); | |
399 | ||
400 | ||
401 | ||
402 | ||
403 | ||
404 | ||
405 | ||
406 | ||
407 | ||
408 | endmodule | |
409 | ||
410 | ||
411 | ||
412 |