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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_dp1lvt.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cl_dp1lvt_add136_8x ( | |
36 | din0, | |
37 | din1, | |
38 | din2, | |
39 | sel_din2, | |
40 | sum, | |
41 | fya_sticky_dp, | |
42 | fya_sticky_sp, | |
43 | fya_xicc_z); | |
44 | wire [101:0] p; | |
45 | wire [100:0] k; | |
46 | wire [101:0] z; | |
47 | ||
48 | ||
49 | input [135:0] din0; | |
50 | input [132:0] din1; | |
51 | input [135:0] din2; | |
52 | input [3:0] sel_din2; | |
53 | ||
54 | output [135:0] sum; | |
55 | output fya_sticky_dp; | |
56 | output fya_sticky_sp; | |
57 | output [1:0] fya_xicc_z; | |
58 | ||
59 | `ifdef LIB | |
60 | ||
61 | assign sum[135:0] = { din0[135:0]} + | |
62 | {3'b000,din1[132:0]} + | |
63 | ({{{40{sel_din2[3]}} & din2[135:96]}, | |
64 | {{32{sel_din2[2]}} & din2[95:64] }, | |
65 | {{32{sel_din2[1]}} & din2[63:32] }, | |
66 | {{32{sel_din2[0]}} & din2[31:0] }}); | |
67 | ||
68 | ||
69 | // 127 126 125 ... 74 73 72 0 | |
70 | // --- --- --------------- --- ------------ | |
71 | // Float DP x x . 52 fraction G -> Sticky -> | |
72 | ||
73 | // 127 126 125 ... 103 102 101 0 | |
74 | // --- --- --------------- --- ------------ | |
75 | // Float SP x x . 23 fraction G -> Sticky -> | |
76 | ||
77 | ||
78 | assign p[101:0] = din0[101:0] ^ {din1[101:4],{4{1'b0}}}; | |
79 | assign k[100:0] = ~din0[100:0] & ~{din1[100:4],{4{1'b0}}}; | |
80 | ||
81 | assign z[101:1] = p[101:1] ^ k[100:0]; | |
82 | assign z[0] = ~p[0]; | |
83 | ||
84 | assign fya_sticky_sp = ~(& z[101:0]); | |
85 | assign fya_sticky_dp = ~(& z[72:0]); | |
86 | ||
87 | assign fya_xicc_z[1] = & z[63:0]; | |
88 | assign fya_xicc_z[0] = & z[31:0]; | |
89 | ||
90 | `endif | |
91 | ||
92 | endmodule | |
93 | module cl_dp1lvt_add12_fulllvt_8x ( | |
94 | cin, | |
95 | in0, | |
96 | in1, | |
97 | out, | |
98 | cout | |
99 | ); | |
100 | input cin; | |
101 | input [11:0] in0; | |
102 | input [11:0] in1; | |
103 | output [11:0] out; | |
104 | output cout; | |
105 | ||
106 | `ifdef LIB | |
107 | assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin}); | |
108 | `endif | |
109 | ||
110 | endmodule | |
111 | ||
112 | module cl_dp1lvt_add16_fulllvt_8x ( | |
113 | cin, | |
114 | in0, | |
115 | in1, | |
116 | out, | |
117 | cout | |
118 | ); | |
119 | input cin; | |
120 | input [15:0] in0; | |
121 | input [15:0] in1; | |
122 | output [15:0] out; | |
123 | output cout; | |
124 | ||
125 | `ifdef LIB | |
126 | assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin}); | |
127 | `endif | |
128 | ||
129 | endmodule | |
130 | module cl_dp1lvt_add4_fulllvt_8x ( | |
131 | cin, | |
132 | in0, | |
133 | in1, | |
134 | out, | |
135 | cout | |
136 | ); | |
137 | input cin; | |
138 | input [3:0] in0; | |
139 | input [3:0] in1; | |
140 | output [3:0] out; | |
141 | output cout; | |
142 | ||
143 | `ifdef LIB | |
144 | assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin}); | |
145 | `endif | |
146 | ||
147 | endmodule | |
148 | module cl_dp1lvt_add64_fulllvt_8x ( | |
149 | cin, | |
150 | in0, | |
151 | in1, | |
152 | out, | |
153 | cout | |
154 | ); | |
155 | input cin; | |
156 | input [63:0] in0; | |
157 | input [63:0] in1; | |
158 | output [63:0] out; | |
159 | output cout; | |
160 | ||
161 | `ifdef LIB | |
162 | assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin}); | |
163 | `endif | |
164 | ||
165 | endmodule | |
166 | module cl_dp1lvt_add8_fulllvt_8x ( | |
167 | cin, | |
168 | in0, | |
169 | in1, | |
170 | out, | |
171 | cout | |
172 | ); | |
173 | input cin; | |
174 | input [7:0] in0; | |
175 | input [7:0] in1; | |
176 | output [7:0] out; | |
177 | output cout; | |
178 | ||
179 | `ifdef LIB | |
180 | assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin}); | |
181 | `endif | |
182 | ||
183 | endmodule | |
184 | module cl_dp1lvt_add12_8x ( | |
185 | cin, | |
186 | in0, | |
187 | in1, | |
188 | out, | |
189 | cout | |
190 | ); | |
191 | input cin; | |
192 | input [11:0] in0; | |
193 | input [11:0] in1; | |
194 | output [11:0] out; | |
195 | output cout; | |
196 | ||
197 | `ifdef LIB | |
198 | assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin}); | |
199 | `endif | |
200 | ||
201 | endmodule | |
202 | module cl_dp1lvt_add16_8x ( | |
203 | cin, | |
204 | in0, | |
205 | in1, | |
206 | out, | |
207 | cout | |
208 | ); | |
209 | input cin; | |
210 | input [15:0] in0; | |
211 | input [15:0] in1; | |
212 | output [15:0] out; | |
213 | output cout; | |
214 | ||
215 | `ifdef LIB | |
216 | assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin}); | |
217 | `endif | |
218 | ||
219 | endmodule | |
220 | module cl_dp1lvt_add32_8x ( | |
221 | cin, | |
222 | in0, | |
223 | in1, | |
224 | out, | |
225 | cout | |
226 | ); | |
227 | input cin; | |
228 | input [31:0] in0; | |
229 | input [31:0] in1; | |
230 | output [31:0] out; | |
231 | output cout; | |
232 | ||
233 | `ifdef LIB | |
234 | assign {cout, out[31:0]} = ({1'b0, in0[31:0]} + {1'b0, in1[31:0]} + {{32{1'b0}}, cin}); | |
235 | `endif | |
236 | ||
237 | endmodule | |
238 | module cl_dp1lvt_add4_8x ( | |
239 | cin, | |
240 | in0, | |
241 | in1, | |
242 | out, | |
243 | cout | |
244 | ); | |
245 | input cin; | |
246 | input [3:0] in0; | |
247 | input [3:0] in1; | |
248 | output [3:0] out; | |
249 | output cout; | |
250 | ||
251 | `ifdef LIB | |
252 | assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin}); | |
253 | `endif | |
254 | ||
255 | endmodule | |
256 | module cl_dp1lvt_add64_8x ( | |
257 | cin, | |
258 | in0, | |
259 | in1, | |
260 | out, | |
261 | cout | |
262 | ); | |
263 | input cin; | |
264 | input [63:0] in0; | |
265 | input [63:0] in1; | |
266 | output [63:0] out; | |
267 | output cout; | |
268 | ||
269 | `ifdef LIB | |
270 | assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin}); | |
271 | `endif | |
272 | ||
273 | endmodule | |
274 | ||
275 | ||
276 | module cl_dp1lvt_cmpr12_8x ( | |
277 | in0, | |
278 | in1, | |
279 | out | |
280 | ); | |
281 | input [11:0] in0; | |
282 | input [11:0] in1; | |
283 | output out; | |
284 | ||
285 | `ifdef LIB | |
286 | assign out = (in0[11:0] == in1[11:0]); | |
287 | `endif | |
288 | ||
289 | endmodule | |
290 | module cl_dp1lvt_add8_8x ( | |
291 | cin, | |
292 | in0, | |
293 | in1, | |
294 | out, | |
295 | cout | |
296 | ); | |
297 | input cin; | |
298 | input [7:0] in0; | |
299 | input [7:0] in1; | |
300 | output [7:0] out; | |
301 | output cout; | |
302 | ||
303 | `ifdef LIB | |
304 | assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin}); | |
305 | `endif | |
306 | ||
307 | endmodule | |
308 | module cl_dp1lvt_cmpr16_8x ( | |
309 | in0, | |
310 | in1, | |
311 | out | |
312 | ); | |
313 | input [15:0] in0; | |
314 | input [15:0] in1; | |
315 | output out; | |
316 | ||
317 | `ifdef LIB | |
318 | assign out = (in0[15:0] == in1[15:0]); | |
319 | `endif | |
320 | ||
321 | endmodule | |
322 | module cl_dp1lvt_cmpr32_8x ( | |
323 | in0, | |
324 | in1, | |
325 | out | |
326 | ); | |
327 | input [31:0] in0; | |
328 | input [31:0] in1; | |
329 | output out; | |
330 | ||
331 | `ifdef LIB | |
332 | assign out = (in0[31:0] == in1[31:0]); | |
333 | `endif | |
334 | ||
335 | endmodule | |
336 | module cl_dp1lvt_cmpr4_8x ( | |
337 | in0, | |
338 | in1, | |
339 | out | |
340 | ); | |
341 | input [3:0] in0; | |
342 | input [3:0] in1; | |
343 | output out; | |
344 | ||
345 | `ifdef LIB | |
346 | assign out = (in0[3:0] == in1[3:0]); | |
347 | `endif | |
348 | ||
349 | endmodule | |
350 | module cl_dp1lvt_cmpr64_8x ( | |
351 | in0, | |
352 | in1, | |
353 | out | |
354 | ); | |
355 | input [63:0] in0; | |
356 | input [63:0] in1; | |
357 | output out; | |
358 | ||
359 | `ifdef LIB | |
360 | assign out = (in0[63:0] == in1[63:0]); | |
361 | `endif | |
362 | ||
363 | endmodule | |
364 | module cl_dp1lvt_cmpr8_8x ( | |
365 | in0, | |
366 | in1, | |
367 | out | |
368 | ); | |
369 | input [7:0] in0; | |
370 | input [7:0] in1; | |
371 | output out; | |
372 | ||
373 | `ifdef LIB | |
374 | assign out = (in0[7:0] == in1[7:0]); | |
375 | `endif | |
376 | ||
377 | endmodule | |
378 | ||
379 | module cl_dp1lvt_prty16_8x ( | |
380 | in, | |
381 | out | |
382 | ); | |
383 | input [15:0] in; | |
384 | output out; | |
385 | ||
386 | ||
387 | `ifdef LIB | |
388 | assign out = ^in[15:0]; | |
389 | `endif | |
390 | ||
391 | endmodule | |
392 | module cl_dp1lvt_prty32_8x ( | |
393 | in, | |
394 | out | |
395 | ); | |
396 | input [31:0] in; | |
397 | output out; | |
398 | ||
399 | `ifdef LIB | |
400 | assign out = ^in[31:0]; | |
401 | `endif | |
402 | ||
403 | endmodule | |
404 | module cl_dp1lvt_prty4_8x ( | |
405 | in, | |
406 | out | |
407 | ); | |
408 | input [3:0] in; | |
409 | output out; | |
410 | ||
411 | `ifdef LIB | |
412 | assign out = ^in[3:0]; | |
413 | `endif | |
414 | ||
415 | endmodule | |
416 | module cl_dp1lvt_prty8_8x ( | |
417 | in, | |
418 | out | |
419 | ); | |
420 | input [7:0] in; | |
421 | output out; | |
422 | ||
423 | `ifdef LIB | |
424 | assign out = ^in[7:0]; | |
425 | `endif | |
426 | ||
427 | endmodule | |
428 | ||
429 | module cl_dp1lvt_aomux2_1x ( | |
430 | in0, | |
431 | in1, | |
432 | sel0, | |
433 | sel1, | |
434 | out | |
435 | ); | |
436 | input in0; | |
437 | input in1; | |
438 | input sel0; | |
439 | input sel1; | |
440 | output out; | |
441 | ||
442 | `ifdef LIB | |
443 | assign out = ((sel0 & in0) | | |
444 | (sel1 & in1)); | |
445 | `endif | |
446 | ||
447 | ||
448 | endmodule | |
449 | module cl_dp1lvt_aomux2_2x ( | |
450 | in0, | |
451 | in1, | |
452 | sel0, | |
453 | sel1, | |
454 | out | |
455 | ); | |
456 | input in0; | |
457 | input in1; | |
458 | input sel0; | |
459 | input sel1; | |
460 | output out; | |
461 | ||
462 | `ifdef LIB | |
463 | assign out = ((sel0 & in0) | | |
464 | (sel1 & in1)); | |
465 | `endif | |
466 | ||
467 | ||
468 | endmodule | |
469 | module cl_dp1lvt_aomux2_4x ( | |
470 | in0, | |
471 | in1, | |
472 | sel0, | |
473 | sel1, | |
474 | out | |
475 | ); | |
476 | input in0; | |
477 | input in1; | |
478 | input sel0; | |
479 | input sel1; | |
480 | output out; | |
481 | ||
482 | `ifdef LIB | |
483 | assign out = ((sel0 & in0) | | |
484 | (sel1 & in1)); | |
485 | `endif | |
486 | ||
487 | ||
488 | endmodule | |
489 | module cl_dp1lvt_aomux2_6x ( | |
490 | in0, | |
491 | in1, | |
492 | sel0, | |
493 | sel1, | |
494 | out | |
495 | ); | |
496 | input in0; | |
497 | input in1; | |
498 | input sel0; | |
499 | input sel1; | |
500 | output out; | |
501 | ||
502 | `ifdef LIB | |
503 | assign out = ((sel0 & in0) | | |
504 | (sel1 & in1)); | |
505 | `endif | |
506 | ||
507 | ||
508 | endmodule | |
509 | module cl_dp1lvt_aomux2_8x ( | |
510 | in0, | |
511 | in1, | |
512 | sel0, | |
513 | sel1, | |
514 | out | |
515 | ); | |
516 | input in0; | |
517 | input in1; | |
518 | input sel0; | |
519 | input sel1; | |
520 | output out; | |
521 | ||
522 | `ifdef LIB | |
523 | assign out = ((sel0 & in0) | | |
524 | (sel1 & in1)); | |
525 | `endif | |
526 | ||
527 | ||
528 | endmodule | |
529 | ||
530 | module cl_dp1lvt_aomux3_1x ( | |
531 | in0, | |
532 | in1, | |
533 | in2, | |
534 | sel0, | |
535 | sel1, | |
536 | sel2, | |
537 | out | |
538 | ); | |
539 | input in0; | |
540 | input in1; | |
541 | input in2; | |
542 | input sel0; | |
543 | input sel1; | |
544 | input sel2; | |
545 | output out; | |
546 | ||
547 | `ifdef LIB | |
548 | assign out = ((sel0 & in0) | | |
549 | (sel1 & in1) | | |
550 | (sel2 & in2)); | |
551 | `endif | |
552 | ||
553 | endmodule | |
554 | module cl_dp1lvt_aomux3_2x ( | |
555 | in0, | |
556 | in1, | |
557 | in2, | |
558 | sel0, | |
559 | sel1, | |
560 | sel2, | |
561 | out | |
562 | ); | |
563 | input in0; | |
564 | input in1; | |
565 | input in2; | |
566 | input sel0; | |
567 | input sel1; | |
568 | input sel2; | |
569 | output out; | |
570 | ||
571 | `ifdef LIB | |
572 | assign out = ((sel0 & in0) | | |
573 | (sel1 & in1) | | |
574 | (sel2 & in2)); | |
575 | `endif | |
576 | ||
577 | endmodule | |
578 | module cl_dp1lvt_aomux3_4x ( | |
579 | in0, | |
580 | in1, | |
581 | in2, | |
582 | sel0, | |
583 | sel1, | |
584 | sel2, | |
585 | out | |
586 | ); | |
587 | input in0; | |
588 | input in1; | |
589 | input in2; | |
590 | input sel0; | |
591 | input sel1; | |
592 | input sel2; | |
593 | output out; | |
594 | ||
595 | `ifdef LIB | |
596 | assign out = ((sel0 & in0) | | |
597 | (sel1 & in1) | | |
598 | (sel2 & in2)); | |
599 | `endif | |
600 | ||
601 | endmodule | |
602 | module cl_dp1lvt_aomux3_6x ( | |
603 | in0, | |
604 | in1, | |
605 | in2, | |
606 | sel0, | |
607 | sel1, | |
608 | sel2, | |
609 | out | |
610 | ); | |
611 | input in0; | |
612 | input in1; | |
613 | input in2; | |
614 | input sel0; | |
615 | input sel1; | |
616 | input sel2; | |
617 | output out; | |
618 | ||
619 | `ifdef LIB | |
620 | assign out = ((sel0 & in0) | | |
621 | (sel1 & in1) | | |
622 | (sel2 & in2)); | |
623 | `endif | |
624 | ||
625 | endmodule | |
626 | module cl_dp1lvt_aomux3_8x ( | |
627 | in0, | |
628 | in1, | |
629 | in2, | |
630 | sel0, | |
631 | sel1, | |
632 | sel2, | |
633 | out | |
634 | ); | |
635 | input in0; | |
636 | input in1; | |
637 | input in2; | |
638 | input sel0; | |
639 | input sel1; | |
640 | input sel2; | |
641 | output out; | |
642 | ||
643 | `ifdef LIB | |
644 | assign out = ((sel0 & in0) | | |
645 | (sel1 & in1) | | |
646 | (sel2 & in2)); | |
647 | `endif | |
648 | ||
649 | endmodule | |
650 | ||
651 | module cl_dp1lvt_aomux4_1x ( | |
652 | in0, | |
653 | in1, | |
654 | in2, | |
655 | in3, | |
656 | sel0, | |
657 | sel1, | |
658 | sel2, | |
659 | sel3, | |
660 | out | |
661 | ); | |
662 | input in0; | |
663 | input in1; | |
664 | input in2; | |
665 | input in3; | |
666 | input sel0; | |
667 | input sel1; | |
668 | input sel2; | |
669 | input sel3; | |
670 | output out; | |
671 | ||
672 | `ifdef LIB | |
673 | assign out = ((sel0 & in0) | | |
674 | (sel1 & in1) | | |
675 | (sel2 & in2) | | |
676 | (sel3 & in3)); | |
677 | `endif | |
678 | ||
679 | endmodule | |
680 | module cl_dp1lvt_aomux4_2x ( | |
681 | in0, | |
682 | in1, | |
683 | in2, | |
684 | in3, | |
685 | sel0, | |
686 | sel1, | |
687 | sel2, | |
688 | sel3, | |
689 | out | |
690 | ); | |
691 | input in0; | |
692 | input in1; | |
693 | input in2; | |
694 | input in3; | |
695 | input sel0; | |
696 | input sel1; | |
697 | input sel2; | |
698 | input sel3; | |
699 | output out; | |
700 | ||
701 | `ifdef LIB | |
702 | assign out = ((sel0 & in0) | | |
703 | (sel1 & in1) | | |
704 | (sel2 & in2) | | |
705 | (sel3 & in3)); | |
706 | `endif | |
707 | ||
708 | endmodule | |
709 | module cl_dp1lvt_aomux4_4x ( | |
710 | in0, | |
711 | in1, | |
712 | in2, | |
713 | in3, | |
714 | sel0, | |
715 | sel1, | |
716 | sel2, | |
717 | sel3, | |
718 | out | |
719 | ); | |
720 | input in0; | |
721 | input in1; | |
722 | input in2; | |
723 | input in3; | |
724 | input sel0; | |
725 | input sel1; | |
726 | input sel2; | |
727 | input sel3; | |
728 | output out; | |
729 | ||
730 | `ifdef LIB | |
731 | assign out = ((sel0 & in0) | | |
732 | (sel1 & in1) | | |
733 | (sel2 & in2) | | |
734 | (sel3 & in3)); | |
735 | `endif | |
736 | ||
737 | endmodule | |
738 | module cl_dp1lvt_aomux4_6x ( | |
739 | in0, | |
740 | in1, | |
741 | in2, | |
742 | in3, | |
743 | sel0, | |
744 | sel1, | |
745 | sel2, | |
746 | sel3, | |
747 | out | |
748 | ); | |
749 | input in0; | |
750 | input in1; | |
751 | input in2; | |
752 | input in3; | |
753 | input sel0; | |
754 | input sel1; | |
755 | input sel2; | |
756 | input sel3; | |
757 | output out; | |
758 | ||
759 | `ifdef LIB | |
760 | assign out = ((sel0 & in0) | | |
761 | (sel1 & in1) | | |
762 | (sel2 & in2) | | |
763 | (sel3 & in3)); | |
764 | `endif | |
765 | ||
766 | endmodule | |
767 | module cl_dp1lvt_aomux4_8x ( | |
768 | in0, | |
769 | in1, | |
770 | in2, | |
771 | in3, | |
772 | sel0, | |
773 | sel1, | |
774 | sel2, | |
775 | sel3, | |
776 | out | |
777 | ); | |
778 | input in0; | |
779 | input in1; | |
780 | input in2; | |
781 | input in3; | |
782 | input sel0; | |
783 | input sel1; | |
784 | input sel2; | |
785 | input sel3; | |
786 | output out; | |
787 | ||
788 | `ifdef LIB | |
789 | assign out = ((sel0 & in0) | | |
790 | (sel1 & in1) | | |
791 | (sel2 & in2) | | |
792 | (sel3 & in3)); | |
793 | `endif | |
794 | ||
795 | endmodule | |
796 | ||
797 | module cl_dp1lvt_aomux5_1x ( | |
798 | in0, | |
799 | in1, | |
800 | in2, | |
801 | in3, | |
802 | in4, | |
803 | sel0, | |
804 | sel1, | |
805 | sel2, | |
806 | sel3, | |
807 | sel4, | |
808 | out | |
809 | ); | |
810 | input in0; | |
811 | input in1; | |
812 | input in2; | |
813 | input in3; | |
814 | input in4; | |
815 | input sel0; | |
816 | input sel1; | |
817 | input sel2; | |
818 | input sel3; | |
819 | input sel4; | |
820 | output out; | |
821 | ||
822 | `ifdef LIB | |
823 | assign out = ((sel0 & in0) | | |
824 | (sel1 & in1) | | |
825 | (sel2 & in2) | | |
826 | (sel3 & in3) | | |
827 | (sel4 & in4)); | |
828 | `endif | |
829 | ||
830 | endmodule | |
831 | module cl_dp1lvt_aomux5_2x ( | |
832 | in0, | |
833 | in1, | |
834 | in2, | |
835 | in3, | |
836 | in4, | |
837 | sel0, | |
838 | sel1, | |
839 | sel2, | |
840 | sel3, | |
841 | sel4, | |
842 | out | |
843 | ); | |
844 | input in0; | |
845 | input in1; | |
846 | input in2; | |
847 | input in3; | |
848 | input in4; | |
849 | input sel0; | |
850 | input sel1; | |
851 | input sel2; | |
852 | input sel3; | |
853 | input sel4; | |
854 | output out; | |
855 | ||
856 | `ifdef LIB | |
857 | assign out = ((sel0 & in0) | | |
858 | (sel1 & in1) | | |
859 | (sel2 & in2) | | |
860 | (sel3 & in3) | | |
861 | (sel4 & in4)); | |
862 | `endif | |
863 | ||
864 | endmodule | |
865 | module cl_dp1lvt_aomux5_4x ( | |
866 | in0, | |
867 | in1, | |
868 | in2, | |
869 | in3, | |
870 | in4, | |
871 | sel0, | |
872 | sel1, | |
873 | sel2, | |
874 | sel3, | |
875 | sel4, | |
876 | out | |
877 | ); | |
878 | input in0; | |
879 | input in1; | |
880 | input in2; | |
881 | input in3; | |
882 | input in4; | |
883 | input sel0; | |
884 | input sel1; | |
885 | input sel2; | |
886 | input sel3; | |
887 | input sel4; | |
888 | output out; | |
889 | ||
890 | `ifdef LIB | |
891 | assign out = ((sel0 & in0) | | |
892 | (sel1 & in1) | | |
893 | (sel2 & in2) | | |
894 | (sel3 & in3) | | |
895 | (sel4 & in4)); | |
896 | `endif | |
897 | ||
898 | endmodule | |
899 | module cl_dp1lvt_aomux5_6x ( | |
900 | in0, | |
901 | in1, | |
902 | in2, | |
903 | in3, | |
904 | in4, | |
905 | sel0, | |
906 | sel1, | |
907 | sel2, | |
908 | sel3, | |
909 | sel4, | |
910 | out | |
911 | ); | |
912 | input in0; | |
913 | input in1; | |
914 | input in2; | |
915 | input in3; | |
916 | input in4; | |
917 | input sel0; | |
918 | input sel1; | |
919 | input sel2; | |
920 | input sel3; | |
921 | input sel4; | |
922 | output out; | |
923 | ||
924 | `ifdef LIB | |
925 | assign out = ((sel0 & in0) | | |
926 | (sel1 & in1) | | |
927 | (sel2 & in2) | | |
928 | (sel3 & in3) | | |
929 | (sel4 & in4)); | |
930 | `endif | |
931 | ||
932 | endmodule | |
933 | module cl_dp1lvt_aomux5_8x ( | |
934 | in0, | |
935 | in1, | |
936 | in2, | |
937 | in3, | |
938 | in4, | |
939 | sel0, | |
940 | sel1, | |
941 | sel2, | |
942 | sel3, | |
943 | sel4, | |
944 | out | |
945 | ); | |
946 | input in0; | |
947 | input in1; | |
948 | input in2; | |
949 | input in3; | |
950 | input in4; | |
951 | input sel0; | |
952 | input sel1; | |
953 | input sel2; | |
954 | input sel3; | |
955 | input sel4; | |
956 | output out; | |
957 | ||
958 | `ifdef LIB | |
959 | assign out = ((sel0 & in0) | | |
960 | (sel1 & in1) | | |
961 | (sel2 & in2) | | |
962 | (sel3 & in3) | | |
963 | (sel4 & in4)); | |
964 | `endif | |
965 | ||
966 | endmodule | |
967 | ||
968 | module cl_dp1lvt_aomux6_1x ( | |
969 | in0, | |
970 | in1, | |
971 | in2, | |
972 | in3, | |
973 | in4, | |
974 | in5, | |
975 | sel0, | |
976 | sel1, | |
977 | sel2, | |
978 | sel3, | |
979 | sel4, | |
980 | sel5, | |
981 | out | |
982 | ); | |
983 | input in0; | |
984 | input in1; | |
985 | input in2; | |
986 | input in3; | |
987 | input in4; | |
988 | input in5; | |
989 | input sel0; | |
990 | input sel1; | |
991 | input sel2; | |
992 | input sel3; | |
993 | input sel4; | |
994 | input sel5; | |
995 | output out; | |
996 | ||
997 | `ifdef LIB | |
998 | assign out = ((sel0 & in0) | | |
999 | (sel1 & in1) | | |
1000 | (sel2 & in2) | | |
1001 | (sel3 & in3) | | |
1002 | (sel4 & in4) | | |
1003 | (sel5 & in5)); | |
1004 | `endif | |
1005 | ||
1006 | endmodule | |
1007 | module cl_dp1lvt_aomux6_2x ( | |
1008 | in0, | |
1009 | in1, | |
1010 | in2, | |
1011 | in3, | |
1012 | in4, | |
1013 | in5, | |
1014 | sel0, | |
1015 | sel1, | |
1016 | sel2, | |
1017 | sel3, | |
1018 | sel4, | |
1019 | sel5, | |
1020 | out | |
1021 | ); | |
1022 | input in0; | |
1023 | input in1; | |
1024 | input in2; | |
1025 | input in3; | |
1026 | input in4; | |
1027 | input in5; | |
1028 | input sel0; | |
1029 | input sel1; | |
1030 | input sel2; | |
1031 | input sel3; | |
1032 | input sel4; | |
1033 | input sel5; | |
1034 | output out; | |
1035 | ||
1036 | `ifdef LIB | |
1037 | assign out = ((sel0 & in0) | | |
1038 | (sel1 & in1) | | |
1039 | (sel2 & in2) | | |
1040 | (sel3 & in3) | | |
1041 | (sel4 & in4) | | |
1042 | (sel5 & in5)); | |
1043 | `endif | |
1044 | ||
1045 | endmodule | |
1046 | module cl_dp1lvt_aomux6_4x ( | |
1047 | in0, | |
1048 | in1, | |
1049 | in2, | |
1050 | in3, | |
1051 | in4, | |
1052 | in5, | |
1053 | sel0, | |
1054 | sel1, | |
1055 | sel2, | |
1056 | sel3, | |
1057 | sel4, | |
1058 | sel5, | |
1059 | out | |
1060 | ); | |
1061 | input in0; | |
1062 | input in1; | |
1063 | input in2; | |
1064 | input in3; | |
1065 | input in4; | |
1066 | input in5; | |
1067 | input sel0; | |
1068 | input sel1; | |
1069 | input sel2; | |
1070 | input sel3; | |
1071 | input sel4; | |
1072 | input sel5; | |
1073 | output out; | |
1074 | ||
1075 | `ifdef LIB | |
1076 | assign out = ((sel0 & in0) | | |
1077 | (sel1 & in1) | | |
1078 | (sel2 & in2) | | |
1079 | (sel3 & in3) | | |
1080 | (sel4 & in4) | | |
1081 | (sel5 & in5)); | |
1082 | `endif | |
1083 | ||
1084 | endmodule | |
1085 | module cl_dp1lvt_aomux6_6x ( | |
1086 | in0, | |
1087 | in1, | |
1088 | in2, | |
1089 | in3, | |
1090 | in4, | |
1091 | in5, | |
1092 | sel0, | |
1093 | sel1, | |
1094 | sel2, | |
1095 | sel3, | |
1096 | sel4, | |
1097 | sel5, | |
1098 | out | |
1099 | ); | |
1100 | input in0; | |
1101 | input in1; | |
1102 | input in2; | |
1103 | input in3; | |
1104 | input in4; | |
1105 | input in5; | |
1106 | input sel0; | |
1107 | input sel1; | |
1108 | input sel2; | |
1109 | input sel3; | |
1110 | input sel4; | |
1111 | input sel5; | |
1112 | output out; | |
1113 | ||
1114 | `ifdef LIB | |
1115 | assign out = ((sel0 & in0) | | |
1116 | (sel1 & in1) | | |
1117 | (sel2 & in2) | | |
1118 | (sel3 & in3) | | |
1119 | (sel4 & in4) | | |
1120 | (sel5 & in5)); | |
1121 | `endif | |
1122 | ||
1123 | endmodule | |
1124 | module cl_dp1lvt_aomux6_8x ( | |
1125 | in0, | |
1126 | in1, | |
1127 | in2, | |
1128 | in3, | |
1129 | in4, | |
1130 | in5, | |
1131 | sel0, | |
1132 | sel1, | |
1133 | sel2, | |
1134 | sel3, | |
1135 | sel4, | |
1136 | sel5, | |
1137 | out | |
1138 | ); | |
1139 | input in0; | |
1140 | input in1; | |
1141 | input in2; | |
1142 | input in3; | |
1143 | input in4; | |
1144 | input in5; | |
1145 | input sel0; | |
1146 | input sel1; | |
1147 | input sel2; | |
1148 | input sel3; | |
1149 | input sel4; | |
1150 | input sel5; | |
1151 | output out; | |
1152 | ||
1153 | `ifdef LIB | |
1154 | assign out = ((sel0 & in0) | | |
1155 | (sel1 & in1) | | |
1156 | (sel2 & in2) | | |
1157 | (sel3 & in3) | | |
1158 | (sel4 & in4) | | |
1159 | (sel5 & in5)); | |
1160 | `endif | |
1161 | ||
1162 | endmodule | |
1163 | ||
1164 | module cl_dp1lvt_aomux7_1x ( | |
1165 | in0, | |
1166 | in1, | |
1167 | in2, | |
1168 | in3, | |
1169 | in4, | |
1170 | in5, | |
1171 | in6, | |
1172 | sel0, | |
1173 | sel1, | |
1174 | sel2, | |
1175 | sel3, | |
1176 | sel4, | |
1177 | sel5, | |
1178 | sel6, | |
1179 | out | |
1180 | ); | |
1181 | input in0; | |
1182 | input in1; | |
1183 | input in2; | |
1184 | input in3; | |
1185 | input in4; | |
1186 | input in5; | |
1187 | input in6; | |
1188 | input sel0; | |
1189 | input sel1; | |
1190 | input sel2; | |
1191 | input sel3; | |
1192 | input sel4; | |
1193 | input sel5; | |
1194 | input sel6; | |
1195 | output out; | |
1196 | ||
1197 | `ifdef LIB | |
1198 | assign out = ((sel0 & in0) | | |
1199 | (sel1 & in1) | | |
1200 | (sel2 & in2) | | |
1201 | (sel3 & in3) | | |
1202 | (sel4 & in4) | | |
1203 | (sel5 & in5) | | |
1204 | (sel6 & in6)); | |
1205 | `endif | |
1206 | ||
1207 | endmodule | |
1208 | module cl_dp1lvt_aomux7_2x ( | |
1209 | in0, | |
1210 | in1, | |
1211 | in2, | |
1212 | in3, | |
1213 | in4, | |
1214 | in5, | |
1215 | in6, | |
1216 | sel0, | |
1217 | sel1, | |
1218 | sel2, | |
1219 | sel3, | |
1220 | sel4, | |
1221 | sel5, | |
1222 | sel6, | |
1223 | out | |
1224 | ); | |
1225 | input in0; | |
1226 | input in1; | |
1227 | input in2; | |
1228 | input in3; | |
1229 | input in4; | |
1230 | input in5; | |
1231 | input in6; | |
1232 | input sel0; | |
1233 | input sel1; | |
1234 | input sel2; | |
1235 | input sel3; | |
1236 | input sel4; | |
1237 | input sel5; | |
1238 | input sel6; | |
1239 | output out; | |
1240 | ||
1241 | `ifdef LIB | |
1242 | assign out = ((sel0 & in0) | | |
1243 | (sel1 & in1) | | |
1244 | (sel2 & in2) | | |
1245 | (sel3 & in3) | | |
1246 | (sel4 & in4) | | |
1247 | (sel5 & in5) | | |
1248 | (sel6 & in6)); | |
1249 | `endif | |
1250 | ||
1251 | endmodule | |
1252 | module cl_dp1lvt_aomux7_4x ( | |
1253 | in0, | |
1254 | in1, | |
1255 | in2, | |
1256 | in3, | |
1257 | in4, | |
1258 | in5, | |
1259 | in6, | |
1260 | sel0, | |
1261 | sel1, | |
1262 | sel2, | |
1263 | sel3, | |
1264 | sel4, | |
1265 | sel5, | |
1266 | sel6, | |
1267 | out | |
1268 | ); | |
1269 | input in0; | |
1270 | input in1; | |
1271 | input in2; | |
1272 | input in3; | |
1273 | input in4; | |
1274 | input in5; | |
1275 | input in6; | |
1276 | input sel0; | |
1277 | input sel1; | |
1278 | input sel2; | |
1279 | input sel3; | |
1280 | input sel4; | |
1281 | input sel5; | |
1282 | input sel6; | |
1283 | output out; | |
1284 | ||
1285 | `ifdef LIB | |
1286 | assign out = ((sel0 & in0) | | |
1287 | (sel1 & in1) | | |
1288 | (sel2 & in2) | | |
1289 | (sel3 & in3) | | |
1290 | (sel4 & in4) | | |
1291 | (sel5 & in5) | | |
1292 | (sel6 & in6)); | |
1293 | `endif | |
1294 | ||
1295 | endmodule | |
1296 | module cl_dp1lvt_aomux7_6x ( | |
1297 | in0, | |
1298 | in1, | |
1299 | in2, | |
1300 | in3, | |
1301 | in4, | |
1302 | in5, | |
1303 | in6, | |
1304 | sel0, | |
1305 | sel1, | |
1306 | sel2, | |
1307 | sel3, | |
1308 | sel4, | |
1309 | sel5, | |
1310 | sel6, | |
1311 | out | |
1312 | ); | |
1313 | input in0; | |
1314 | input in1; | |
1315 | input in2; | |
1316 | input in3; | |
1317 | input in4; | |
1318 | input in5; | |
1319 | input in6; | |
1320 | input sel0; | |
1321 | input sel1; | |
1322 | input sel2; | |
1323 | input sel3; | |
1324 | input sel4; | |
1325 | input sel5; | |
1326 | input sel6; | |
1327 | output out; | |
1328 | ||
1329 | `ifdef LIB | |
1330 | assign out = ((sel0 & in0) | | |
1331 | (sel1 & in1) | | |
1332 | (sel2 & in2) | | |
1333 | (sel3 & in3) | | |
1334 | (sel4 & in4) | | |
1335 | (sel5 & in5) | | |
1336 | (sel6 & in6)); | |
1337 | `endif | |
1338 | ||
1339 | endmodule | |
1340 | module cl_dp1lvt_aomux7_8x ( | |
1341 | in0, | |
1342 | in1, | |
1343 | in2, | |
1344 | in3, | |
1345 | in4, | |
1346 | in5, | |
1347 | in6, | |
1348 | sel0, | |
1349 | sel1, | |
1350 | sel2, | |
1351 | sel3, | |
1352 | sel4, | |
1353 | sel5, | |
1354 | sel6, | |
1355 | out | |
1356 | ); | |
1357 | input in0; | |
1358 | input in1; | |
1359 | input in2; | |
1360 | input in3; | |
1361 | input in4; | |
1362 | input in5; | |
1363 | input in6; | |
1364 | input sel0; | |
1365 | input sel1; | |
1366 | input sel2; | |
1367 | input sel3; | |
1368 | input sel4; | |
1369 | input sel5; | |
1370 | input sel6; | |
1371 | output out; | |
1372 | ||
1373 | `ifdef LIB | |
1374 | assign out = ((sel0 & in0) | | |
1375 | (sel1 & in1) | | |
1376 | (sel2 & in2) | | |
1377 | (sel3 & in3) | | |
1378 | (sel4 & in4) | | |
1379 | (sel5 & in5) | | |
1380 | (sel6 & in6)); | |
1381 | `endif | |
1382 | ||
1383 | endmodule | |
1384 | ||
1385 | module cl_dp1lvt_aomux8_1x ( | |
1386 | in0, | |
1387 | in1, | |
1388 | in2, | |
1389 | in3, | |
1390 | in4, | |
1391 | in5, | |
1392 | in6, | |
1393 | in7, | |
1394 | sel0, | |
1395 | sel1, | |
1396 | sel2, | |
1397 | sel3, | |
1398 | sel4, | |
1399 | sel5, | |
1400 | sel6, | |
1401 | sel7, | |
1402 | out | |
1403 | ); | |
1404 | input in0; | |
1405 | input in1; | |
1406 | input in2; | |
1407 | input in3; | |
1408 | input in4; | |
1409 | input in5; | |
1410 | input in6; | |
1411 | input in7; | |
1412 | input sel0; | |
1413 | input sel1; | |
1414 | input sel2; | |
1415 | input sel3; | |
1416 | input sel4; | |
1417 | input sel5; | |
1418 | input sel6; | |
1419 | input sel7; | |
1420 | output out; | |
1421 | ||
1422 | `ifdef LIB | |
1423 | assign out = ((sel0 & in0) | | |
1424 | (sel1 & in1) | | |
1425 | (sel2 & in2) | | |
1426 | (sel3 & in3) | | |
1427 | (sel4 & in4) | | |
1428 | (sel5 & in5) | | |
1429 | (sel6 & in6) | | |
1430 | (sel7 & in7)); | |
1431 | `endif | |
1432 | ||
1433 | ||
1434 | endmodule | |
1435 | module cl_dp1lvt_aomux8_2x ( | |
1436 | in0, | |
1437 | in1, | |
1438 | in2, | |
1439 | in3, | |
1440 | in4, | |
1441 | in5, | |
1442 | in6, | |
1443 | in7, | |
1444 | sel0, | |
1445 | sel1, | |
1446 | sel2, | |
1447 | sel3, | |
1448 | sel4, | |
1449 | sel5, | |
1450 | sel6, | |
1451 | sel7, | |
1452 | out | |
1453 | ); | |
1454 | input in0; | |
1455 | input in1; | |
1456 | input in2; | |
1457 | input in3; | |
1458 | input in4; | |
1459 | input in5; | |
1460 | input in6; | |
1461 | input in7; | |
1462 | input sel0; | |
1463 | input sel1; | |
1464 | input sel2; | |
1465 | input sel3; | |
1466 | input sel4; | |
1467 | input sel5; | |
1468 | input sel6; | |
1469 | input sel7; | |
1470 | output out; | |
1471 | ||
1472 | `ifdef LIB | |
1473 | assign out = ((sel0 & in0) | | |
1474 | (sel1 & in1) | | |
1475 | (sel2 & in2) | | |
1476 | (sel3 & in3) | | |
1477 | (sel4 & in4) | | |
1478 | (sel5 & in5) | | |
1479 | (sel6 & in6) | | |
1480 | (sel7 & in7)); | |
1481 | `endif | |
1482 | ||
1483 | ||
1484 | endmodule | |
1485 | module cl_dp1lvt_aomux8_4x ( | |
1486 | in0, | |
1487 | in1, | |
1488 | in2, | |
1489 | in3, | |
1490 | in4, | |
1491 | in5, | |
1492 | in6, | |
1493 | in7, | |
1494 | sel0, | |
1495 | sel1, | |
1496 | sel2, | |
1497 | sel3, | |
1498 | sel4, | |
1499 | sel5, | |
1500 | sel6, | |
1501 | sel7, | |
1502 | out | |
1503 | ); | |
1504 | input in0; | |
1505 | input in1; | |
1506 | input in2; | |
1507 | input in3; | |
1508 | input in4; | |
1509 | input in5; | |
1510 | input in6; | |
1511 | input in7; | |
1512 | input sel0; | |
1513 | input sel1; | |
1514 | input sel2; | |
1515 | input sel3; | |
1516 | input sel4; | |
1517 | input sel5; | |
1518 | input sel6; | |
1519 | input sel7; | |
1520 | output out; | |
1521 | ||
1522 | `ifdef LIB | |
1523 | assign out = ((sel0 & in0) | | |
1524 | (sel1 & in1) | | |
1525 | (sel2 & in2) | | |
1526 | (sel3 & in3) | | |
1527 | (sel4 & in4) | | |
1528 | (sel5 & in5) | | |
1529 | (sel6 & in6) | | |
1530 | (sel7 & in7)); | |
1531 | `endif | |
1532 | ||
1533 | ||
1534 | endmodule | |
1535 | module cl_dp1lvt_aomux8_6x ( | |
1536 | in0, | |
1537 | in1, | |
1538 | in2, | |
1539 | in3, | |
1540 | in4, | |
1541 | in5, | |
1542 | in6, | |
1543 | in7, | |
1544 | sel0, | |
1545 | sel1, | |
1546 | sel2, | |
1547 | sel3, | |
1548 | sel4, | |
1549 | sel5, | |
1550 | sel6, | |
1551 | sel7, | |
1552 | out | |
1553 | ); | |
1554 | input in0; | |
1555 | input in1; | |
1556 | input in2; | |
1557 | input in3; | |
1558 | input in4; | |
1559 | input in5; | |
1560 | input in6; | |
1561 | input in7; | |
1562 | input sel0; | |
1563 | input sel1; | |
1564 | input sel2; | |
1565 | input sel3; | |
1566 | input sel4; | |
1567 | input sel5; | |
1568 | input sel6; | |
1569 | input sel7; | |
1570 | output out; | |
1571 | ||
1572 | `ifdef LIB | |
1573 | assign out = ((sel0 & in0) | | |
1574 | (sel1 & in1) | | |
1575 | (sel2 & in2) | | |
1576 | (sel3 & in3) | | |
1577 | (sel4 & in4) | | |
1578 | (sel5 & in5) | | |
1579 | (sel6 & in6) | | |
1580 | (sel7 & in7)); | |
1581 | `endif | |
1582 | ||
1583 | ||
1584 | endmodule | |
1585 | module cl_dp1lvt_aomux8_8x ( | |
1586 | in0, | |
1587 | in1, | |
1588 | in2, | |
1589 | in3, | |
1590 | in4, | |
1591 | in5, | |
1592 | in6, | |
1593 | in7, | |
1594 | sel0, | |
1595 | sel1, | |
1596 | sel2, | |
1597 | sel3, | |
1598 | sel4, | |
1599 | sel5, | |
1600 | sel6, | |
1601 | sel7, | |
1602 | out | |
1603 | ); | |
1604 | input in0; | |
1605 | input in1; | |
1606 | input in2; | |
1607 | input in3; | |
1608 | input in4; | |
1609 | input in5; | |
1610 | input in6; | |
1611 | input in7; | |
1612 | input sel0; | |
1613 | input sel1; | |
1614 | input sel2; | |
1615 | input sel3; | |
1616 | input sel4; | |
1617 | input sel5; | |
1618 | input sel6; | |
1619 | input sel7; | |
1620 | output out; | |
1621 | ||
1622 | `ifdef LIB | |
1623 | assign out = ((sel0 & in0) | | |
1624 | (sel1 & in1) | | |
1625 | (sel2 & in2) | | |
1626 | (sel3 & in3) | | |
1627 | (sel4 & in4) | | |
1628 | (sel5 & in5) | | |
1629 | (sel6 & in6) | | |
1630 | (sel7 & in7)); | |
1631 | `endif | |
1632 | ||
1633 | ||
1634 | endmodule | |
1635 | module cl_dp1lvt_incr32_8x ( | |
1636 | cin, | |
1637 | in0, | |
1638 | out, | |
1639 | cout | |
1640 | ); | |
1641 | input cin; | |
1642 | input [31:0] in0; | |
1643 | output [31:0] out; | |
1644 | output cout; | |
1645 | ||
1646 | `ifdef LIB | |
1647 | assign {cout, out[31:0]} = {1'b0, in0[31:0]} + {32'b0, cin}; | |
1648 | `endif | |
1649 | ||
1650 | endmodule | |
1651 | module cl_dp1lvt_incr48_8x ( | |
1652 | cin, | |
1653 | in0, | |
1654 | out, | |
1655 | cout | |
1656 | ); | |
1657 | input cin; | |
1658 | input [47:0] in0; | |
1659 | output [47:0] out; | |
1660 | output cout; | |
1661 | ||
1662 | `ifdef LIB | |
1663 | assign {cout, out[47:0]} = {1'b0, in0[47:0]} + {48'b0, cin}; | |
1664 | `endif | |
1665 | ||
1666 | endmodule | |
1667 | module cl_dp1lvt_incr64_8x ( | |
1668 | cin, | |
1669 | in0, | |
1670 | out, | |
1671 | cout | |
1672 | ); | |
1673 | input cin; | |
1674 | input [63:0] in0; | |
1675 | output [63:0] out; | |
1676 | output cout; | |
1677 | ||
1678 | `ifdef LIB | |
1679 | assign {cout, out[63:0]} = {1'b0, in0[63:0]} + {64'b0, cin}; | |
1680 | `endif | |
1681 | ||
1682 | endmodule |