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// OpenSPARC T2 Processor File: cl_dp1lvt.v
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module cl_dp1lvt_add136_8x (
assign sum[135:0] = { din0[135:0]} +
({{{40{sel_din2[3]}} & din2[135:96]},
{{32{sel_din2[2]}} & din2[95:64] },
{{32{sel_din2[1]}} & din2[63:32] },
{{32{sel_din2[0]}} & din2[31:0] }});
// 127 126 125 ... 74 73 72 0
// --- --- --------------- --- ------------
// Float DP x x . 52 fraction G -> Sticky ->
// 127 126 125 ... 103 102 101 0
// --- --- --------------- --- ------------
// Float SP x x . 23 fraction G -> Sticky ->
assign p[101:0] = din0[101:0] ^ {din1[101:4],{4{1'b0}}};
assign k[100:0] = ~din0[100:0] & ~{din1[100:4],{4{1'b0}}};
assign z[101:1] = p[101:1] ^ k[100:0];
assign fya_sticky_sp = ~(& z[101:0]);
assign fya_sticky_dp = ~(& z[72:0]);
assign fya_xicc_z[1] = & z[63:0];
assign fya_xicc_z[0] = & z[31:0];
module cl_dp1lvt_add12_fulllvt_8x (
assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin});
module cl_dp1lvt_add16_fulllvt_8x (
assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin});
module cl_dp1lvt_add4_fulllvt_8x (
assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin});
module cl_dp1lvt_add64_fulllvt_8x (
assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin});
module cl_dp1lvt_add8_fulllvt_8x (
assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin});
module cl_dp1lvt_add12_8x (
assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin});
module cl_dp1lvt_add16_8x (
assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin});
module cl_dp1lvt_add32_8x (
assign {cout, out[31:0]} = ({1'b0, in0[31:0]} + {1'b0, in1[31:0]} + {{32{1'b0}}, cin});
module cl_dp1lvt_add4_8x (
assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin});
module cl_dp1lvt_add64_8x (
assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin});
module cl_dp1lvt_cmpr12_8x (
assign out = (in0[11:0] == in1[11:0]);
module cl_dp1lvt_add8_8x (
assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin});
module cl_dp1lvt_cmpr16_8x (
assign out = (in0[15:0] == in1[15:0]);
module cl_dp1lvt_cmpr32_8x (
assign out = (in0[31:0] == in1[31:0]);
module cl_dp1lvt_cmpr4_8x (
assign out = (in0[3:0] == in1[3:0]);
module cl_dp1lvt_cmpr64_8x (
assign out = (in0[63:0] == in1[63:0]);
module cl_dp1lvt_cmpr8_8x (
assign out = (in0[7:0] == in1[7:0]);
module cl_dp1lvt_prty16_8x (
module cl_dp1lvt_prty32_8x (
module cl_dp1lvt_prty4_8x (
module cl_dp1lvt_prty8_8x (
module cl_dp1lvt_aomux2_1x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux2_2x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux2_4x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux2_6x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux2_8x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux3_1x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux3_2x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux3_4x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux3_6x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux3_8x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux4_1x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux4_2x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux4_4x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux4_6x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux4_8x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux5_1x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux5_2x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux5_4x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux5_6x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux5_8x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux6_1x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux6_2x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux6_4x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux6_6x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux6_8x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux7_1x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux7_2x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux7_4x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux7_6x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux7_8x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux8_1x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux8_2x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux8_4x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux8_6x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_aomux8_8x (
assign out = ((sel0 & in0) |
module cl_dp1lvt_incr32_8x (
assign {cout, out[31:0]} = {1'b0, in0[31:0]} + {32'b0, cin};
module cl_dp1lvt_incr48_8x (
assign {cout, out[47:0]} = {1'b0, in0[47:0]} + {48'b0, cin};
module cl_dp1lvt_incr64_8x (
assign {cout, out[63:0]} = {1'b0, in0[63:0]} + {64'b0, cin};