[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_l2_da_ce_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_l2_da_ce_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define MAIN_PAGE_HV_ALSO


#define  L2_ENTRY_PA        0xa000000000
#define  TEST_DATA1         0x5555555555555555
#define	 L2_ENTRY_PA0       0x30000008
#define  L2_ES_W1C_VALUE    0xc03ffffc00000000
#define	 SPARC_ES_W1C_VALUE 0xefffffff
#define  TT_SW_Error        0x40

#define  	L2_ESR_MASK	0xf03ffffff0000000 
#define 	L2_VEC		36
#define		L2_LDWC		51
#define         L2_LDAC         53
 
#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"

.text
.global	 main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:


  ! Boot code does not provide TLB translation for IO address space
	ta    T_CHANGE_HPRIV
	clr	%i0
	clr	%o0
th_id:
	ldxa    [%g0]ASI_INTR_ID, %o6
	

disable_l1_DCache:
	ldxa  [%g0] ASI_LSU_CONTROL, %l0
	! Remove bit 2
	andn  %l0, 0x2, %l0
	stxa  %l0, [%g0] ASI_LSU_CONTROL

enable_err_reporting:
	setx L2EE_PA0, %l0, %l1
	ldx  [%l1], %l2
	mov  0x3, %l0
	or   %l2, %l0, %l2
	stx  %l2, [%l1]


set_L2_Directly_Mapped_Mode_errorsteer:
	setx  	L2CS_PA0, %l6, %g1
	ldx	[%g1], %o6

	mov   	0x2, %o5		! L2_CSR_REG<1>=1 => DM mode

        ldxa    [%g0]ASI_INTR_ID, %o4	! get the thread id; for core-portable
	sllx	%o4, 15, %o4		! L2_CSR_REG<21:15> = ERROR_STEER

	or	%o5, %o4, %o5

	or	%o6, %o5, %o6

	stx   	%o6, [%g1]
	membar	0x40

store_to_L2:
	setx  TEST_DATA1, %l0, %g5

store_to_L2_way0:
	setx	0x3000aa00, %l0, %g2  ! bits [21:18] select way
	stx %g5, [%g2] 
	stx %g5, [%g2+8]

        nop; nop; nop; nop; nop
        nop; nop; nop; nop; nop
        nop; nop; nop; nop; nop


	membar #Sync

L2_diag_load:
	setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
	setx	L2_ENTRY_PA, %l0, %g4
	and   %g2, %l2, %g5           !g2 has L2 PA, 
	or	%g5, %g4, %g5           !g5 now has Diagnostic Data Array address 
	ldx	[%g5], %g6
	membar #Sync

! Flip one bits to inject error
	xor	 %g6, 0x200, %g6
	stx	%g6, [%g5]
	membar #Sync

reading_back_0:                 !Load to L2 again to get the error
	setx  0x3000aa00, %l0, %g2
	ldx   [%g2], %l6
	membar #Sync  


	! Loop until gets first  trap	
	set	0x100, %o1
loop_1:
	dec	%o1
	cmp	%o1, %g0
	be	test_fail
	nop

	nop
	cmp	%i0, 0x1
	bne	loop_1
	nop


/**********************************************
        LDWC
***********************************************/
write_back:        
        setx  0x1000aa00, %l0, %g2
        ldx   [%g2], %l6
        add     %g2, 0x200, %g2
        ldx   [%g2], %l6
        membar #Sync

        setx  0x2000aa00, %l0, %g2
        ldx   [%g2], %l6


        ! Loop until gets first  trap
        set     0x100, %o1
loop_2:
        dec     %o1
        cmp     %o1, %g0
        be      test_fail
        nop

        nop
        cmp     %o0, 0x1
        bne     loop_2
        nop

	nop; nop; nop; nop

        membar #Sync

/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
	ta  T_GOOD_TRAP

test_fail:
	ta  T_BAD_TRAP


My_Corrected_ECC_error_trap:
	inc	%o0

check_l2_ESR_0x63:
        setx  L2ES_PA0, %l6, %g1
        ldx   [%g1], %g2

        setx    L2_ESR_MASK, %g7, %g3
        and     %g2, %g3, %g4

check_LDWC_0x63:
        mov     0x1, %i1
        sllx    %i1, L2_VEC, %i2
        sllx    %i1, L2_LDWC, %i3
        or      %i2, %i3, %i4

        cmp     %g4, %i4
        bne     %xcc, test_fail
        nop


clear_l2_ESR_0x63:
	setx	L2_ES_W1C_VALUE, %g7, %g2
	stx	%g2, [%g1]
	membar	#Sync


check_l2_EAR_0x63:
        setx    L2EA_PA0, %g7, %g1
        ldx     [%g1], %g2
        setx    0x3000aa00, %g7, %g3
        cmp     %g3, %g2
        bne     test_fail
        nop


check_DESR_L2C_0x63:
        ldxa    [%g0] 0x4c, %g1
        setx    0xff00000000000000, %g7, %g2
        and     %g1, %g2, %g3
        setx    0xa900000000000000, %g7, %g4
        cmp     %g3, %g4
!        bne     %xcc, test_failed
        nop

	done
	nop


My_Recoverable_Sw_error_trap:
	inc	%i0

check_l2_ESR_0x40:
        setx  L2ES_PA0, %l6, %g1
        ldx   [%g1], %g2

        setx    L2_ESR_MASK, %g7, %g3
        and     %g2, %g3, %g4

check_LDAC_0x40:
        mov     0x1, %i1
        sllx    %i1, L2_VEC, %i2
        sllx    %i1, L2_LDAC, %i3
        or      %i2, %i3, %i4

        cmp     %g4, %i4
        bne     %xcc, test_fail
        nop

clear_l2_ESR_0x40:
	setx	L2_ES_W1C_VALUE, %g7, %g2
	stx	%g2, [%g1]
	membar	#Sync

check_l2_EAR_0x40:
        setx    L2EA_PA0, %g7, %g1
        ldx     [%g1], %g2
        setx    0x3000aa00, %g7, %g3
        cmp     %g3, %g2
        bne     test_fail
        nop

check_DESR_L2C_0x40:
        ldxa    [%g0] 0x4c, %g1
        setx    0xff00000000000000, %g7, %g2
        and     %g1, %g2, %g3
        setx    0xb500000000000000, %g7, %g4
        cmp     %g3, %g4
!        bne     %xcc, test_failed
        nop

        done
        nop
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_l2_da_ce_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define MAIN_PAGE_HV_ALSO
	42
	43
	44	#define L2_ENTRY_PA 0xa000000000
	45	#define TEST_DATA1 0x5555555555555555
	46	#define L2_ENTRY_PA0 0x30000008
	47	#define L2_ES_W1C_VALUE 0xc03ffffc00000000
	48	#define SPARC_ES_W1C_VALUE 0xefffffff
	49	#define TT_SW_Error 0x40
	50
	51	#define L2_ESR_MASK 0xf03ffffff0000000
	52	#define L2_VEC 36
	53	#define L2_LDWC 51
	54	#define L2_LDAC 53
	55
	56	#include "hboot.s"
	57	#include "asi_s.h"
	58	#include "err_defines.h"
	59
	60	.text
	61	.global main
	62	.global My_Corrected_ECC_error_trap
	63	.global My_Recoverable_Sw_error_trap
	64
65	main:
66
67
68	! Boot code does not provide TLB translation for IO address space
69	ta T_CHANGE_HPRIV
70	clr %i0
71	clr %o0
72	th_id:
73	ldxa [%g0]ASI_INTR_ID, %o6
74
75
76	disable_l1_DCache:
77	ldxa [%g0] ASI_LSU_CONTROL, %l0
78	! Remove bit 2
79	andn %l0, 0x2, %l0
80	stxa %l0, [%g0] ASI_LSU_CONTROL
81
82	enable_err_reporting:
83	setx L2EE_PA0, %l0, %l1
84	ldx [%l1], %l2
85	mov 0x3, %l0
86	or %l2, %l0, %l2
87	stx %l2, [%l1]
88
89
90	set_L2_Directly_Mapped_Mode_errorsteer:
91	setx L2CS_PA0, %l6, %g1
92	ldx [%g1], %o6
93
94	mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
95
96	ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
97	sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER
98
99	or %o5, %o4, %o5
100
101	or %o6, %o5, %o6
102
103	stx %o6, [%g1]
104	membar 0x40
105
106	store_to_L2:
107	setx TEST_DATA1, %l0, %g5
108
109	store_to_L2_way0:
110	setx 0x3000aa00, %l0, %g2 ! bits [21:18] select way
111	stx %g5, [%g2]
112	stx %g5, [%g2+8]
113
114	nop; nop; nop; nop; nop
115	nop; nop; nop; nop; nop
116	nop; nop; nop; nop; nop
117
118
119	membar #Sync
120
121	L2_diag_load:
122	setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
123	setx L2_ENTRY_PA, %l0, %g4
124	and %g2, %l2, %g5 !g2 has L2 PA,
125	or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
126	ldx [%g5], %g6
127	membar #Sync
128
129	! Flip one bits to inject error
130	xor %g6, 0x200, %g6
131	stx %g6, [%g5]
132	membar #Sync
133
134	reading_back_0: !Load to L2 again to get the error
135	setx 0x3000aa00, %l0, %g2
136	ldx [%g2], %l6
137	membar #Sync
138
139
140	! Loop until gets first trap
141	set 0x100, %o1
142	loop_1:
143	dec %o1
144	cmp %o1, %g0
145	be test_fail
146	nop
147
148	nop
149	cmp %i0, 0x1
150	bne loop_1
151	nop
152
153
154
155	/**********************************************
156	LDWC
157	***********************************************/
158	write_back:
159	setx 0x1000aa00, %l0, %g2
160	ldx [%g2], %l6
161	add %g2, 0x200, %g2
162	ldx [%g2], %l6
163	membar #Sync
164
165	setx 0x2000aa00, %l0, %g2
166	ldx [%g2], %l6
167
168
169	! Loop until gets first trap
170	set 0x100, %o1
171	loop_2:
172	dec %o1
173	cmp %o1, %g0
174	be test_fail
175	nop
176
177	nop
178	cmp %o0, 0x1
179	bne loop_2
180	nop
181
182	nop; nop; nop; nop
183
184	membar #Sync
185
186	/*******************************************************
187	* Exit code
188	*******************************************************/
189
190	test_pass:
191	ta T_GOOD_TRAP
192
193	test_fail:
194	ta T_BAD_TRAP
195
196
197
198
199	My_Corrected_ECC_error_trap:
200	inc %o0
201
202	check_l2_ESR_0x63:
203	setx L2ES_PA0, %l6, %g1
204	ldx [%g1], %g2
205
206	setx L2_ESR_MASK, %g7, %g3
207	and %g2, %g3, %g4
208
209	check_LDWC_0x63:
210	mov 0x1, %i1
211	sllx %i1, L2_VEC, %i2
212	sllx %i1, L2_LDWC, %i3
213	or %i2, %i3, %i4
214
215	cmp %g4, %i4
216	bne %xcc, test_fail
217	nop
218
219
220	clear_l2_ESR_0x63:
221	setx L2_ES_W1C_VALUE, %g7, %g2
222	stx %g2, [%g1]
223	membar #Sync
224
225
226	check_l2_EAR_0x63:
227	setx L2EA_PA0, %g7, %g1
228	ldx [%g1], %g2
229	setx 0x3000aa00, %g7, %g3
230	cmp %g3, %g2
231	bne test_fail
232	nop
233
234
235	check_DESR_L2C_0x63:
236	ldxa [%g0] 0x4c, %g1
237	setx 0xff00000000000000, %g7, %g2
238	and %g1, %g2, %g3
239	setx 0xa900000000000000, %g7, %g4
240	cmp %g3, %g4
241	! bne %xcc, test_failed
242	nop
243
244	done
245	nop
246
247
248
249
250	My_Recoverable_Sw_error_trap:
251	inc %i0
252
253	check_l2_ESR_0x40:
254	setx L2ES_PA0, %l6, %g1
255	ldx [%g1], %g2
256
257	setx L2_ESR_MASK, %g7, %g3
258	and %g2, %g3, %g4
259
260	check_LDAC_0x40:
261	mov 0x1, %i1
262	sllx %i1, L2_VEC, %i2
263	sllx %i1, L2_LDAC, %i3
264	or %i2, %i3, %i4
265
266	cmp %g4, %i4
267	bne %xcc, test_fail
268	nop
269
270	clear_l2_ESR_0x40:
271	setx L2_ES_W1C_VALUE, %g7, %g2
272	stx %g2, [%g1]
273	membar #Sync
274
275	check_l2_EAR_0x40:
276	setx L2EA_PA0, %g7, %g1
277	ldx [%g1], %g2
278	setx 0x3000aa00, %g7, %g3
279	cmp %g3, %g2
280	bne test_fail
281	nop
282
283	check_DESR_L2C_0x40:
284	ldxa [%g0] 0x4c, %g1
285	setx 0xff00000000000000, %g7, %g2
286	and %g1, %g2, %g3
287	setx 0xb500000000000000, %g7, %g4
288	cmp %g3, %g4
289	! bne %xcc, test_failed
290	nop
291
292	done
293	nop
294
295
296