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* OpenSPARC T2 Processor File: n2_ras_vec_l2_da_ce_trap.s
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#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
#define MAIN_PAGE_HV_ALSO
#define L2_ENTRY_PA 0xa000000000
#define TEST_DATA1 0x5555555555555555
#define L2_ENTRY_PA0 0x30000008
#define L2_ES_W1C_VALUE 0xc03ffffc00000000
#define SPARC_ES_W1C_VALUE 0xefffffff
#define L2_ESR_MASK 0xf03ffffff0000000
.global My_Corrected_ECC_error_trap
.global My_Recoverable_Sw_error_trap
! Boot code does not provide TLB translation for IO address space
ldxa [%g0]ASI_INTR_ID, %o6
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
set_L2_Directly_Mapped_Mode_errorsteer:
mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER
setx TEST_DATA1, %l0, %g5
setx 0x3000aa00, %l0, %g2 ! bits [21:18] select way
setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
setx L2_ENTRY_PA, %l0, %g4
and %g2, %l2, %g5 !g2 has L2 PA,
or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
! Flip one bits to inject error
reading_back_0: !Load to L2 again to get the error
setx 0x3000aa00, %l0, %g2
! Loop until gets first trap
/**********************************************
***********************************************/
setx 0x1000aa00, %l0, %g2
setx 0x2000aa00, %l0, %g2
! Loop until gets first trap
/*******************************************************
*******************************************************/
My_Corrected_ECC_error_trap:
setx L2_ESR_MASK, %g7, %g3
setx L2_ES_W1C_VALUE, %g7, %g2
setx 0x3000aa00, %g7, %g3
setx 0xff00000000000000, %g7, %g2
setx 0xa900000000000000, %g7, %g4
My_Recoverable_Sw_error_trap:
setx L2_ESR_MASK, %g7, %g3
setx L2_ES_W1C_VALUE, %g7, %g2
setx 0x3000aa00, %g7, %g3
setx 0xff00000000000000, %g7, %g2
setx 0xb500000000000000, %g7, %g4