[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_mcu_dac_ErrorCntReg1.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_mcu_dac_ErrorCntReg1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define  L2_ERR_STAT_REG    0xAB00000000
#define  L2_ERR_ADDR_REG    0xAC00000000

#define  TEST_DATA0         0x1000100081c3e008
#define  TEST_DATA1         0x2000200081c3e008
#define  TEST_DATA2         0x3000300081c3e008
#define  L2_ES_W1C_VALUE    0xc03ffffc00000000
#define  DRAM_ES_W1C_VALUE  0xfe00000000000000

#ifdef MCU0
#define L2_BANK_ADDR        0x0       
#define MCU_BANK_ADDR       0x0
#define  DRAM_ERR_INJ_REG   0x8400000290
#define  DRAM_ERR_STAT_REG  0x8400000280
#define  DRAM_ERR_COUNTER_REG	0x8400000298
#endif

#ifdef MCU1
#define L2_BANK_ADDR        0x80
#define MCU_BANK_ADDR       0x80
#define  DRAM_ERR_INJ_REG   0x8400001290
#define  DRAM_ERR_STAT_REG  0x8400001280
#define  DRAM_ERR_COUNTER_REG	0x8400001298
#endif

#ifdef MCU2
#define L2_BANK_ADDR        0x100
#define MCU_BANK_ADDR       0x100
#define  DRAM_ERR_INJ_REG   0x8400002290
#define  DRAM_ERR_STAT_REG  0x8400002280
#define  ERROR_ADDR         0x20200100
#define  DRAM_ERR_COUNTER_REG   0x8400002298
#endif

#ifdef MCU3
#define L2_BANK_ADDR        0x180
#define MCU_BANK_ADDR       0x180
#define  DRAM_ERR_INJ_REG   0x8400003290
#define  DRAM_ERR_STAT_REG  0x8400003280
#define  DRAM_ERR_COUNTER_REG   0x8400003298
#endif


#define		L2_ESR_MASK	0xf03ffffff0000000
#define		L2_VEC		36
#define		L2_LDWC		51
#define		L2_LDAC		53
#define         L2_DAC 		42

#define		MCU_DAC		61


#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global  main


main:
  ta T_CHANGE_HPRIV


disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


dram_error_count_reg:
	setx	DRAM_ERR_COUNTER_REG, %g7, %g1
	mov	COUNT, %g2
	stx	%g2, [%g1]


! MSA 01/04/07: Set Continuous error Injection
set_DRAM_error_inject_ch0:
  mov   0x2, %l1                ! ECC Mask (1-bit error)
!  mov   0x1, %l2 		
!  sllx  %l2, DRAM_EI_SSHOT, %l3
!  Or    %l1, %l3, %l1           
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6 
  stx   %l1, [%g6]
  membar 0x40


store_to_L2:
  	setx  TEST_DATA1, %l0, %g5

set_L2_Directly_Mapped_Mode_errorsteer:
        setx    L2CS_PA0, %l6, %g1
        add     %g1, L2_BANK_ADDR, %g1

        ldx     [%g1], %o6

        mov     0x2, %o5                ! L2_CSR_REG<1>=1 => DM mode

        ldxa    [%g0]ASI_INTR_ID, %o4   ! get the thread id; for core-portable
        sllx    %o4, 15, %o4            ! L2_CSR_REG<21:15> = ERROR_STEER

        or      %o5, %o4, %o5

        or      %o6, %o5, %o6
        stx     %o6, [%g1]
        membar  0x40


store_to_L2_way0:
  	setx	0x2200a000, %l0, %g2  ! bits [21:18] select way
  	add	%g2, L2_BANK_ADDR, %g2
  	stx 	%g5, [%g2]
  	stx 	%g5, [%g2+8]

  	add	%g2, 0x200, %g2
  	stx 	%g5, [%g2]
  	stx 	%g5, [%g2+8]

  	add   	%g2, 0x200, %g2
  	stx 	%g5, [%g2]
  	stx 	%g5, [%g2+8]

	add	%g2, 0x200, %g2
	stx	%g5, [%g2]
	stx	%g5, [%g2+8]

	add	%g2, 0x200, %g2
	stx	%g5, [%g2]
	stx	%g5, [%g2+8]

	add	%g2, 0x200, %g2
	stx	%g5, [%g2]
	stx	%g5, [%g2+8]

  	membar 	#Sync

	! Inject error to 0x2200a000, 0x2200a200, 0x2200a400
	! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_wb_0:
  	setx	0x2100a000, %l0, %g3 ! bits [21:18] select way
  	add 	%g3, L2_BANK_ADDR, %g3
  	stx 	%g5, [%g3]
  	stx 	%g5, [%g3+8]

  	add 	%g3, 0x200, %g3
  	stx 	%g5, [%g3]
  	stx 	%g5, [%g3+8]

  	add 	%g3, 0x200, %g3
  	stx 	%g5, [%g3]
  	stx 	%g5, [%g3+8]

	add	%g3, 0x200, %g3
	stx	%g5, [%g3]
	stx	%g5, [%g3+8]

	add	%g3, 0x200, %g3
	stx	%g5, [%g3]
	stx	%g5, [%g3+8]

	add	%g3, 0x200, %g3
	stx	%g5, [%g3]
	stx	%g5, [%g3+8]
  	membar 	#Sync

read_error_address_1:
	setx	0x2200a000, %l0, %g2  ! bits [21:18] select way
        add     %g2, L2_BANK_ADDR, %g2
  	ldx	[%g2], %l1
  	membar 	#Sync

	! Loop until gets MCU ESR logged
	set	0x100, %o2
        setx    DRAM_ERR_STAT_REG, %g7, %g1
loop_1:
        dec	%o2
	cmp	%o2, %g0
	be	test_fail	!Time out
	nop

	ldx	[%g1], %g3
	cmp	%g3, %g0
	be	%xcc, loop_1
	nop

clear_mcuesr1:
	setx	DRAM_ES_W1C_VALUE, %g7, %o3
	stx	%o3, [%g1]
  
soc_esr1:
        setx    SOC_ESR_REG, %g7, %g4
	ldx	[%g4], %i6

read_error_address_2:
	add	%g2, 0x200, %g2
  	ldx	[%g2], %l1
  	membar 	#Sync

	! Loop until gets MCU ESR logged
	set	0x100, %o2
loop_2:
      	dec	%o2
	cmp	%o2, %g0
	be	test_fail	!Time out
	nop

	ldx	[%g1], %g3
        cmp     %g3, %g0
        be      %xcc, loop_2
        nop

clear_mcuesr2:
        stx     %o3, [%g1]

soc_esr2:
        ldx     [%g4], %i6


read_error_address_3:
        add     %g2, 0x200, %g2
	ldx	[%g2], %l1
        membar 	#Sync

        ! Loop until gets MCU ESR logged
        set     0x100, %o2
loop_3:
        dec     %o2
        cmp     %o2, %g0
        be      test_fail       !Time out
        nop

        ldx     [%g1], %g3
        cmp     %g3, %g0
        be      %xcc, loop_3
        nop


	! Check for SOC ESR 
	set	0x20, %o2
trap_loop:
	dec	%o2
	cmp	%o2, %g0
	be	test_fail	!Time out
	nop

soc_esr3:
	ldx	[%g4], %g5
	mov	1, %g3
	sllx	%g3, EXP_ERR, %g3
	setx	0x8000000000000000,  %g7, %g4
	or	%g3, %g4, %g3
	cmp	%g5, %g3
	bne	%xcc, trap_loop
	nop

clear_mcuesr3:
        stx     %o3, [%g1]


test_pass:
ta  T_GOOD_TRAP

test_fail:
ta  T_BAD_TRAP

/************************************
       	Trap Handler 
************************************/
My_Corrected_ECC_error_trap:
	inc	%i0

check_l2_ESR_0x63:
	setx  L2ES_PA0, %l6, %g1
	ldx   [%g1], %g2

	setx	L2_ESR_MASK, %g7, %g3
	and	%g2, %g3, %g4

check_DAC_0x63:
	mov	0x1, %i1
	sllx	%i1, L2_VEC, %i2
	sllx	%i1, L2_DAC, %i3
	or	%i2, %i3, %i4

	cmp	%g4, %i4
	bne	%xcc, test_fail
	nop

clear_l2_ESR_0x63:
	setx	L2_ES_W1C_VALUE, %g7, %g2
	stx	%g2, [%g1]
	membar	#Sync

check_l2_EAR_0x63:
	setx	L2EA_PA0, %g7, %g1
	ldx	[%g1], %g2
	setx	0xffffffffffffffc0, %g7, %g5 
	and	%g2, %g5, %g2
	setx	0x2200aa00, %g7, %g3
	cmp	%g3, %g2
	bne	test_fail
	nop

check_mcu_esr:
	setx	DRAM_ERR_STAT_REG, %g7, %g1
	ldx	[%g1], %g2

	mov	0x1, %g6
	sllx	%g6, MCU_DAC, %g3
	set	0x0002, %g5
	or	%g3, %g5, %g4

	cmp	%g4, %g2
	bne	%xcc, test_fail
	nop

	
check_DESR_L2C_0x63:
	ldxa	[%g0] 0x4c, %g1
	setx	0xff00000000000000, %g7, %g2
	and	%g1, %g2, %g3
	setx	0x8900000000000000, %g7, %g4
	cmp	%g3, %g4
	bne	 %xcc, test_fail
        nop

	retry
        nop
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_mcu_dac_ErrorCntReg1.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define L2_ERR_STAT_REG 0xAB00000000
	42	#define L2_ERR_ADDR_REG 0xAC00000000
	43
	44	#define TEST_DATA0 0x1000100081c3e008
	45	#define TEST_DATA1 0x2000200081c3e008
	46	#define TEST_DATA2 0x3000300081c3e008
	47	#define L2_ES_W1C_VALUE 0xc03ffffc00000000
	48	#define DRAM_ES_W1C_VALUE 0xfe00000000000000
	49
	50	#ifdef MCU0
	51	#define L2_BANK_ADDR 0x0
	52	#define MCU_BANK_ADDR 0x0
	53	#define DRAM_ERR_INJ_REG 0x8400000290
	54	#define DRAM_ERR_STAT_REG 0x8400000280
	55	#define DRAM_ERR_COUNTER_REG 0x8400000298
	56	#endif
	57
	58	#ifdef MCU1
	59	#define L2_BANK_ADDR 0x80
	60	#define MCU_BANK_ADDR 0x80
	61	#define DRAM_ERR_INJ_REG 0x8400001290
	62	#define DRAM_ERR_STAT_REG 0x8400001280
	63	#define DRAM_ERR_COUNTER_REG 0x8400001298
	64	#endif
65
66	#ifdef MCU2
67	#define L2_BANK_ADDR 0x100
68	#define MCU_BANK_ADDR 0x100
69	#define DRAM_ERR_INJ_REG 0x8400002290
70	#define DRAM_ERR_STAT_REG 0x8400002280
71	#define ERROR_ADDR 0x20200100
72	#define DRAM_ERR_COUNTER_REG 0x8400002298
73	#endif
74
75	#ifdef MCU3
76	#define L2_BANK_ADDR 0x180
77	#define MCU_BANK_ADDR 0x180
78	#define DRAM_ERR_INJ_REG 0x8400003290
79	#define DRAM_ERR_STAT_REG 0x8400003280
80	#define DRAM_ERR_COUNTER_REG 0x8400003298
81	#endif
82
83
84	#define L2_ESR_MASK 0xf03ffffff0000000
85	#define L2_VEC 36
86	#define L2_LDWC 51
87	#define L2_LDAC 53
88	#define L2_DAC 42
89
90	#define MCU_DAC 61
91
92
93
94	#include "hboot.s"
95	#include "asi_s.h"
96	#include "err_defines.h"
97
98
99	.text
100	.global main
101
102
103
104	main:
105	ta T_CHANGE_HPRIV
106
107
108	disable_l1:
109	ldxa [%g0] ASI_LSU_CONTROL, %l0
110	! Remove the lower 2 bits (I-Cache and D-Cache enables)
111	andn %l0, 0x3, %l0
112	stxa %l0, [%g0] ASI_LSU_CONTROL
113
114
115	dram_error_count_reg:
116	setx DRAM_ERR_COUNTER_REG, %g7, %g1
117	mov COUNT, %g2
118	stx %g2, [%g1]
119
120
121	! MSA 01/04/07: Set Continuous error Injection
122	set_DRAM_error_inject_ch0:
123	mov 0x2, %l1 ! ECC Mask (1-bit error)
124	! mov 0x1, %l2
125	! sllx %l2, DRAM_EI_SSHOT, %l3
126	! Or %l1, %l3, %l1
127	mov 0x1, %l2
128	sllx %l2, DRAM_EI_ENB, %l3
129	or %l1, %l3, %l1 ! Enable error injection for the next write
130	setx DRAM_ERR_INJ_REG, %l3, %g6
131	stx %l1, [%g6]
132	membar 0x40
133
134
135	store_to_L2:
136	setx TEST_DATA1, %l0, %g5
137
138	set_L2_Directly_Mapped_Mode_errorsteer:
139	setx L2CS_PA0, %l6, %g1
140	add %g1, L2_BANK_ADDR, %g1
141
142	ldx [%g1], %o6
143
144	mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
145
146	ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
147	sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER
148
149	or %o5, %o4, %o5
150
151	or %o6, %o5, %o6
152	stx %o6, [%g1]
153	membar 0x40
154
155
156	store_to_L2_way0:
157	setx 0x2200a000, %l0, %g2 ! bits [21:18] select way
158	add %g2, L2_BANK_ADDR, %g2
159	stx %g5, [%g2]
160	stx %g5, [%g2+8]
161
162	add %g2, 0x200, %g2
163	stx %g5, [%g2]
164	stx %g5, [%g2+8]
165
166	add %g2, 0x200, %g2
167	stx %g5, [%g2]
168	stx %g5, [%g2+8]
169
170	add %g2, 0x200, %g2
171	stx %g5, [%g2]
172	stx %g5, [%g2+8]
173
174	add %g2, 0x200, %g2
175	stx %g5, [%g2]
176	stx %g5, [%g2+8]
177
178	add %g2, 0x200, %g2
179	stx %g5, [%g2]
180	stx %g5, [%g2+8]
181
182	membar #Sync
183
184	! Inject error to 0x2200a000, 0x2200a200, 0x2200a400
185	! Storing to same L2 way0 but different tag,this will write to mcu
186	write_mcu_wb_0:
187	setx 0x2100a000, %l0, %g3 ! bits [21:18] select way
188	add %g3, L2_BANK_ADDR, %g3
189	stx %g5, [%g3]
190	stx %g5, [%g3+8]
191
192	add %g3, 0x200, %g3
193	stx %g5, [%g3]
194	stx %g5, [%g3+8]
195
196	add %g3, 0x200, %g3
197	stx %g5, [%g3]
198	stx %g5, [%g3+8]
199
200	add %g3, 0x200, %g3
201	stx %g5, [%g3]
202	stx %g5, [%g3+8]
203
204	add %g3, 0x200, %g3
205	stx %g5, [%g3]
206	stx %g5, [%g3+8]
207
208	add %g3, 0x200, %g3
209	stx %g5, [%g3]
210	stx %g5, [%g3+8]
211	membar #Sync
212
213	read_error_address_1:
214	setx 0x2200a000, %l0, %g2 ! bits [21:18] select way
215	add %g2, L2_BANK_ADDR, %g2
216	ldx [%g2], %l1
217	membar #Sync
218
219	! Loop until gets MCU ESR logged
220	set 0x100, %o2
221	setx DRAM_ERR_STAT_REG, %g7, %g1
222	loop_1:
223	dec %o2
224	cmp %o2, %g0
225	be test_fail !Time out
226	nop
227
228	ldx [%g1], %g3
229	cmp %g3, %g0
230	be %xcc, loop_1
231	nop
232
233	clear_mcuesr1:
234	setx DRAM_ES_W1C_VALUE, %g7, %o3
235	stx %o3, [%g1]
236
237	soc_esr1:
238	setx SOC_ESR_REG, %g7, %g4
239	ldx [%g4], %i6
240
241	read_error_address_2:
242	add %g2, 0x200, %g2
243	ldx [%g2], %l1
244	membar #Sync
245
246	! Loop until gets MCU ESR logged
247	set 0x100, %o2
248	loop_2:
249	dec %o2
250	cmp %o2, %g0
251	be test_fail !Time out
252	nop
253
254	ldx [%g1], %g3
255	cmp %g3, %g0
256	be %xcc, loop_2
257	nop
258
259	clear_mcuesr2:
260	stx %o3, [%g1]
261
262	soc_esr2:
263	ldx [%g4], %i6
264
265
266	read_error_address_3:
267	add %g2, 0x200, %g2
268	ldx [%g2], %l1
269	membar #Sync
270
271	! Loop until gets MCU ESR logged
272	set 0x100, %o2
273	loop_3:
274	dec %o2
275	cmp %o2, %g0
276	be test_fail !Time out
277	nop
278
279	ldx [%g1], %g3
280	cmp %g3, %g0
281	be %xcc, loop_3
282	nop
283
284
285	! Check for SOC ESR
286	set 0x20, %o2
287	trap_loop:
288	dec %o2
289	cmp %o2, %g0
290	be test_fail !Time out
291	nop
292
293	soc_esr3:
294	ldx [%g4], %g5
295	mov 1, %g3
296	sllx %g3, EXP_ERR, %g3
297	setx 0x8000000000000000, %g7, %g4
298	or %g3, %g4, %g3
299	cmp %g5, %g3
300	bne %xcc, trap_loop
301	nop
302
303	clear_mcuesr3:
304	stx %o3, [%g1]
305
306
307
308	test_pass:
309	ta T_GOOD_TRAP
310
311	test_fail:
312	ta T_BAD_TRAP
313
314	/************************************
315	Trap Handler
316	************************************/
317	My_Corrected_ECC_error_trap:
318	inc %i0
319
320	check_l2_ESR_0x63:
321	setx L2ES_PA0, %l6, %g1
322	ldx [%g1], %g2
323
324	setx L2_ESR_MASK, %g7, %g3
325	and %g2, %g3, %g4
326
327	check_DAC_0x63:
328	mov 0x1, %i1
329	sllx %i1, L2_VEC, %i2
330	sllx %i1, L2_DAC, %i3
331	or %i2, %i3, %i4
332
333	cmp %g4, %i4
334	bne %xcc, test_fail
335	nop
336
337	clear_l2_ESR_0x63:
338	setx L2_ES_W1C_VALUE, %g7, %g2
339	stx %g2, [%g1]
340	membar #Sync
341
342	check_l2_EAR_0x63:
343	setx L2EA_PA0, %g7, %g1
344	ldx [%g1], %g2
345	setx 0xffffffffffffffc0, %g7, %g5
346	and %g2, %g5, %g2
347	setx 0x2200aa00, %g7, %g3
348	cmp %g3, %g2
349	bne test_fail
350	nop
351
352	check_mcu_esr:
353	setx DRAM_ERR_STAT_REG, %g7, %g1
354	ldx [%g1], %g2
355
356	mov 0x1, %g6
357	sllx %g6, MCU_DAC, %g3
358	set 0x0002, %g5
359	or %g3, %g5, %g4
360
361	cmp %g4, %g2
362	bne %xcc, test_fail
363	nop
364
365
366	check_DESR_L2C_0x63:
367	ldxa [%g0] 0x4c, %g1
368	setx 0xff00000000000000, %g7, %g2
369	and %g1, %g2, %g3
370	setx 0x8900000000000000, %g7, %g4
371	cmp %g3, %g4
372	bne %xcc, test_fail
373	nop
374
375	retry
376	nop
377
378
379