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* OpenSPARC T2 Processor File: n2_ras_vec_mcu_dac_ErrorCntReg1.s
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#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define L2_ERR_STAT_REG 0xAB00000000
#define L2_ERR_ADDR_REG 0xAC00000000
#define TEST_DATA0 0x1000100081c3e008
#define TEST_DATA1 0x2000200081c3e008
#define TEST_DATA2 0x3000300081c3e008
#define L2_ES_W1C_VALUE 0xc03ffffc00000000
#define DRAM_ES_W1C_VALUE 0xfe00000000000000
#define MCU_BANK_ADDR 0x0
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define DRAM_ERR_COUNTER_REG 0x8400000298
#define L2_BANK_ADDR 0x80
#define MCU_BANK_ADDR 0x80
#define DRAM_ERR_INJ_REG 0x8400001290
#define DRAM_ERR_STAT_REG 0x8400001280
#define DRAM_ERR_COUNTER_REG 0x8400001298
#define L2_BANK_ADDR 0x100
#define MCU_BANK_ADDR 0x100
#define DRAM_ERR_INJ_REG 0x8400002290
#define DRAM_ERR_STAT_REG 0x8400002280
#define ERROR_ADDR 0x20200100
#define DRAM_ERR_COUNTER_REG 0x8400002298
#define L2_BANK_ADDR 0x180
#define MCU_BANK_ADDR 0x180
#define DRAM_ERR_INJ_REG 0x8400003290
#define DRAM_ERR_STAT_REG 0x8400003280
#define DRAM_ERR_COUNTER_REG 0x8400003298
#define L2_ESR_MASK 0xf03ffffff0000000
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
setx DRAM_ERR_COUNTER_REG, %g7, %g1
! MSA 01/04/07: Set Continuous error Injection
set_DRAM_error_inject_ch0:
mov 0x2, %l1 ! ECC Mask (1-bit error)
! sllx %l2, DRAM_EI_SSHOT, %l3
sllx %l2, DRAM_EI_ENB, %l3
or %l1, %l3, %l1 ! Enable error injection for the next write
setx DRAM_ERR_INJ_REG, %l3, %g6
setx TEST_DATA1, %l0, %g5
set_L2_Directly_Mapped_Mode_errorsteer:
add %g1, L2_BANK_ADDR, %g1
mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER
setx 0x2200a000, %l0, %g2 ! bits [21:18] select way
add %g2, L2_BANK_ADDR, %g2
! Inject error to 0x2200a000, 0x2200a200, 0x2200a400
! Storing to same L2 way0 but different tag,this will write to mcu
setx 0x2100a000, %l0, %g3 ! bits [21:18] select way
add %g3, L2_BANK_ADDR, %g3
setx 0x2200a000, %l0, %g2 ! bits [21:18] select way
add %g2, L2_BANK_ADDR, %g2
! Loop until gets MCU ESR logged
setx DRAM_ERR_STAT_REG, %g7, %g1
setx DRAM_ES_W1C_VALUE, %g7, %o3
setx SOC_ESR_REG, %g7, %g4
! Loop until gets MCU ESR logged
! Loop until gets MCU ESR logged
setx 0x8000000000000000, %g7, %g4
/************************************
************************************/
My_Corrected_ECC_error_trap:
setx L2_ESR_MASK, %g7, %g3
setx L2_ES_W1C_VALUE, %g7, %g2
setx 0xffffffffffffffc0, %g7, %g5
setx 0x2200aa00, %g7, %g3
setx DRAM_ERR_STAT_REG, %g7, %g1
setx 0xff00000000000000, %g7, %g2
setx 0x8900000000000000, %g7, %g4