[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_SPU_interrupt.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: interrupt_SPU_interrupt.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define SPU_TIMEOUT 0x100

#define H_HT0_Control_Word_Queue_Interrupt_0x3c
#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
        call    my_CWQ_Interrupt_trap; \
        nop; \
        retry; \
        nop; 


#include "hboot.s"
#include "asi_s.h"


/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:
	! Switch to Hypervisor mode.

	ta	T_CHANGE_HPRIV
	nop
	
	! This code was modified from isa3_spu_cwq_tcp.s diag

        wr	%g0, 0x40, %asi		! setup ASI register to point to SPU
	
	! Make sure CWQ is currently disabled, not busy,
	! not terminated, no protocol error; else fail
checkCWQ:
	ldxa	[%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
	and	%l1, 0xf, %l2
	cmp	%g0, %l2
	bne,pn	%xcc, test_failed
	nop
	
	! Allocate control word queue
	! (e.g., setup head/tail/first/last registers)
allowcateCWQ:
	setx CWQ_BASE, %g1, %l6

	! First pointer
firstPtr:
	stxa	%l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
	setx	0x0000ffffffffffff, %l5, %l0	! Mask off upper 16 bits
	and	%l0, %l6, %l2
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop
headPtr:	
	! Head Pointer

	stxa	%l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop
	
	! Tail pointer
tailPtr:	
	stxa	%l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop
	
	! Last pointer
lastPtr:	
	setx	CWQ_LAST, %g1, %l5
	stxa	%l5, [%g0 + ASI_SPU_CWQ_LAST] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
	and	%l0, %l5, %l2		!# Mask off upper 16 bits
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop
	
	! Build the initial control word, for the first RC4 vector.
	! First build up word 0
	! For RC4, set op = 65, Enc=1, SOB=EOB=1, SFAS=0,
	! AuthType=8, EncType=00, status=0, Len=30
	! For interrupt, set Int = 1 and Strand ID = thread ID.
buildControlWord:	
	setx	0xc1E101080000001D, %l1, %l2
        ta      T_RD_THID		! Get thread # within this core
	and	%o1, 7, %o1
	sllx	%o1, 37, %o1
	or	%l2, %o1, %l2		! Set this thread to get interrupt

	! %l6 points to CWQ_BASE
	! Note:	All CWQ entry addresses must be physical!

	stx	%l2, [%l6 + 0x0]
	
	! Write source address to next CW field
sourceAddr:
	setx	cleartext_1, %g1, %l2
	stx	%l2, [%l6+0x8]

	! Write 0's to the next 5 CW fields as they are not used
zeroFiveEntries:
	stx	%g0, [%l6+0x10]

	setx	crc_iv_2, %g1, %l2
	stx	%l2, [%l6+0x18]

	stx	%g0, [%l6+0x20]
	stx	%g0, [%l6+0x28] 
	stx	%g0, [%l6+0x30]

	! Finally write destination address to last CW field
destinationAddr:
	setx result_1, %g1, %o3
	stx	%o3, [%l6 + 0x38] 
	
	! Make sure all these stores get to memory before we start

	membar #Sync

	! Now add 1 (actually 8*8B) to tail pointer 
incrementTail:
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
	add	%l2, 0x40, %l2
	stxa	%l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop
	
	! Kick off the CWQ operation by writing to the CWQ_CSR
	! Set the enabled bit and reset the other bits 
startOp:
	or	%g0, 0x1, %g1
	stxa	%g1,	[%g0 + ASI_SPU_CWQ_CSR] %asi	

	! set maximum wait loop count, setup mask for busy bit
	! This timeout may need adjustment
initWait:
	setx	SPU_TIMEOUT, %o3, %l3
	or	%g0, 0x2, %l2		! mask out all but the busy bit

	! loop on busy to fall through when done or loop count exceeded
waitLoop:
	ldxa	[%g0 + ASI_SPU_CWQ_CSR] %asi,	%l1
	andcc	%l1, %l2, %l1
	be	checkData
	addcc	%l3, -1, %l3
	bgt	waitLoop
	nop
	ba	test_failed
	nop

	! check the results...first check the data
checkData:
	or	%g0, 0x1, %i0
	setx	result_1, %g1, %l5
	setx	ciphertext_1, %g1, %l6
	or	%g0, %g0, %g3
dataLoop:
	ldx	[%l5 + %g3], %l1
	ldx	[%l6 + %g3], %l2
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	add	%g3, 0x8, %g3	!# i++
	addcc	%i0, -1, %i0
	bgt	dataLoop
	nop

	! Check to make sure an interrupt occured.
checkIntr:
	setx	cwq_intr_count, %l7, %l6
	ld	[%l6], %l5
	cmp	%l5, 1
	bne,pn	%icc, test_failed
	nop

	! Done
done:	
	ba	test_passed
	nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/**********************************************************************
   Trap handlers.
**********************************************************************/

.global my_CWQ_Interrupt_trap

my_CWQ_Interrupt_trap:
        ! Increment the count

        setx    cwq_intr_count, %g6, %g7
        ld      [%g7], %g5
        add     %g5, 1, %g5
        st      %g5, [%g7]
        membar  #Sync

        jmpl    %o7+0x8, %g0
        nop


/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:

cwq_intr_count:
	.word	0x0

	! Data used for steam (SPU) load/store testing

	! input data
	.align 16
cleartext_1:		
	.xword	0xDEECA425C5AF7185
	.xword	0xB128069258CF5271
	.xword	0xF2D9FC0493661FF4
	.xword	0x4C6DC5810067DEAD	
	 
	! expected ciphertext
	.align 16
ciphertext_1:	
	.xword	0x2e2dBEEFDEADBEEF

	.align 16
result_1:	
	.xword	0xDEADBEEFDEADBEEF

crc_iv_2:	
	.xword	0x0000BEEFDEADBEEF
	
	! CWQ data area, set aside 512 CW's worth
	! 512*8*8 = 32K

	.align 32*1024
CWQ_BASE:		
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.align 32*1024
CWQ_LAST:	.xword 0x0

user_data_end:
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: interrupt_SPU_interrupt.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40	#define SPU_TIMEOUT 0x100
	41
	42	#define H_HT0_Control_Word_Queue_Interrupt_0x3c
	43	#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
	44	call my_CWQ_Interrupt_trap; \
	45	nop; \
	46	retry; \
	47	nop;
	48
	49
	50	#include "hboot.s"
	51	#include "asi_s.h"
	52
	53
	54	/************************************************************************
	55	Test case code start
	56	************************************************************************/
	57
	58	.text
	59	.global main
	60
	61	main:
	62	! Switch to Hypervisor mode.
	63
	64	ta T_CHANGE_HPRIV
65	nop
66
67	! This code was modified from isa3_spu_cwq_tcp.s diag
68
69	wr %g0, 0x40, %asi ! setup ASI register to point to SPU
70
71	! Make sure CWQ is currently disabled, not busy,
72	! not terminated, no protocol error; else fail
73	checkCWQ:
74	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
75	and %l1, 0xf, %l2
76	cmp %g0, %l2
77	bne,pn %xcc, test_failed
78	nop
79
80	! Allocate control word queue
81	! (e.g., setup head/tail/first/last registers)
82	allowcateCWQ:
83	setx CWQ_BASE, %g1, %l6
84
85	! First pointer
86	firstPtr:
87	stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
88	ldxa [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
89	setx 0x0000ffffffffffff, %l5, %l0 ! Mask off upper 16 bits
90	and %l0, %l6, %l2
91	cmp %l1, %l2
92	bne,pn %xcc, test_failed
93	nop
94	headPtr:
95	! Head Pointer
96
97	stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
98	ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
99	cmp %l1, %l2
100	bne,pn %xcc, test_failed
101	nop
102
103	! Tail pointer
104	tailPtr:
105	stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
106	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
107	cmp %l1, %l2
108	bne,pn %xcc, test_failed
109	nop
110
111	! Last pointer
112	lastPtr:
113	setx CWQ_LAST, %g1, %l5
114	stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
115	ldxa [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
116	and %l0, %l5, %l2 !# Mask off upper 16 bits
117	cmp %l1, %l2
118	bne,pn %xcc, test_failed
119	nop
120
121	! Build the initial control word, for the first RC4 vector.
122	! First build up word 0
123	! For RC4, set op = 65, Enc=1, SOB=EOB=1, SFAS=0,
124	! AuthType=8, EncType=00, status=0, Len=30
125	! For interrupt, set Int = 1 and Strand ID = thread ID.
126	buildControlWord:
127	setx 0xc1E101080000001D, %l1, %l2
128	ta T_RD_THID ! Get thread # within this core
129	and %o1, 7, %o1
130	sllx %o1, 37, %o1
131	or %l2, %o1, %l2 ! Set this thread to get interrupt
132
133	! %l6 points to CWQ_BASE
134	! Note: All CWQ entry addresses must be physical!
135
136	stx %l2, [%l6 + 0x0]
137
138	! Write source address to next CW field
139	sourceAddr:
140	setx cleartext_1, %g1, %l2
141	stx %l2, [%l6+0x8]
142
143	! Write 0's to the next 5 CW fields as they are not used
144	zeroFiveEntries:
145	stx %g0, [%l6+0x10]
146
147	setx crc_iv_2, %g1, %l2
148	stx %l2, [%l6+0x18]
149
150	stx %g0, [%l6+0x20]
151	stx %g0, [%l6+0x28]
152	stx %g0, [%l6+0x30]
153
154	! Finally write destination address to last CW field
155	destinationAddr:
156	setx result_1, %g1, %o3
157	stx %o3, [%l6 + 0x38]
158
159	! Make sure all these stores get to memory before we start
160
161	membar #Sync
162
163	! Now add 1 (actually 8*8B) to tail pointer
164	incrementTail:
165	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
166	add %l2, 0x40, %l2
167	stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
168	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
169	cmp %l1, %l2
170	bne,pn %xcc, test_failed
171	nop
172
173	! Kick off the CWQ operation by writing to the CWQ_CSR
174	! Set the enabled bit and reset the other bits
175	startOp:
176	or %g0, 0x1, %g1
177	stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
178
179	! set maximum wait loop count, setup mask for busy bit
180	! This timeout may need adjustment
181	initWait:
182	setx SPU_TIMEOUT, %o3, %l3
183	or %g0, 0x2, %l2 ! mask out all but the busy bit
184
185	! loop on busy to fall through when done or loop count exceeded
186	waitLoop:
187	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
188	andcc %l1, %l2, %l1
189	be checkData
190	addcc %l3, -1, %l3
191	bgt waitLoop
192	nop
193	ba test_failed
194	nop
195
196	! check the results...first check the data
197	checkData:
198	or %g0, 0x1, %i0
199	setx result_1, %g1, %l5
200	setx ciphertext_1, %g1, %l6
201	or %g0, %g0, %g3
202	dataLoop:
203	ldx [%l5 + %g3], %l1
204	ldx [%l6 + %g3], %l2
205	cmp %l1, %l2
206	bne,pn %xcc, test_failed
207	add %g3, 0x8, %g3 !# i++
208	addcc %i0, -1, %i0
209	bgt dataLoop
210	nop
211
212	! Check to make sure an interrupt occured.
213	checkIntr:
214	setx cwq_intr_count, %l7, %l6
215	ld [%l6], %l5
216	cmp %l5, 1
217	bne,pn %icc, test_failed
218	nop
219
220	! Done
221	done:
222	ba test_passed
223	nop
224
225	test_passed:
226	EXIT_GOOD
227
228	test_failed:
229	EXIT_BAD
230
231
232	/**********************************************************************
233	Trap handlers.
234	**********************************************************************/
235
236	.global my_CWQ_Interrupt_trap
237
238	my_CWQ_Interrupt_trap:
239	! Increment the count
240
241	setx cwq_intr_count, %g6, %g7
242	ld [%g7], %g5
243	add %g5, 1, %g5
244	st %g5, [%g7]
245	membar #Sync
246
247	jmpl %o7+0x8, %g0
248	nop
249
250
251
252	/************************************************************************
253	Test case data start
254	************************************************************************/
255	.data
256	user_data_start:
257
258	cwq_intr_count:
259	.word 0x0
260
261	! Data used for steam (SPU) load/store testing
262
263	! input data
264	.align 16
265	cleartext_1:
266	.xword 0xDEECA425C5AF7185
267	.xword 0xB128069258CF5271
268	.xword 0xF2D9FC0493661FF4
269	.xword 0x4C6DC5810067DEAD
270
271	! expected ciphertext
272	.align 16
273	ciphertext_1:
274	.xword 0x2e2dBEEFDEADBEEF
275
276	.align 16
277	result_1:
278	.xword 0xDEADBEEFDEADBEEF
279
280	crc_iv_2:
281	.xword 0x0000BEEFDEADBEEF
282
283	! CWQ data area, set aside 512 CW's worth
284	! 51288 = 32K
285
286	.align 32*1024
287	CWQ_BASE:
288	.xword 0xAAAAAAAAAAAAAAA
289	.xword 0xAAAAAAAAAAAAAAA
290	.xword 0xAAAAAAAAAAAAAAA
291	.xword 0xAAAAAAAAAAAAAAA
292	.xword 0xAAAAAAAAAAAAAAA
293	.xword 0xAAAAAAAAAAAAAAA
294	.xword 0xAAAAAAAAAAAAAAA
295	.xword 0xAAAAAAAAAAAAAAA
296	.align 32*1024
297	CWQ_LAST: .xword 0x0
298
299	user_data_end:
300	.end
301
302