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* OpenSPARC T2 Processor File: interrupt_SPU_interrupt.s
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#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define SPU_TIMEOUT 0x100
#define H_HT0_Control_Word_Queue_Interrupt_0x3c
#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
call my_CWQ_Interrupt_trap; \
/************************************************************************
************************************************************************/
! Switch to Hypervisor mode.
! This code was modified from isa3_spu_cwq_tcp.s diag
wr %g0, 0x40, %asi ! setup ASI register to point to SPU
! Make sure CWQ is currently disabled, not busy,
! not terminated, no protocol error; else fail
ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
! Allocate control word queue
! (e.g., setup head/tail/first/last registers)
stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
ldxa [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
setx 0x0000ffffffffffff, %l5, %l0 ! Mask off upper 16 bits
stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
ldxa [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
and %l0, %l5, %l2 !# Mask off upper 16 bits
! Build the initial control word, for the first RC4 vector.
! For RC4, set op = 65, Enc=1, SOB=EOB=1, SFAS=0,
! AuthType=8, EncType=00, status=0, Len=30
! For interrupt, set Int = 1 and Strand ID = thread ID.
setx 0xc1E101080000001D, %l1, %l2
ta T_RD_THID ! Get thread # within this core
or %l2, %o1, %l2 ! Set this thread to get interrupt
! Note: All CWQ entry addresses must be physical!
! Write source address to next CW field
setx cleartext_1, %g1, %l2
! Write 0's to the next 5 CW fields as they are not used
! Finally write destination address to last CW field
! Make sure all these stores get to memory before we start
! Now add 1 (actually 8*8B) to tail pointer
ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
! Kick off the CWQ operation by writing to the CWQ_CSR
! Set the enabled bit and reset the other bits
stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
! set maximum wait loop count, setup mask for busy bit
! This timeout may need adjustment
setx SPU_TIMEOUT, %o3, %l3
or %g0, 0x2, %l2 ! mask out all but the busy bit
! loop on busy to fall through when done or loop count exceeded
ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
! check the results...first check the data
setx ciphertext_1, %g1, %l6
! Check to make sure an interrupt occured.
setx cwq_intr_count, %l7, %l6
/**********************************************************************
**********************************************************************/
.global my_CWQ_Interrupt_trap
setx cwq_intr_count, %g6, %g7
/************************************************************************
************************************************************************/
! Data used for steam (SPU) load/store testing
.xword 0xDEECA425C5AF7185
.xword 0xB128069258CF5271
.xword 0xF2D9FC0493661FF4
.xword 0x4C6DC5810067DEAD
.xword 0x2e2dBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0x0000BEEFDEADBEEF
! CWQ data area, set aside 512 CW's worth