[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_niu_regs_rw.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: interrupt_niu_regs_rw.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "asi_s.h"
#include "niu_defines.h"

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:

	! Switch to hypervisor mode.

	ta	T_CHANGE_HPRIV
	nop
	ta	T_CHANGE_PRIV
	nop
pstate:	
	rdpr	%pstate, %l0
	and	%l0, 0x2, %l1
	wrpr	%l0, %l1, %pstate	! Disable interrupts

	wr	%g0, ASI_PRIMARY_LITTLE, %asi	! The NCU is little endian

	! Test the Recieve DMA Control and Status register.

rx_dma_ctl_stat_write1:
	setx	RX_DMA_CTL_STAT, %l0, %l1
	setx	RX_DMA_CTL_STAT_COUNT, %l0, %l2
	setx	RX_DMA_CTL_STAT_STEP, %l0, %l3
	sub	%g0, 1, %l4		! data of all 1's

rx_dma_ctl_stat_write1_loop_top:
	stxa	%l4, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	rx_dma_ctl_stat_write1_loop_top
	dec	%l2

rx_dma_ctl_stat_read1:
	setx	RX_DMA_CTL_STAT, %l0, %l1
	setx	RX_DMA_CTL_STAT_COUNT, %l0, %l2
	setx	0x8000ffffffff, %l0, %l6		! mask for RW fields

rx_dma_ctl_stat_read1_loop_top:
	ldxa	[%l1]%asi, %l7
	and	%l7, %l6, %l7
	cmp	%l7, %l6
	bne	test_failed
	nop
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	rx_dma_ctl_stat_read1_loop_top
	dec	%l2

rx_dma_ctl_stat_write0:
	setx	RX_DMA_CTL_STAT, %l0, %l1
	setx	RX_DMA_CTL_STAT_COUNT, %l0, %l2
	setx	RX_DMA_CTL_STAT_STEP, %l0, %l3

rx_dma_ctl_stat_write0_loop_top:
	stxa	%g0, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	rx_dma_ctl_stat_write0_loop_top
	dec	%l2

rx_dma_ctl_stat_read0:
	setx	RX_DMA_CTL_STAT, %l0, %l1
	setx	RX_DMA_CTL_STAT_COUNT, %l0, %l2
	setx	0x8000ffffffff, %l0, %l6		! mask for RW fields

rx_dma_ctl_stat_read0_loop_top:
	ldxa	[%l1]%asi, %l7
	and	%l7, %l6, %l7
	cmp	%l7, 0
	bne	test_failed
	nop
	add     %l1, %l3, %l1
	cmp	%l2, 1
	bne	rx_dma_ctl_stat_read0_loop_top
	dec	%l2

	! Test the Logical Device Group Number registers.

ldg_num1:
	setx	LDG_NUM, %l1, %l2
	set	LDG_NUM_COUNT, %l3
	set	LDG_NUM_STEP, %l4

ldg_num_write0_loop_top:
	stxa	%g0, [%l2]%asi		! Write 0's to LDG_NUM register
	add	%l2, %l4, %l2
	cmp	%l3, 1
	bne	ldg_num_write0_loop_top
	dec	%l3

ldg_num2:
	setx	LDG_NUM, %l1, %l2
	set	LDG_NUM_COUNT, %l3

ldg_num_read0_loop_top:
	ldxa	[%l2]%asi, %l7
	cmp	%l7, 0			! Expect all 0's read back
	bne	test_failed
	nop
	add	%l2, %l4, %l2
	cmp	%l3, 1
	bne	ldg_num_read0_loop_top
	dec	%l3

ldg_num3:
	setx	LDG_NUM, %l1, %l2
	set	LDG_NUM_COUNT, %l3
	sub	%g0, 1, %l5

ldg_num_write1_loop_top:
	stxa	%l5, [%l2]%asi		! Write 1's to LDG_NUM register
	add	%l2, %l4, %l2
	cmp	%l3, 1
	bne	ldg_num_write1_loop_top
	dec	%l3

ldg_num4:
	setx	LDG_NUM, %l1, %l2
	set	LDG_NUM_COUNT, %l3

ldg_num_read1_loop_top:
	ldxa	[%l2]%asi, %l7
	cmp	%l7, 0x3f			! Expect 0x3f read back
	bne	test_failed
	nop
	add	%l2, %l4, %l2
	cmp	%l3, 1
	bne	ldg_num_read1_loop_top
	dec	%l3

	! Test the Logical Device State Vector 0 registers
	! These are read only registers

ldsv0:
	setx	LDSV0, %l0, %l1
	set	LDSV0_COUNT, %l2
	setx	LDSV0_STEP, %l0, %l3

ldsv0_loop_top:
	ldxa	[%l1]%asi, %l7
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ldsv0_loop_top
	dec	%l2

	! Test the Logical Device State Vector 1 registers
	! These are read only registers

ldsv1:
	setx	LDSV1, %l0, %l1
!	set	LDSV1_COUNT, %l2
	set	1, %l2
	setx	LDSV1_STEP, %l0, %l3

ldsv1_loop_top:
	ldxa	[%l1]%asi, %l7
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ldsv1_loop_top
	dec	%l2

	! Test the Logical Device State Vector 2 registers
	! These are read only registers

ldsv2:
	setx	LDSV2, %l0, %l1
!	set	LDSV2_COUNT, %l2
	set	1, %l2
	setx	LDSV2_STEP, %l0, %l3

ldsv2_loop_top:
	ldxa	[%l1]%asi, %l7
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ldsv2_loop_top
	dec	%l2

	! Test the Logical Device Interrupt Mask 0 register.
	
ld_im0_write1:
	setx	LD_IM0, %l0, %l1
!	set	LD_IM0_COUNT, %l2
	set	1, %l2
	setx	LD_IM0_STEP, %l0, %l3
	sub	%g0, 1, %l4		! Data of all 1's

ld_im0_write1_loop_top:
	stxa	%l4, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ld_im0_write1_loop_top
	dec	%l2

ld_im0_read1:	
	setx	LD_IM0, %l0, %l1
	set	LD_IM0_COUNT, %l2

ld_im0_read1_loop_top:
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 3		! Exp. data = 3 since only bits 1:0 are R/W
	bne	test_failed
	nop
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ld_im0_read1_loop_top
	dec	%l2

ld_im0_write0:
	setx	LD_IM0, %l0, %l1
	set	LD_IM0_COUNT, %l2

ld_im0_write0_loop_top:
	stxa	%g0, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ld_im0_write0_loop_top
	dec	%l2

ld_im0_read0:
	setx	LD_IM0, %l0, %l1
	set	LD_IM0_COUNT, %l2

ld_im0_read0_loop_top:
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ld_im0_read0_loop_top
	dec	%l2

	! Test the Logical Device Interrupt Mask 1 register.
	
ld_im1_write1:
	setx	LD_IM1, %l0, %l1
!	set	LD_IM1_COUNT, %l2
	set	1, %l2
	setx	LD_IM1_STEP, %l0, %l3
	sub	%g0, 1, %l4		! Data of all 1's

ld_im1_write1_loop_top:
	stxa	%l4, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ld_im1_write1_loop_top
	dec	%l2

ld_im1_read1:	
	setx	LD_IM1, %l0, %l1
	set	LD_IM1_COUNT, %l2

ld_im1_read1_loop_top:
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 3		! Exp. data = 3 since only bits 1:0 are R/W
	bne	test_failed
	nop
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ld_im1_read1_loop_top
	dec	%l2

ld_im1_write0:
	setx	LD_IM1, %l0, %l1
	set	LD_IM1_COUNT, %l2

ld_im1_write0_loop_top:
	stxa	%g0, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ld_im1_write0_loop_top
	dec	%l2

ld_im1_read0:
	setx	LD_IM1, %l0, %l1
	set	LD_IM1_COUNT, %l2

ld_im1_read0_loop_top:
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ld_im1_read0_loop_top
	dec	%l2

	! Test the Logical Device Group Interrupt Management registers

ldgimgn_write1:
	setx	LDGIMGN, %l0, %l1
	setx	LDGIMGN_COUNT, %l0, %l2
	setx	LDGIMGN_STEP, %l0, %l3
	sub	%g0, 1, %l4			! Data of all 1's

ldgimgn_write1_loop_top:
	stxa	%l4, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ldgimgn_write1_loop_top
	dec	%l2

ldgimgn_read1:
	setx	LDGIMGN, %l0, %l1
	setx	LDGIMGN_COUNT, %l0, %l2

ldgimgn_read1_loop_top:
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0		! Since this contains a countdown timer,
	beq	test_failed	! value is not known.
	nop
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ldgimgn_read1_loop_top
	dec	%l2

ldgimgn_write0:
	setx	LDGIMGN, %l0, %l1
	setx	LDGIMGN_COUNT, %l0, %l2

ldgimgn_write0_loop_top:
	stxa	%g0, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ldgimgn_write0_loop_top
	dec	%l2

ldgimgn_read0:
	setx	LDGIMGN, %l0, %l1
	setx	LDGIMGN_COUNT, %l0, %l2

ldgimgn_read0_loop_top:
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	ldgimgn_read0_loop_top
	dec	%l2

	! Test the Logical Device Group Interrupt Timer Resolution register.

ldgitmres_write1:
	setx	LDGITMRES, %l0, %l1
	sub	%g0, 1, %l4
	stxa	%l4, [%l1]%asi

ldgitmres_read1:
	setx	0xfffff, %l0, %l4	! Only bits [19:0] are R/W
	ldxa	[%l1]%asi, %l7
	cmp	%l7, %l4
	bne	test_failed
	nop

ldgitmres_write0:
	setx	LDGITMRES, %l0, %l1

	stxa	%g0, [%l1]%asi

ldgitmres_read0:
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop

	! Test the System Interrupt Data registers.

sid_write1:
	setx	SID, %l0, %l1
	setx	SID_COUNT, %l0, %l2
	setx	SID_STEP, %l0, %l3
	sub	%g0, 1, %l4		! Data of all 1's

sid_write1_loop_top:
	stxa	%l4, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	sid_write1_loop_top
	dec	%l2

sid_read1:
	setx	SID, %l0, %l1
	setx	SID_COUNT, %l0, %l2

sid_read1_loop_top:	
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0x7f		! Only bits [6:0] are R/W
	bne	test_failed
	nop
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	sid_read1_loop_top
	dec	%l2

sid_write0:
	setx	SID, %l0, %l1
	setx	SID_COUNT, %l0, %l2
	setx	SID_STEP, %l0, %l3

sid_write0_loop_top:
	stxa	%g0, [%l1]%asi
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	sid_write0_loop_top
	dec	%l2

sid_read0:
	setx	SID, %l0, %l1
	setx	SID_COUNT, %l0, %l2

sid_read0_loop_top:	
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop
	add	%l1, %l3, %l1
	cmp	%l2, 1
	bne	sid_read0_loop_top
	dec	%l2

	! Test the Tx_xMac Status Registers

tx_xmac_status0_read:
	setx	xtxmac_status0_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop	

tx_xmac_status1_read:
	setx	xtxmac_status1_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop	

	! Test the Rx_xMac Status Registers

rx_xmac_status0_read:
	setx	xrxmac_status0_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop	

rx_xmac_status1_read:
	setx	xrxmac_status1_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop	

	! Test the xMac Flow Control Status Registers

xmac_flow_stat0_read:
	setx	xmac_flow_stat0_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop	

xmac_flow_stat1_read:
	setx	xmac_flow_stat1_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0
	bne	test_failed
	nop

	! Test the xMac Flow Control Status Mask Registers

xmac_flow_stat_mask0_read:
	setx	xmac_flow_msk0_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 7
	bne	test_failed
	nop	

xmac_flow_stat_mask1_read:
	setx	xmac_flow_msk1_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 7
	bne	test_failed
	nop

	! Test the Tx_xMac Status Mask Registers

tx_xmac_mask0_read:
	setx	xtxmac_stat_msk0_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0xfff
	bne	test_failed
	nop	

tx_xmac_mask1_read:
	setx	xtxmac_stat_msk1_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, 0xfff
	bne	test_failed
	nop	

	! Test the Rx_xMac Status Mask Registers

	setx	0xfffff, %l0, %l6
rx_xmac_mask0_read:
	setx	xrxmac_stat_msk0_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, %l6
	bne	test_failed
	nop	

rx_xmac_mask1_read:
	setx	xrxmac_stat_msk1_addr, %l0, %l1
	ldxa	[%l1]%asi, %l7
	cmp	%l7, %l6
	bne	test_failed
	nop	

	! Done

	ba	test_passed
	nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
	.word	0x0
	.word	0x0
user_data_end:	
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: interrupt_niu_regs_rw.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#include "hboot.s"
	42	#include "asi_s.h"
	43	#include "niu_defines.h"
	44
	45	/************************************************************************
	46	Test case code start
	47	************************************************************************/
	48
	49	.text
	50	.global main
	51
	52	main:
	53
	54	! Switch to hypervisor mode.
	55
	56	ta T_CHANGE_HPRIV
	57	nop
	58	ta T_CHANGE_PRIV
	59	nop
	60	pstate:
	61	rdpr %pstate, %l0
	62	and %l0, 0x2, %l1
	63	wrpr %l0, %l1, %pstate ! Disable interrupts
	64
65	wr %g0, ASI_PRIMARY_LITTLE, %asi ! The NCU is little endian
66
67	! Test the Recieve DMA Control and Status register.
68
69	rx_dma_ctl_stat_write1:
70	setx RX_DMA_CTL_STAT, %l0, %l1
71	setx RX_DMA_CTL_STAT_COUNT, %l0, %l2
72	setx RX_DMA_CTL_STAT_STEP, %l0, %l3
73	sub %g0, 1, %l4 ! data of all 1's
74
75	rx_dma_ctl_stat_write1_loop_top:
76	stxa %l4, [%l1]%asi
77	add %l1, %l3, %l1
78	cmp %l2, 1
79	bne rx_dma_ctl_stat_write1_loop_top
80	dec %l2
81
82	rx_dma_ctl_stat_read1:
83	setx RX_DMA_CTL_STAT, %l0, %l1
84	setx RX_DMA_CTL_STAT_COUNT, %l0, %l2
85	setx 0x8000ffffffff, %l0, %l6 ! mask for RW fields
86
87	rx_dma_ctl_stat_read1_loop_top:
88	ldxa [%l1]%asi, %l7
89	and %l7, %l6, %l7
90	cmp %l7, %l6
91	bne test_failed
92	nop
93	add %l1, %l3, %l1
94	cmp %l2, 1
95	bne rx_dma_ctl_stat_read1_loop_top
96	dec %l2
97
98	rx_dma_ctl_stat_write0:
99	setx RX_DMA_CTL_STAT, %l0, %l1
100	setx RX_DMA_CTL_STAT_COUNT, %l0, %l2
101	setx RX_DMA_CTL_STAT_STEP, %l0, %l3
102
103	rx_dma_ctl_stat_write0_loop_top:
104	stxa %g0, [%l1]%asi
105	add %l1, %l3, %l1
106	cmp %l2, 1
107	bne rx_dma_ctl_stat_write0_loop_top
108	dec %l2
109
110	rx_dma_ctl_stat_read0:
111	setx RX_DMA_CTL_STAT, %l0, %l1
112	setx RX_DMA_CTL_STAT_COUNT, %l0, %l2
113	setx 0x8000ffffffff, %l0, %l6 ! mask for RW fields
114
115	rx_dma_ctl_stat_read0_loop_top:
116	ldxa [%l1]%asi, %l7
117	and %l7, %l6, %l7
118	cmp %l7, 0
119	bne test_failed
120	nop
121	add %l1, %l3, %l1
122	cmp %l2, 1
123	bne rx_dma_ctl_stat_read0_loop_top
124	dec %l2
125
126	! Test the Logical Device Group Number registers.
127
128	ldg_num1:
129	setx LDG_NUM, %l1, %l2
130	set LDG_NUM_COUNT, %l3
131	set LDG_NUM_STEP, %l4
132
133	ldg_num_write0_loop_top:
134	stxa %g0, [%l2]%asi ! Write 0's to LDG_NUM register
135	add %l2, %l4, %l2
136	cmp %l3, 1
137	bne ldg_num_write0_loop_top
138	dec %l3
139
140	ldg_num2:
141	setx LDG_NUM, %l1, %l2
142	set LDG_NUM_COUNT, %l3
143
144	ldg_num_read0_loop_top:
145	ldxa [%l2]%asi, %l7
146	cmp %l7, 0 ! Expect all 0's read back
147	bne test_failed
148	nop
149	add %l2, %l4, %l2
150	cmp %l3, 1
151	bne ldg_num_read0_loop_top
152	dec %l3
153
154	ldg_num3:
155	setx LDG_NUM, %l1, %l2
156	set LDG_NUM_COUNT, %l3
157	sub %g0, 1, %l5
158
159	ldg_num_write1_loop_top:
160	stxa %l5, [%l2]%asi ! Write 1's to LDG_NUM register
161	add %l2, %l4, %l2
162	cmp %l3, 1
163	bne ldg_num_write1_loop_top
164	dec %l3
165
166	ldg_num4:
167	setx LDG_NUM, %l1, %l2
168	set LDG_NUM_COUNT, %l3
169
170	ldg_num_read1_loop_top:
171	ldxa [%l2]%asi, %l7
172	cmp %l7, 0x3f ! Expect 0x3f read back
173	bne test_failed
174	nop
175	add %l2, %l4, %l2
176	cmp %l3, 1
177	bne ldg_num_read1_loop_top
178	dec %l3
179
180	! Test the Logical Device State Vector 0 registers
181	! These are read only registers
182
183	ldsv0:
184	setx LDSV0, %l0, %l1
185	set LDSV0_COUNT, %l2
186	setx LDSV0_STEP, %l0, %l3
187
188	ldsv0_loop_top:
189	ldxa [%l1]%asi, %l7
190	add %l1, %l3, %l1
191	cmp %l2, 1
192	bne ldsv0_loop_top
193	dec %l2
194
195	! Test the Logical Device State Vector 1 registers
196	! These are read only registers
197
198	ldsv1:
199	setx LDSV1, %l0, %l1
200	! set LDSV1_COUNT, %l2
201	set 1, %l2
202	setx LDSV1_STEP, %l0, %l3
203
204	ldsv1_loop_top:
205	ldxa [%l1]%asi, %l7
206	add %l1, %l3, %l1
207	cmp %l2, 1
208	bne ldsv1_loop_top
209	dec %l2
210
211	! Test the Logical Device State Vector 2 registers
212	! These are read only registers
213
214	ldsv2:
215	setx LDSV2, %l0, %l1
216	! set LDSV2_COUNT, %l2
217	set 1, %l2
218	setx LDSV2_STEP, %l0, %l3
219
220	ldsv2_loop_top:
221	ldxa [%l1]%asi, %l7
222	add %l1, %l3, %l1
223	cmp %l2, 1
224	bne ldsv2_loop_top
225	dec %l2
226
227	! Test the Logical Device Interrupt Mask 0 register.
228
229	ld_im0_write1:
230	setx LD_IM0, %l0, %l1
231	! set LD_IM0_COUNT, %l2
232	set 1, %l2
233	setx LD_IM0_STEP, %l0, %l3
234	sub %g0, 1, %l4 ! Data of all 1's
235
236	ld_im0_write1_loop_top:
237	stxa %l4, [%l1]%asi
238	add %l1, %l3, %l1
239	cmp %l2, 1
240	bne ld_im0_write1_loop_top
241	dec %l2
242
243	ld_im0_read1:
244	setx LD_IM0, %l0, %l1
245	set LD_IM0_COUNT, %l2
246
247	ld_im0_read1_loop_top:
248	ldxa [%l1]%asi, %l7
249	cmp %l7, 3 ! Exp. data = 3 since only bits 1:0 are R/W
250	bne test_failed
251	nop
252	add %l1, %l3, %l1
253	cmp %l2, 1
254	bne ld_im0_read1_loop_top
255	dec %l2
256
257	ld_im0_write0:
258	setx LD_IM0, %l0, %l1
259	set LD_IM0_COUNT, %l2
260
261	ld_im0_write0_loop_top:
262	stxa %g0, [%l1]%asi
263	add %l1, %l3, %l1
264	cmp %l2, 1
265	bne ld_im0_write0_loop_top
266	dec %l2
267
268	ld_im0_read0:
269	setx LD_IM0, %l0, %l1
270	set LD_IM0_COUNT, %l2
271
272	ld_im0_read0_loop_top:
273	ldxa [%l1]%asi, %l7
274	cmp %l7, 0
275	bne test_failed
276	nop
277	add %l1, %l3, %l1
278	cmp %l2, 1
279	bne ld_im0_read0_loop_top
280	dec %l2
281
282	! Test the Logical Device Interrupt Mask 1 register.
283
284	ld_im1_write1:
285	setx LD_IM1, %l0, %l1
286	! set LD_IM1_COUNT, %l2
287	set 1, %l2
288	setx LD_IM1_STEP, %l0, %l3
289	sub %g0, 1, %l4 ! Data of all 1's
290
291	ld_im1_write1_loop_top:
292	stxa %l4, [%l1]%asi
293	add %l1, %l3, %l1
294	cmp %l2, 1
295	bne ld_im1_write1_loop_top
296	dec %l2
297
298	ld_im1_read1:
299	setx LD_IM1, %l0, %l1
300	set LD_IM1_COUNT, %l2
301
302	ld_im1_read1_loop_top:
303	ldxa [%l1]%asi, %l7
304	cmp %l7, 3 ! Exp. data = 3 since only bits 1:0 are R/W
305	bne test_failed
306	nop
307	add %l1, %l3, %l1
308	cmp %l2, 1
309	bne ld_im1_read1_loop_top
310	dec %l2
311
312	ld_im1_write0:
313	setx LD_IM1, %l0, %l1
314	set LD_IM1_COUNT, %l2
315
316	ld_im1_write0_loop_top:
317	stxa %g0, [%l1]%asi
318	add %l1, %l3, %l1
319	cmp %l2, 1
320	bne ld_im1_write0_loop_top
321	dec %l2
322
323	ld_im1_read0:
324	setx LD_IM1, %l0, %l1
325	set LD_IM1_COUNT, %l2
326
327	ld_im1_read0_loop_top:
328	ldxa [%l1]%asi, %l7
329	cmp %l7, 0
330	bne test_failed
331	nop
332	add %l1, %l3, %l1
333	cmp %l2, 1
334	bne ld_im1_read0_loop_top
335	dec %l2
336
337	! Test the Logical Device Group Interrupt Management registers
338
339	ldgimgn_write1:
340	setx LDGIMGN, %l0, %l1
341	setx LDGIMGN_COUNT, %l0, %l2
342	setx LDGIMGN_STEP, %l0, %l3
343	sub %g0, 1, %l4 ! Data of all 1's
344
345	ldgimgn_write1_loop_top:
346	stxa %l4, [%l1]%asi
347	add %l1, %l3, %l1
348	cmp %l2, 1
349	bne ldgimgn_write1_loop_top
350	dec %l2
351
352	ldgimgn_read1:
353	setx LDGIMGN, %l0, %l1
354	setx LDGIMGN_COUNT, %l0, %l2
355
356	ldgimgn_read1_loop_top:
357	ldxa [%l1]%asi, %l7
358	cmp %l7, 0 ! Since this contains a countdown timer,
359	beq test_failed ! value is not known.
360	nop
361	add %l1, %l3, %l1
362	cmp %l2, 1
363	bne ldgimgn_read1_loop_top
364	dec %l2
365
366	ldgimgn_write0:
367	setx LDGIMGN, %l0, %l1
368	setx LDGIMGN_COUNT, %l0, %l2
369
370	ldgimgn_write0_loop_top:
371	stxa %g0, [%l1]%asi
372	add %l1, %l3, %l1
373	cmp %l2, 1
374	bne ldgimgn_write0_loop_top
375	dec %l2
376
377	ldgimgn_read0:
378	setx LDGIMGN, %l0, %l1
379	setx LDGIMGN_COUNT, %l0, %l2
380
381	ldgimgn_read0_loop_top:
382	ldxa [%l1]%asi, %l7
383	cmp %l7, 0
384	bne test_failed
385	nop
386	add %l1, %l3, %l1
387	cmp %l2, 1
388	bne ldgimgn_read0_loop_top
389	dec %l2
390
391	! Test the Logical Device Group Interrupt Timer Resolution register.
392
393	ldgitmres_write1:
394	setx LDGITMRES, %l0, %l1
395	sub %g0, 1, %l4
396	stxa %l4, [%l1]%asi
397
398	ldgitmres_read1:
399	setx 0xfffff, %l0, %l4 ! Only bits [19:0] are R/W
400	ldxa [%l1]%asi, %l7
401	cmp %l7, %l4
402	bne test_failed
403	nop
404
405	ldgitmres_write0:
406	setx LDGITMRES, %l0, %l1
407
408	stxa %g0, [%l1]%asi
409
410	ldgitmres_read0:
411	ldxa [%l1]%asi, %l7
412	cmp %l7, 0
413	bne test_failed
414	nop
415
416	! Test the System Interrupt Data registers.
417
418	sid_write1:
419	setx SID, %l0, %l1
420	setx SID_COUNT, %l0, %l2
421	setx SID_STEP, %l0, %l3
422	sub %g0, 1, %l4 ! Data of all 1's
423
424	sid_write1_loop_top:
425	stxa %l4, [%l1]%asi
426	add %l1, %l3, %l1
427	cmp %l2, 1
428	bne sid_write1_loop_top
429	dec %l2
430
431	sid_read1:
432	setx SID, %l0, %l1
433	setx SID_COUNT, %l0, %l2
434
435	sid_read1_loop_top:
436	ldxa [%l1]%asi, %l7
437	cmp %l7, 0x7f ! Only bits [6:0] are R/W
438	bne test_failed
439	nop
440	add %l1, %l3, %l1
441	cmp %l2, 1
442	bne sid_read1_loop_top
443	dec %l2
444
445	sid_write0:
446	setx SID, %l0, %l1
447	setx SID_COUNT, %l0, %l2
448	setx SID_STEP, %l0, %l3
449
450	sid_write0_loop_top:
451	stxa %g0, [%l1]%asi
452	add %l1, %l3, %l1
453	cmp %l2, 1
454	bne sid_write0_loop_top
455	dec %l2
456
457	sid_read0:
458	setx SID, %l0, %l1
459	setx SID_COUNT, %l0, %l2
460
461	sid_read0_loop_top:
462	ldxa [%l1]%asi, %l7
463	cmp %l7, 0
464	bne test_failed
465	nop
466	add %l1, %l3, %l1
467	cmp %l2, 1
468	bne sid_read0_loop_top
469	dec %l2
470
471	! Test the Tx_xMac Status Registers
472
473	tx_xmac_status0_read:
474	setx xtxmac_status0_addr, %l0, %l1
475	ldxa [%l1]%asi, %l7
476	cmp %l7, 0
477	bne test_failed
478	nop
479
480	tx_xmac_status1_read:
481	setx xtxmac_status1_addr, %l0, %l1
482	ldxa [%l1]%asi, %l7
483	cmp %l7, 0
484	bne test_failed
485	nop
486
487	! Test the Rx_xMac Status Registers
488
489	rx_xmac_status0_read:
490	setx xrxmac_status0_addr, %l0, %l1
491	ldxa [%l1]%asi, %l7
492	cmp %l7, 0
493	bne test_failed
494	nop
495
496	rx_xmac_status1_read:
497	setx xrxmac_status1_addr, %l0, %l1
498	ldxa [%l1]%asi, %l7
499	cmp %l7, 0
500	bne test_failed
501	nop
502
503	! Test the xMac Flow Control Status Registers
504
505	xmac_flow_stat0_read:
506	setx xmac_flow_stat0_addr, %l0, %l1
507	ldxa [%l1]%asi, %l7
508	cmp %l7, 0
509	bne test_failed
510	nop
511
512	xmac_flow_stat1_read:
513	setx xmac_flow_stat1_addr, %l0, %l1
514	ldxa [%l1]%asi, %l7
515	cmp %l7, 0
516	bne test_failed
517	nop
518
519	! Test the xMac Flow Control Status Mask Registers
520
521	xmac_flow_stat_mask0_read:
522	setx xmac_flow_msk0_addr, %l0, %l1
523	ldxa [%l1]%asi, %l7
524	cmp %l7, 7
525	bne test_failed
526	nop
527
528	xmac_flow_stat_mask1_read:
529	setx xmac_flow_msk1_addr, %l0, %l1
530	ldxa [%l1]%asi, %l7
531	cmp %l7, 7
532	bne test_failed
533	nop
534
535	! Test the Tx_xMac Status Mask Registers
536
537	tx_xmac_mask0_read:
538	setx xtxmac_stat_msk0_addr, %l0, %l1
539	ldxa [%l1]%asi, %l7
540	cmp %l7, 0xfff
541	bne test_failed
542	nop
543
544	tx_xmac_mask1_read:
545	setx xtxmac_stat_msk1_addr, %l0, %l1
546	ldxa [%l1]%asi, %l7
547	cmp %l7, 0xfff
548	bne test_failed
549	nop
550
551	! Test the Rx_xMac Status Mask Registers
552
553	setx 0xfffff, %l0, %l6
554	rx_xmac_mask0_read:
555	setx xrxmac_stat_msk0_addr, %l0, %l1
556	ldxa [%l1]%asi, %l7
557	cmp %l7, %l6
558	bne test_failed
559	nop
560
561	rx_xmac_mask1_read:
562	setx xrxmac_stat_msk1_addr, %l0, %l1
563	ldxa [%l1]%asi, %l7
564	cmp %l7, %l6
565	bne test_failed
566	nop
567
568	! Done
569
570	ba test_passed
571	nop
572
573	test_passed:
574	EXIT_GOOD
575
576	test_failed:
577	EXIT_BAD
578
579
580	/************************************************************************
581	Test case data start
582	************************************************************************/
583	.data
584	user_data_start:
585	.word 0x0
586	.word 0x0
587	user_data_end:
588	.end