* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: interrupt_niu_regs_rw.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
/************************************************************************
************************************************************************/
! Switch to hypervisor mode.
wrpr %l0, %l1, %pstate ! Disable interrupts
wr %g0, ASI_PRIMARY_LITTLE, %asi ! The NCU is little endian
! Test the Recieve DMA Control and Status register.
setx RX_DMA_CTL_STAT, %l0, %l1
setx RX_DMA_CTL_STAT_COUNT, %l0, %l2
setx RX_DMA_CTL_STAT_STEP, %l0, %l3
sub %g0, 1, %l4 ! data of all 1's
rx_dma_ctl_stat_write1_loop_top:
bne rx_dma_ctl_stat_write1_loop_top
setx RX_DMA_CTL_STAT, %l0, %l1
setx RX_DMA_CTL_STAT_COUNT, %l0, %l2
setx 0x8000ffffffff, %l0, %l6 ! mask for RW fields
rx_dma_ctl_stat_read1_loop_top:
bne rx_dma_ctl_stat_read1_loop_top
setx RX_DMA_CTL_STAT, %l0, %l1
setx RX_DMA_CTL_STAT_COUNT, %l0, %l2
setx RX_DMA_CTL_STAT_STEP, %l0, %l3
rx_dma_ctl_stat_write0_loop_top:
bne rx_dma_ctl_stat_write0_loop_top
setx RX_DMA_CTL_STAT, %l0, %l1
setx RX_DMA_CTL_STAT_COUNT, %l0, %l2
setx 0x8000ffffffff, %l0, %l6 ! mask for RW fields
rx_dma_ctl_stat_read0_loop_top:
bne rx_dma_ctl_stat_read0_loop_top
! Test the Logical Device Group Number registers.
stxa %g0, [%l2]%asi ! Write 0's to LDG_NUM register
bne ldg_num_write0_loop_top
cmp %l7, 0 ! Expect all 0's read back
bne ldg_num_read0_loop_top
stxa %l5, [%l2]%asi ! Write 1's to LDG_NUM register
bne ldg_num_write1_loop_top
cmp %l7, 0x3f ! Expect 0x3f read back
bne ldg_num_read1_loop_top
! Test the Logical Device State Vector 0 registers
! These are read only registers
setx LDSV0_STEP, %l0, %l3
! Test the Logical Device State Vector 1 registers
! These are read only registers
setx LDSV1_STEP, %l0, %l3
! Test the Logical Device State Vector 2 registers
! These are read only registers
setx LDSV2_STEP, %l0, %l3
! Test the Logical Device Interrupt Mask 0 register.
setx LD_IM0_STEP, %l0, %l3
sub %g0, 1, %l4 ! Data of all 1's
bne ld_im0_write1_loop_top
cmp %l7, 3 ! Exp. data = 3 since only bits 1:0 are R/W
bne ld_im0_read1_loop_top
bne ld_im0_write0_loop_top
bne ld_im0_read0_loop_top
! Test the Logical Device Interrupt Mask 1 register.
setx LD_IM1_STEP, %l0, %l3
sub %g0, 1, %l4 ! Data of all 1's
bne ld_im1_write1_loop_top
cmp %l7, 3 ! Exp. data = 3 since only bits 1:0 are R/W
bne ld_im1_read1_loop_top
bne ld_im1_write0_loop_top
bne ld_im1_read0_loop_top
! Test the Logical Device Group Interrupt Management registers
setx LDGIMGN_COUNT, %l0, %l2
setx LDGIMGN_STEP, %l0, %l3
sub %g0, 1, %l4 ! Data of all 1's
bne ldgimgn_write1_loop_top
setx LDGIMGN_COUNT, %l0, %l2
cmp %l7, 0 ! Since this contains a countdown timer,
beq test_failed ! value is not known.
bne ldgimgn_read1_loop_top
setx LDGIMGN_COUNT, %l0, %l2
bne ldgimgn_write0_loop_top
setx LDGIMGN_COUNT, %l0, %l2
bne ldgimgn_read0_loop_top
! Test the Logical Device Group Interrupt Timer Resolution register.
setx 0xfffff, %l0, %l4 ! Only bits [19:0] are R/W
! Test the System Interrupt Data registers.
sub %g0, 1, %l4 ! Data of all 1's
cmp %l7, 0x7f ! Only bits [6:0] are R/W
! Test the Tx_xMac Status Registers
setx xtxmac_status0_addr, %l0, %l1
setx xtxmac_status1_addr, %l0, %l1
! Test the Rx_xMac Status Registers
setx xrxmac_status0_addr, %l0, %l1
setx xrxmac_status1_addr, %l0, %l1
! Test the xMac Flow Control Status Registers
setx xmac_flow_stat0_addr, %l0, %l1
setx xmac_flow_stat1_addr, %l0, %l1
! Test the xMac Flow Control Status Mask Registers
xmac_flow_stat_mask0_read:
setx xmac_flow_msk0_addr, %l0, %l1
xmac_flow_stat_mask1_read:
setx xmac_flow_msk1_addr, %l0, %l1
! Test the Tx_xMac Status Mask Registers
setx xtxmac_stat_msk0_addr, %l0, %l1
setx xtxmac_stat_msk1_addr, %l0, %l1
! Test the Rx_xMac Status Mask Registers
setx xrxmac_stat_msk0_addr, %l0, %l1
setx xrxmac_stat_msk1_addr, %l0, %l1
/************************************************************************
************************************************************************/