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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_prod_cons2_pio.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tso_n1_prod_cons2_pio.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39#define spinlock_addr_reg %o0
40#define data_base_reg %o1
41#define my_id_reg %o3
42#define test_reg %o4
43#define global_cnt_reg %o5
44#define tmp1 %l1
45
46#define ITERATIONS 0x2
47
48#include "hboot.s"
49
50.global main
51
52main:
53ta T_CHANGE_HPRIV
54nop
55 wr %g0, 0x4, %fprs /* make sure fef is 1 */
56 setx spinlock_address, %l0, spinlock_addr_reg ! spinlock address
57 set ITERATIONS, global_cnt_reg !
58
59th_fork(th_main,%l0)
60
61!Some of the threads are producers, some are consumers
62! A pair of producer and consumer has the same ID.
63!=====================================================
64th_main_0:
65 add %g0, 0x8, my_id_reg ! this is my ID address
66 ba producer
67 nop
68
69th_main_1:
70 add %g0, 0x10, my_id_reg
71 ba consumer
72 nop
73
74th_main_2:
75 add %g0, 0x18, my_id_reg
76 ba consumer
77 nop
78
79th_main_3:
80 add %g0, 0x20, my_id_reg
81 ba consumer
82 nop
83
84th_main_4:
85 add %g0, 0x28, my_id_reg
86 ba consumer
87 nop
88
89th_main_5:
90 add %g0, 0x30, my_id_reg
91 ba consumer
92 nop
93
94th_main_6:
95 add %g0, 0x38, my_id_reg
96 ba consumer
97 nop
98
99th_main_7:
100 add %g0, 0x40, my_id_reg
101 ba consumer
102 nop
103
104!====================================================================================
105producer:
106wait1:
107 ld [spinlock_addr_reg + 0x10], test_reg ! try to acquire lock
108 tst test_reg ! did we get it?
109 bne wait1
110 nop
111wait2:
112 ld [spinlock_addr_reg + 0x18], test_reg ! try to acquire lock
113 tst test_reg ! did we get it?
114 bne wait2
115 nop
116wait3:
117 ld [spinlock_addr_reg + 0x20], test_reg ! try to acquire lock
118 tst test_reg ! did we get it?
119 bne wait3
120 nop
121wait4:
122 ld [spinlock_addr_reg + 0x28], test_reg ! try to acquire lock
123 tst test_reg ! did we get it?
124 bne wait4
125 nop
126wait5:
127 ld [spinlock_addr_reg + 0x30], test_reg ! try to acquire lock
128 tst test_reg ! did we get it?
129 bne wait5
130 nop
131wait6:
132 ld [spinlock_addr_reg + 0x38], test_reg ! try to acquire lock
133 tst test_reg ! did we get it?
134 bne wait6
135 nop
136wait7:
137 ld [spinlock_addr_reg + 0x40], test_reg ! try to acquire lock
138 tst test_reg ! did we get it?
139 bne wait7
140 nop
141 ba producer_gotlock
142 nop
143
144!====================================================================================
145consumer:
146 ld [spinlock_addr_reg + my_id_reg], test_reg ! try to acquire lock
147 sub test_reg, 0x55, %i1 ! code to end the test
148 tst %i1
149 be good_end ! end the test
150 nop
151 sub test_reg, 0x1, %i1 ! code for available data
152 tst %i1
153 be check_consumer_type
154 nop
155 ba consumer
156 nop
157
158check_consumer_type:
159 andcc my_id_reg, 0x8, %i1
160 bne consumer_gotlock2
161 nop
162 ba consumer_gotlock
163 nop
164
165
166!====================================================================================
167producer_gotlock:
168
169 set 0x60, %l0
170 setx protected_area, tmp1, data_base_reg
171producer_loop0:
172 st %g0, [data_base_reg + my_id_reg] ! cleanup
173 add data_base_reg, 0x40, data_base_reg ! increment the address
174 deccc %l0
175 bne producer_loop0 ! repeat
176 nop
177
178 set 0x60, %l0
179 setx protected_area, tmp1, data_base_reg
180producer_loop1:
181 st my_id_reg, [data_base_reg + my_id_reg] ! store my ID in there
182 add data_base_reg, 0x40, data_base_reg ! increment the address
183 deccc %l0
184 bne producer_loop1 ! repeat
185 nop
186
187 deccc global_cnt_reg
188 be cleanup_and_finish
189 nop
190 add %g0, 1 , tmp1
191 st tmp1, [spinlock_addr_reg + 0x10] ! data ready
192 st tmp1, [spinlock_addr_reg + 0x18] ! data ready
193 st tmp1, [spinlock_addr_reg + 0x20] ! data ready
194 st tmp1, [spinlock_addr_reg + 0x28] ! data ready
195 st tmp1, [spinlock_addr_reg + 0x30] ! data ready
196 st tmp1, [spinlock_addr_reg + 0x38] ! data ready
197 st tmp1, [spinlock_addr_reg + 0x40] ! data ready
198 ba producer
199 nop
200
201cleanup_and_finish:
202 add %g0, 0x55 , tmp1
203 st tmp1, [spinlock_addr_reg + 0x10] ! data ready
204 st tmp1, [spinlock_addr_reg + 0x18] ! data ready
205 st tmp1, [spinlock_addr_reg + 0x20] ! data ready
206 st tmp1, [spinlock_addr_reg + 0x28] ! data ready
207 st tmp1, [spinlock_addr_reg + 0x30] ! data ready
208 st tmp1, [spinlock_addr_reg + 0x38] ! data ready
209 st tmp1, [spinlock_addr_reg + 0x40] ! data ready
210 ba good_end
211 nop
212
213!====================================================================================
214consumer_gotlock:
215 set 0x60, %l0
216 setx protected_area, tmp1, data_base_reg
217 mov 0x8, %i1
218consumer_loop1:
219 ld [data_base_reg + 0x8], %i2 ! load producer's ID in there
220 subcc %i2, %i1, %g0
221 bne bad_end
222 nop
223 add data_base_reg, 0x40, data_base_reg ! increment the address
224 deccc %l0
225 bne consumer_loop1 ! repeat
226 nop
227
228 st %g0, [spinlock_addr_reg+ my_id_reg] ! consumer ready
229
230 ba consumer
231 nop
232
233consumer_gotlock2:
234 set 0x60, %l0
235 setx protected_area, tmp1, data_base_reg
236 mov 0x8, %i1
237 st %i1, [data_base_reg + my_id_reg] ! store my ID in there
238 ld [data_base_reg + my_id_reg], %f2 ! load producer's ID in there
239consumer_loop2:
240 ld [data_base_reg + 0x8], %f14 ! load producer's ID in there
241 fcmps %fcc0, %f2, %f14 ! should be my ID
242 fbne %fcc0, bad_end
243 nop
244 add data_base_reg, 0x40, data_base_reg ! increment the address
245 deccc %l0
246 bne consumer_loop2 ! repeat
247 nop
248
249 st %g0, [spinlock_addr_reg+ my_id_reg] ! consumer ready
250
251 ba consumer
252 nop
253
254good_end:
255 ta T_GOOD_TRAP
256bad_end:
257 ta T_BAD_TRAP
258
259!==========================
260
261
262SECTION .MY_DATA0 DATA_VA=0xd0100000
263attr_data {
264 Name = .MY_DATA0,
265 VA= 0x0d0100000,
266 RA=0xc000000000,
267 PA=0xc000000000,
268 part_0_ctx_nonzero_tsb_config_0,
269 TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
270 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
271 TTE_L=0, TTE_CP=0, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1
272 }
273
274 .data
275
276.global spinlock_address
277spinlock_address:
278 .skip 0x1000
279
280
281SECTION .MY_DATA1 DATA_VA=0xd1110000
282attr_data {
283 Name = .MY_DATA1,
284 VA= 0x0d1110000,
285 RA=0xc200bee000,
286 PA=0xc200bee000,
287 part_0_ctx_nonzero_tsb_config_1,
288 TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
289 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
290 TTE_L=0, TTE_CP=0, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1
291 }
292
293 .data
294.global protected_area
295protected_area:
296 .word 0xbeef
297 .skip 0x1000
298 .word 0xbeef
299.end
300
Full OpenSPARC design & verification tarball including full HDL.