[OpenSPARC-T2-DV] / verif / diag / assembly / include / kaos_ro_handler.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: kaos_ro_handler.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define LOCAL_HYPERVISOR_SECTION_TEXT_VA 0x20210000
attr_text {
        Name = local_hypervisor_section_text,	
	hypervisor
        }
	
SECTION local_hypervisor_section_text TEXT_VA=LOCAL_SUPERVISOR_SECTION_TEXT_VA
.seg "text"
.global	toggle_tte_w_handler
toggle_tte_w_handler:
 	setx    0xfffff000, %g2, %g3
	and	%g6, %g3, %g6
	or	%g6, 0x44, %g6	
#ifdef CHECK_SFSR_SFAR
        mov     0x18, %g7
        ldxa    [%g7] ASI_PARTITION_ID, %g2         ! get sfsr
        mov     0x20, %g7
        ldxa    [%g7] ASI_PARTITION_ID, %g3         ! get sfar
#endif
toggle_tte_w_conf_0:
	! Load TSB_CONFIG address in %g7
        mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %g7
	
toggle_tte_w_tsbptr_calc:	
!Uses g1-g5, Expects TSB_CONFIG address in %g7, va in %g6, REsults in %g1
!Leave %g6 intact
#include "mmu_ptr_calc.s"	
toggle_w_load_entry:
	setx	0x1fff, %g4, %g2			! 13 context-bits
	and	%g6, %g2, %g2
	sllx	%g2, 48, %g2
	srl	%g6, 22, %g4
	or	%g2, %g4, %g2			
	ldda	[%g1] ASI_NUCLEUS_QUAD_LDD, %g4		! load tte from ps0 tsb
	!ldxa	[%g0] ASI_DMMU_TAG_REG, %g2		! get va/context from tag-target
	cmp	%g2, %g4
	bne	%xcc, toggle_tte_w_check_for_ptr_chase
	nop
	ba	toggle_tte_w_trap_done
	mov	0x80, %g1
	
toggle_tte_w_check_for_ptr_chase:
    cmp %g4, -1         ! if all 1's, follow link
    be,a    %xcc, toggle_tte_w_ptr_chase
    nop

    !! Look up all config registers (1-3)
    !! Gotta do SW table walk through the 3 remaing configs ..
    ! Expect %g7 to stll have addr of last ctx0 config register
    ! and %g6 should have va/context from tag access register

    ! Normalize %g7
    sllx %g6, 51, %g5
    brnz,a %g5, 1f
    sub %g7, 0x20, %g7     ! this executes only if branch taken

1:

    cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1
    bl,a toggle_tte_w_tsbptr_calc
toggle_tte_w_conf_1:
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1, %g7

    cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2
    bl,a toggle_tte_w_tsbptr_calc
toggle_tte_w_conf_2:
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2, %g7

    cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3
    bl,a toggle_tte_w_tsbptr_calc
toggle_tte_w_conf_3:
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g7

#ifndef SUN4V
	sllx	%g5, 15, %g3		! extract size[2]
	srlx	%g3, 61, %g3
	sllx	%g5, 1, %g1		! extract size[1:0]
	srlx	%g1, 62, %g1
	or	%g3, %g1, %g1		! %g1 = size[2:0]
#else
	sllx	%g5, 61, %g1
	srlx	%g1, 61, %g1            ! %g1 = size[2:0]
#endif
	mulx	%g1, 3, %g1
	sub	%g0, 1, %g3
	sllx	%g3, 13, %g3
	sllx	%g3, %g1, %g3
        sethi   %hi(0x00001fff), %g1
        or      %g1, 0xfff, %g1
	or	%g3, %g1, %g3		! %g3 = va/ctxt mask based on size[2:0]

	and	%g2, %g3, %g3		! apply mask
	cmp	%g3, %g4		! check if va/ctxt match
	be	%xcc, toggle_tte_w_trap_done
	nop
	
toggle_tte_w_ptr_chase:
    or  %g5, %g0, %g3           ! %g3 is link-reg
toggle_tte_w_ptr_chase_loop:
    ldda    [%g3] ASI_NUCLEUS_QUAD_LDD, %g4     ! load tte from tsb
    ldxa    [%g0] ASI_DMMU_TAG_REG, %g2     ! get va/context from tag-target
    cmp %g2, %g4
    bne %xcc, toggle_tte_w_follow_link
    nop
    ba  toggle_tte_w_trap_done
    mov ASI_PARTITION_ID_VAL, %g1       ! offset (VA) for patrition id

toggle_tte_w_follow_link:
    ldx [%g3+16], %g3
    cmp %g3, -1
    bne %xcc, toggle_tte_w_ptr_chase_loop ! keep chasing pointer
    nop

toggle_tte_w_next_tsb:
    ! Look up the Next TSB, until done with all TSBs ?
    ! Compare with TSB_CONFIG_3 for ctx0 and TSB_CONFIG_3+0x20 for ctx!0
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g4
    sllx %g6, 51, %g5
    brnz,a %g5, 2f
    sub %g7, 0x20, %g7
2:  
    cmp %g7, %g4
    bl 1b
    nop		

toggle_tte_w_trap_done:
	// check to see if RA[39] is set.
	// RA[39] = 0 means accessing memory space
	// RA[39] = 1 means accessing I/O space
	mov	%g5, %g3
	sllx	%g3, 24, %g3
	srlx	%g3, 63, %g3
	brnz	%g3, toggle_tte_w_skip_part_base	
	! add partition base to data-in
	setx	partition_base_list, %g3, %g2	! for partition base
	ldxa	[%g1] ASI_PARTITION_ID, %g3		! partition id
	sllx	%g3, 3, %g3		! offset - partition list
	ldx	[%g2 + %g3], %g1
	add	%g5, %g1, %g5
toggle_tte_w_skip_part_base:	
	mov	0x30, %g7
#ifndef SUN4V
	mov     0x000, %g6
	mov	0x2, %g1		! set W-bit
#else
	mov	0x400, %g6		
	mov	0x40, %g1		! set W-bit
#endif
	xor	%g1, %g5, %g5
	!stxa	%g4, [ %g7 ] ASI_PARTITION_ID	! {tag-access, data-in}
	stxa	%g5, [ %g6 ] ASI_DTLB_DATA_IN
	retl
	ta T_CHANGE_NONHPRIV 
!!	

	
toggle_tte_w_handler_ext:
	cmp	%g4, -1			! if all 1's, follow link
	be,a	%xcc, toggle_tte_w_ptr_chase
	mov	0, %g7			! remember ptr chase from ps0

    !! Look up all config registers (1-3)
    !! Gotta do SW table walk through the 3 remaing configs ..
    ! Expect %g7 to stll have addr of last ctx0 config register
    ! and %g6 should have va/context from tag access register

    ! Normalize %g7
    sllx %g6, 51, %g5
    brnz,a %g5, 1f
    sub %g7, 0x20, %g7     ! this executes only if branch taken

1:

    cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1
    bl,a toggle_tte_w_tsbptr_calc
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1, %g7

    cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2
    bl,a toggle_tte_w_tsbptr_calc
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2, %g7

    cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3
    bl,a toggle_tte_w_tsbptr_calc
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g7

    ! Now try other crazy stuff, which has not been debugged for N2
    ! TBD TBD TBD TBD TBD

#ifndef SUN4V
	sllx	%g5, 15, %g3		! extract size[2]
	srlx	%g3, 61, %g3
	sllx	%g5, 1, %g1		! extract size[1:0]
	srlx	%g1, 62, %g1
	or	%g3, %g1, %g1		! %g1 = size[2:0]
#else
	sllx	%g5, 61, %g1
	srlx	%g1, 61, %g1            ! %g1 = size[2:0]
#endif
	mulx	%g1, 3, %g1
	sub	%g0, 1, %g3
	sllx	%g3, 13, %g3
	sllx	%g3, %g1, %g3
    sethi   %hi(0x00001fff), %g1
    or      %g1, 0xfff, %g1
	or	%g3, %g1, %g3		! %g3 = va/ctxt mask based on size[2:0]

	and	%g2, %g3, %g3		! apply mask
	cmp	%g3, %g4		! check if va/ctxt match
	be,a	%xcc, toggle_tte_w_trap_done
	mov	0x80, %g1		! offset (VA) for patrition id
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: kaos_ro_handler.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define LOCAL_HYPERVISOR_SECTION_TEXT_VA 0x20210000
	39	attr_text {
	40	Name = local_hypervisor_section_text,
	41	hypervisor
	42	}
	43
	44	SECTION local_hypervisor_section_text TEXT_VA=LOCAL_SUPERVISOR_SECTION_TEXT_VA
	45	.seg "text"
	46	.global toggle_tte_w_handler
	47	toggle_tte_w_handler:
	48	setx 0xfffff000, %g2, %g3
	49	and %g6, %g3, %g6
	50	or %g6, 0x44, %g6
	51	#ifdef CHECK_SFSR_SFAR
	52	mov 0x18, %g7
	53	ldxa [%g7] ASI_PARTITION_ID, %g2 ! get sfsr
	54	mov 0x20, %g7
	55	ldxa [%g7] ASI_PARTITION_ID, %g3 ! get sfar
	56	#endif
	57	toggle_tte_w_conf_0:
	58	! Load TSB_CONFIG address in %g7
	59	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %g7
	60
	61	toggle_tte_w_tsbptr_calc:
	62	!Uses g1-g5, Expects TSB_CONFIG address in %g7, va in %g6, REsults in %g1
	63	!Leave %g6 intact
	64	#include "mmu_ptr_calc.s"
65	toggle_w_load_entry:
66	setx 0x1fff, %g4, %g2 ! 13 context-bits
67	and %g6, %g2, %g2
68	sllx %g2, 48, %g2
69	srl %g6, 22, %g4
70	or %g2, %g4, %g2
71	ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4 ! load tte from ps0 tsb
72	!ldxa [%g0] ASI_DMMU_TAG_REG, %g2 ! get va/context from tag-target
73	cmp %g2, %g4
74	bne %xcc, toggle_tte_w_check_for_ptr_chase
75	nop
76	ba toggle_tte_w_trap_done
77	mov 0x80, %g1
78
79	toggle_tte_w_check_for_ptr_chase:
80	cmp %g4, -1 ! if all 1's, follow link
81	be,a %xcc, toggle_tte_w_ptr_chase
82	nop
83
84	!! Look up all config registers (1-3)
85	!! Gotta do SW table walk through the 3 remaing configs ..
86	! Expect %g7 to stll have addr of last ctx0 config register
87	! and %g6 should have va/context from tag access register
88
89	! Normalize %g7
90	sllx %g6, 51, %g5
91	brnz,a %g5, 1f
92	sub %g7, 0x20, %g7 ! this executes only if branch taken
93
94	1:
95
96	cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1
97	bl,a toggle_tte_w_tsbptr_calc
98	toggle_tte_w_conf_1:
99	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1, %g7
100
101	cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2
102	bl,a toggle_tte_w_tsbptr_calc
103	toggle_tte_w_conf_2:
104	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2, %g7
105
106	cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3
107	bl,a toggle_tte_w_tsbptr_calc
108	toggle_tte_w_conf_3:
109	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g7
110
111	#ifndef SUN4V
112	sllx %g5, 15, %g3 ! extract size[2]
113	srlx %g3, 61, %g3
114	sllx %g5, 1, %g1 ! extract size[1:0]
115	srlx %g1, 62, %g1
116	or %g3, %g1, %g1 ! %g1 = size[2:0]
117	#else
118	sllx %g5, 61, %g1
119	srlx %g1, 61, %g1 ! %g1 = size[2:0]
120	#endif
121	mulx %g1, 3, %g1
122	sub %g0, 1, %g3
123	sllx %g3, 13, %g3
124	sllx %g3, %g1, %g3
125	sethi %hi(0x00001fff), %g1
126	or %g1, 0xfff, %g1
127	or %g3, %g1, %g3 ! %g3 = va/ctxt mask based on size[2:0]
128
129	and %g2, %g3, %g3 ! apply mask
130	cmp %g3, %g4 ! check if va/ctxt match
131	be %xcc, toggle_tte_w_trap_done
132	nop
133
134	toggle_tte_w_ptr_chase:
135	or %g5, %g0, %g3 ! %g3 is link-reg
136	toggle_tte_w_ptr_chase_loop:
137	ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! load tte from tsb
138	ldxa [%g0] ASI_DMMU_TAG_REG, %g2 ! get va/context from tag-target
139	cmp %g2, %g4
140	bne %xcc, toggle_tte_w_follow_link
141	nop
142	ba toggle_tte_w_trap_done
143	mov ASI_PARTITION_ID_VAL, %g1 ! offset (VA) for patrition id
144
145	toggle_tte_w_follow_link:
146	ldx [%g3+16], %g3
147	cmp %g3, -1
148	bne %xcc, toggle_tte_w_ptr_chase_loop ! keep chasing pointer
149	nop
150
151	toggle_tte_w_next_tsb:
152	! Look up the Next TSB, until done with all TSBs ?
153	! Compare with TSB_CONFIG_3 for ctx0 and TSB_CONFIG_3+0x20 for ctx!0
154	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g4
155	sllx %g6, 51, %g5
156	brnz,a %g5, 2f
157	sub %g7, 0x20, %g7
158	2:
159	cmp %g7, %g4
160	bl 1b
161	nop
162
163	toggle_tte_w_trap_done:
164	// check to see if RA[39] is set.
165	// RA[39] = 0 means accessing memory space
166	// RA[39] = 1 means accessing I/O space
167	mov %g5, %g3
168	sllx %g3, 24, %g3
169	srlx %g3, 63, %g3
170	brnz %g3, toggle_tte_w_skip_part_base
171	! add partition base to data-in
172	setx partition_base_list, %g3, %g2 ! for partition base
173	ldxa [%g1] ASI_PARTITION_ID, %g3 ! partition id
174	sllx %g3, 3, %g3 ! offset - partition list
175	ldx [%g2 + %g3], %g1
176	add %g5, %g1, %g5
177	toggle_tte_w_skip_part_base:
178	mov 0x30, %g7
179	#ifndef SUN4V
180	mov 0x000, %g6
181	mov 0x2, %g1 ! set W-bit
182	#else
183	mov 0x400, %g6
184	mov 0x40, %g1 ! set W-bit
185	#endif
186	xor %g1, %g5, %g5
187	!stxa %g4, [ %g7 ] ASI_PARTITION_ID ! {tag-access, data-in}
188	stxa %g5, [ %g6 ] ASI_DTLB_DATA_IN
189	retl
190	ta T_CHANGE_NONHPRIV
191	!!
192
193
194	toggle_tte_w_handler_ext:
195	cmp %g4, -1 ! if all 1's, follow link
196	be,a %xcc, toggle_tte_w_ptr_chase
197	mov 0, %g7 ! remember ptr chase from ps0
198
199	!! Look up all config registers (1-3)
200	!! Gotta do SW table walk through the 3 remaing configs ..
201	! Expect %g7 to stll have addr of last ctx0 config register
202	! and %g6 should have va/context from tag access register
203
204	! Normalize %g7
205	sllx %g6, 51, %g5
206	brnz,a %g5, 1f
207	sub %g7, 0x20, %g7 ! this executes only if branch taken
208
209	1:
210
211	cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1
212	bl,a toggle_tte_w_tsbptr_calc
213	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1, %g7
214
215	cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2
216	bl,a toggle_tte_w_tsbptr_calc
217	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2, %g7
218
219	cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3
220	bl,a toggle_tte_w_tsbptr_calc
221	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g7
222
223	! Now try other crazy stuff, which has not been debugged for N2
224	! TBD TBD TBD TBD TBD
225
226	#ifndef SUN4V
227	sllx %g5, 15, %g3 ! extract size[2]
228	srlx %g3, 61, %g3
229	sllx %g5, 1, %g1 ! extract size[1:0]
230	srlx %g1, 62, %g1
231	or %g3, %g1, %g1 ! %g1 = size[2:0]
232	#else
233	sllx %g5, 61, %g1
234	srlx %g1, 61, %g1 ! %g1 = size[2:0]
235	#endif
236	mulx %g1, 3, %g1
237	sub %g0, 1, %g3
238	sllx %g3, 13, %g3
239	sllx %g3, %g1, %g3
240	sethi %hi(0x00001fff), %g1
241	or %g1, 0xfff, %g1
242	or %g3, %g1, %g3 ! %g3 = va/ctxt mask based on size[2:0]
243
244	and %g2, %g3, %g3 ! apply mask
245	cmp %g3, %g4 ! check if va/ctxt match
246	be,a %xcc, toggle_tte_w_trap_done
247	mov 0x80, %g1 ! offset (VA) for patrition id
248