Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / peu_set_serdes_pll_ratio.s
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: peu_set_serdes_pll_ratio.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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14* This program is distributed in the hope that it will be useful,
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37*/
38#include "ccu_defines.h"
39#include "peu_defines.h"
40
41#define PEU_SERDES_PLL_MPY__100MHZ 7
42#define PEU_SERDES_PLL_MPY__125MHZ 5
43#define PEU_SERDES_PLL_MPY__250MHZ 1
44
45
46#ifdef PCIE_REF_CLK_100
47peu_set_target_pcie_ref_clk_100MHz:
48 mov PEU_SERDES_PLL_MPY__100MHZ, %g4
49#else
50#ifdef PCIE_REF_CLK_125
51peu_set_target_pcie_ref_clk_125MHz:
52 mov PEU_SERDES_PLL_MPY__125MHZ, %g4
53#else
54#ifdef PCIE_REF_CLK_250
55peu_set_target_pcie_ref_clk_250MHz:
56 mov PEU_SERDES_PLL_MPY__250MHZ, %g4
57#endif /* PCIE_REF_CLK_250 */
58#endif /* PCIE_REF_CLK_125 */
59#endif /* PCIE_REF_CLK_100 */
60#if defined(PCIE_REF_CLK_100) || defined(PCIE_REF_CLK_125) || defined(PCIE_REF_CLK_250)
61peu_check_serdes_pll_ratio:
62 best_set_reg(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_ADDR, %g2, %g3)
63 ldx [%g3], %g5
64 sub %g5, %g4, %g5
65 brz %g5, peu_serdes_pll_ratio_already_set
66 nop
67peu_set_serdes_pll_ratio:
68 stx %g4, [%g3] ! set mpy field for 100Mhz refclk
69 ! do a warm reset to activate the new value, per PRM 16.6.6
70 setx RESET_GEN, %g2, %g5 ! warm reset reg
71 add %g0, 0x1, %g7 ! warm reset reg data
72peu_kick_wmr_for_serdes_pll_ratio_change:
73 stx %g7, [%g5] ! Warm Reset
74 ldx [%g5], %g7 ! Force a delay to wait for WMR
75
76peu_serdes_pll_ratio_already_set:
77#endif /*defined(PCIE_REF_CLK_100) || defined(PCIE_REF_CLK_125) || defined(PCIE_REF_CLK_250)*/