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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / cmp1.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: cmp1.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
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16// GNU General Public License for more details.
17//
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21//
22// For the avoidance of doubt, and except that if any non-GPL license
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33//
34// ========== Copyright Header End ============================================
35#ifndef SYSNAME
36#define SYSNAME cmp1
37#define sys(x) cmp1_ ## x
38#define CMP
39#define CMP1
40#define ALL_THREADS 8
41#endif
42
43////////////////////////////////////////////////////////////////////////////////////////////
44//
45// added this group of tests for OpenSparc T2 (called cmp1_mini_T2)
46//
47////////////////////////////////////////////////////////////////////////////////////////////
48
49<sys(mini_T2) sys=cmp1>
50<runargs -sys=cmp1 -tg_seed=1 >
51<runargs -sas -vcs_run_args=+show_delta>
52
53
54// has 6 tests that should pass
55
56<cmp_tso_diag name=cmp_tso_diag>
57<runargs -nosas>
58tso_n1_cross_mod103 tso_n1_cross_mod103.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3
59</runargs>
60</cmp_tso_diag>
61
62<cmp_kaos name=cmp_kaos>
63<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=0f -midas_args=-DNOHWTW>
64 v9_4thread_kaos v9_4th_kao_02_25_04_4.s
65</runargs>
66</cmp_kaos>
67
68<cmp_tlu_fast name=cmp_tlu_fast>
69tlu_halt_park tlu_halt_park.s -vcs_run_args=+thread=all
70</cmp_tlu_fast>
71
72
73<cmp_fgu_traps name=cmp_fgu_traps>
74fgu_stfsr_traps_22 fgu_stfsr_traps_22.s
75</cmp_fgu_traps>
76<cmp_lsu_fast name=cmp_lsu_fast>
77 ld_blk ld_blk.s
78</cmp_lsu_fast>
79
80<cmp_mmu name=cmp_mmu>
81mmu_mt_demap_0 mmu_mt_demap_0.s -midas_args=-DNOHWTW -vcs_run_args=+thread=all
82</cmp_mmu>
83
84</runargs>
85</runargs>
86</sys(mini_T2)>
87
88////////////////////////////////////////////////////////////////////////////////////////////
89//
90// added this group of tests for OpenSparc T2 (called cmp1_all_T2)
91//
92////////////////////////////////////////////////////////////////////////////////////////////
93
94<sys(all_T2) sys=cmp1>
95<runargs -sys=cmp1 -tg_seed=1>
96<runargs -nosas -vcs_run_args=+show_delta>
97
98
99<core_qualify name=core_qualify>
100// Always run with TSO_CHECKER enabled
101<runargs -sas_run_args=-DTSO_CHECKER>
102
103//---tsotool diag {{{
104<runargs -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-allow_tsb_conflicts -fast_boot -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+8_FBDIMMS -vcs_run_args=+l2cpx_errmon_off>
105n2_8tcasxa_2 n2_8tcasxa_2.s
106n2_8t_ldst1_7 n2_8t_ldst1_7.s
107n2_8t_bstbld_1 n2_8t_bstbld_1.s
108</runargs>
109
110//---tsotool diag }}}
111
112//---ccx diag {{{
113<runargs -fast_boot -midas_args=-allow_tsb_conflicts -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DCMP_THREAD_START=ALL -finish_mask=all -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -vcs_run_args=+l2esr_mon_off -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+8_FBDIMMS -midas_args=-DL2_REG_PROG -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2cpx_errmon_off>
114n2_cpx_fill_io_8b n2_cpx_fill_io_8b.s
115n2_cpx_ifill8b n2_cpx_ifill8b.s
116</runargs>
117//---ccx diag }}}
118
119
120//---MPGen diags {{{
121<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-allow_tsb_conflicts>
122mpgen_semi_full_isa_1 mpgen_semi_full_isa_1.s
123mpgen_semi_full_isa_2 mpgen_semi_full_isa_2.s
124mpgen_semi_full_isa_3 mpgen_semi_full_isa_3.s
125mpgen_ldst_mix mpgen_ldst_mix.s
126mpgen_ldst_int_no_asi mpgen_ldst_int_no_asi.s
127mpgen_ldst_all_l2_banks mpgen_ldst_all_l2_banks.s
128mpgen_smc_1 mpgen_smc_1.s
129mpgen_smc_2 mpgen_smc_2.s
130mpgen_smc_3 mpgen_smc_3.s
131mpgen_smc_4 mpgen_smc_4.s
132mpgen_dynamic_spec_cache mpgen_dynamic_spec_cache.s
133mpgen_tso_atomic_1_bank mpgen_tso_atomic_1_bank.s
134</runargs>
135//---MPGen diags }}}
136
137//---TLU_RAND5 diags {{{
138<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+l2cpx_errmon_off>
139<runargs -rtl_timeout=20000 -vcs_run_args=+skt_timeout=20000 -vcs_run_args=+th_timeout=50000>
140tlu_fcrand05_ind_14 tlu_fcrand05_ind_14.s
141// fcrand05_rand_38 fcrand05_rand_38.s -midas_args=-DMULTIPASS=2
142fcrand05_rand_88 fcrand05_rand_88.s -midas_args=-DMULTIPASS=2
143// fcrand05_rand_4 fcrand05_rand_4.s -midas_args=-DMULTIPASS=2
144// fcrand05_rand_37 fcrand05_rand_37.s -midas_args=-DMULTIPASS=2
145// fcrand05_rand_43 fcrand05_rand_43.s -midas_args=-DMULTIPASS=2
146tlu_rand5fc_8149597 tlu_rand5fc_8149597.s -midas_args=-DMULTIPASS=1
147</runargs>
148</runargs>
149//---TLU_RAND5 diags }}}
150
151</runargs>
152</core_qualify>
153
154<lsu_fast name=lsu_fast>
155
156 dcache_diag_test_0 dcache_diag_test_0.s -nosas -vcs_run_args=+gchkr_off
157 lsu_dcache_diagnostic lsu_dcache_diagnostic.s -nosas -vcs_run_args=+gchkr_off
158
159
160 <runargs -midas_args=-allow_tsb_conflicts>
161
162 lsu_ie_01 lsu_ie_01.s
163 lsu_ie_02 lsu_ie_02.s
164 lsu_ie_03 lsu_ie_03.s
165 lsu_ie_04 lsu_ie_04.s
166 lsu_ie_05 lsu_ie_05.s
167 lsu_ie_06 lsu_ie_06.s
168 lsu_ie_07 lsu_ie_07.s
169 lsu_ie_08 lsu_ie_08.s
170 lsu_ie_09 lsu_ie_09.s
171 lsu_ie_10 lsu_ie_10.s
172 lsu_hang_cwp lsu_hang_cwp.s -vcs_run_args=+thread=all -vcs_run_args=+th_timeout=8000 -tg_seed=1
173
174#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
175 lsu_casa_std_pst0 lsu_casa_std_pst0.s
176 lsu_casa_std_pst1 lsu_casa_std_pst1.s
177 lsu_casa_std_pst2 lsu_casa_std_pst2.s
178 lsu_casa_std_pst3 lsu_casa_std_pst3.s
179 lsu_casa_std_pst4 lsu_casa_std_pst4.s
180 lsu_casa_std_pst5 lsu_casa_std_pst5.s
181 lsu_casa_std_pst6 lsu_casa_std_pst6.s
182 lsu_casa_std_pst7 lsu_casa_std_pst7.s
183 lsu_casa_std_pst8 lsu_casa_std_pst8.s
184 lsu_casa_std_pst9 lsu_casa_std_pst9.s
185#endif
186
187 </runargs>
188</lsu_fast>
189#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
190<lsu_long name=lsu_long>
191
192 <runargs -vcs_run_args=+thread=all -sas -midas_args=-allow_tsb_conflicts>
193
194 n2_lsu_arb_hitl1_1.j_652649_rand_0 n2_lsu_arb_hitl1_1.j_652649_rand_0.s -midas_args=-allow_tsb_conflicts
195
196 </runargs>
197</lsu_long>
198#endif
199<lsu_share name=lsu_share>
200
201 <runargs -vcs_run_args=+thread=all -sas -midas_args=-allow_tsb_conflicts>
202
203 ldst_sync_fc0 ldst_sync_fc0.s -vcs_run_args=+hash_on
204 ldst_sync_fc1 ldst_sync_fc1.s -vcs_run_args=+hash_on
205 ldst_sync_fc2 ldst_sync_fc2.s
206 ldst_sync_fc3 ldst_sync_fc3.s
207#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
208 ldst_sync_fc4 ldst_sync_fc4.s -vcs_run_args=+hash_on
209 ldst_sync_fc5 ldst_sync_fc5.s -vcs_run_args=+hash_on
210 ldst_sync_fc6 ldst_sync_fc6.s
211 ldst_sync_fc9 ldst_sync_fc9.s
212 ldst_sync_fc10 ldst_sync_fc10.s -vcs_run_args=+inval_rate=300 -vcs_run_args=+hash_on
213 ldst_sync_fc11 ldst_sync_fc11.s -vcs_run_args=+inval_rate=300 -vcs_run_args=+hash_on
214 ldst_sync_fc13 ldst_sync_fc13.s -vcs_run_args=+inval_rate=400
215 ldst_sync_fc15 ldst_sync_fc15.s -vcs_run_args=+inval_rate=400
216 ldst_sync_fc16 ldst_sync_fc16.s -vcs_run_args=+inval_rate=500
217 ldst_sync_fc17 ldst_sync_fc17.s -vcs_run_args=+inval_rate=500
218 ldst_sync_fc18 ldst_sync_fc18.s -vcs_run_args=+inval_rate=500
219 ldst_sync_fc19 ldst_sync_fc19.s -vcs_run_args=+inval_rate=500
220
221 ifu_basic_ld ifu_basic_ld.s
222 ldst_sync ldst_sync.s
223 st_blk st_blk.s
224 ld_blk ld_blk.s
225 ldst_sync_ldd ldst_sync_ldd.s
226
227 saveld1 saveld1.s
228 ldst_sync_fc7 ldst_sync_fc7.s
229 ldst_sync_fc8 ldst_sync_fc8.s
230 ldst_sync_fc12 ldst_sync_fc12.s -vcs_run_args=+inval_rate=300
231 ldst_sync_fc14 ldst_sync_fc14.s -vcs_run_args=+inval_rate=400
232#endif
233 </runargs>
234</lsu_share>
235<lsu_asi name=lsu_asi>
236
237<runargs -vcs_run_args=-max_cycle=100000>
238 n2_lsu_asi_ring_01 n2_lsu_asi_ring_01.s -vcs_run_args=+thread=all
239 n2_lsu_asi_ring_02 n2_lsu_asi_ring_02.s -vcs_run_args=+thread=all
240 n2_lsu_asi_ring_03 n2_lsu_asi_ring_03.s -vcs_run_args=+thread=all
241
242</runargs>
243</lsu_asi>
244<lsu_ras name=lsu_ras>
245
246<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off -vcs_run_args=+noDebugModes>
247#ifdef SPC
248 err_dttp_diag err_dttp_diag.s -vcs_run_args=+thread=03
249 err_dtdp_diag err_dtdp_diag.s -vcs_run_args=+thread=03
250
251
252 err_sbdpu_diag_0 err_sbdpu_diag.s
253 err_sbdpu_diag_1 err_sbdpu_diag.s -vcs_run_args=+thread=02
254 err_sbdpu_diag_2 err_sbdpu_diag.s -vcs_run_args=+thread=04
255 err_sbdpu_diag_3 err_sbdpu_diag.s -vcs_run_args=+thread=08
256 err_sbdpu_diag_4 err_sbdpu_diag.s -vcs_run_args=+thread=10
257 err_sbdpu_diag_5 err_sbdpu_diag.s -vcs_run_args=+thread=20
258 err_sbdpu_diag_6 err_sbdpu_diag.s -vcs_run_args=+thread=40
259 err_sbdpu_diag_7 err_sbdpu_diag.s -vcs_run_args=+thread=80
260
261
262</runargs>
263
264
265<runargs -sas -vcs_run_args=+thread=all -midas_args=-DINC_ERR_TRAPS -vcs_run_args=+noDebugModes>
266#endif
267
268</runargs>
269</lsu_ras>
270
271<blimp name=blimp>
272
273<runargs -midas_args=-allow_tsb_conflicts>
274//---------------------------
275// 1 thread
276<runargs -vcs_run_args=+thread=01>
277 // #90279 tlu assertion
278 blimp_rand1_st_2865865 blimp_rand1_st_2865865.s
279 // #90867 - 8t diag fails ST
280 blimp_rand1_8t_3148963 blimp_rand1_8t_3148963.s
281</runargs>
282
283//---------------------------
284// 2 thread
285<runargs -vcs_run_args=+thread=11>
286 // #102229 TLU redirect with error injection
287 blimp_rand1_8t_11_7812675 blimp_rand1.knobs_7812675.s -tg_seed=1411795610 -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_ic_on -midas_args=-DINC_ERR_TRAPS
288</runargs>
289
290//---------------------------
291// 4 thread
292<runargs -vcs_run_args=+thread=0f>
293</runargs>
294
295
296//---------------------------
297// 8 thread
298<runargs -vcs_run_args=+thread=ff>
299 // #90696 PC miscmp on trap
300 blimp_rand1_8t_3033526 blimp_rand1_8t_3033526.s
301 // #93441
302 blimp_rand1_8t_4240359 blimp_rand1_8t_4240359.s
303 // #94081
304 blimp_rand1_8t_4527139 blimp_rand1_8t_4527139.s
305 // #94079
306 blimp_rand4_8t_4528891 blimp_rand4_8t_4528891.s
307 // #98363
308 blimp_rand5_8t_6471004 blimp_rand5_8t_6471004.s
309 // #100870 - 2 traps taken at once
310 blimp_rand3.knobs_7246351 blimp_rand3.knobs_7246351.s -vcs_run_args=+random_ccx_gnt -vcs_run_args=+min_ccx_gnt_delay=2 -vcs_run_args=+max_ccx_gnt_delay=10 -vcs_run_args=+TIMEOUT=10000 -max_cycle=+4000000 -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_irf_on -vcs_run_args=+err_irf_freq=45 -midas_args=-DINC_ERR_TRAPS -vcs_run_args=+thread=ff -tg_seed=1344387010
311</runargs>
312
313
314</runargs>
315</blimp>
316
317<tso_diags name=tso_diags>
318
319tso_n1_bcopy tso_n1_bcopy.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
320tso_n1_binit1 tso_n1_binit1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
321tso_n1_binit2 tso_n1_binit2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
322
323
324tso_n1_binit3 tso_n1_binit3.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
325tso_n1_cross_mod1 tso_n1_cross_mod1.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
326tso_n1_cross_mod101 tso_n1_cross_mod101.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
327tso_n1_cross_mod102 tso_n1_cross_mod102.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
328tso_n1_cross_mod103 tso_n1_cross_mod103.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
329tso_n1_cross_mod2 tso_n1_cross_mod2.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
330tso_n1_cross_mod201 tso_n1_cross_mod201.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
331tso_n1_cross_mod203 tso_n1_cross_mod203.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
332tso_n1_cross_mod3 tso_n1_cross_mod3.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+inst_check_off=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
333tso_n1_cross_mod4 tso_n1_cross_mod4.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
334tso_n1_cross_mod5 tso_n1_cross_mod5.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
335tso_n1_cross_mod6_bug6372 tso_n1_cross_mod6_bug6372.s -midas_args=-DTHREAD_COUNT=4 -finish_mask=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=f
336tso_n1_dekker1 tso_n1_dekker1.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
337tso_n1_dekker2 tso_n1_dekker2.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3
338tso_n1_dekker10 tso_n1_dekker10.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
339tso_n1_dekker11 tso_n1_dekker11.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
340tso_n1_false_sharing1 tso_n1_false_sharing1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
341tso_n1_false_sharing2 tso_n1_false_sharing2.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
342tso_n1_false_sharing_vershort tso_n1_false_sharing_vershort.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
343tso_n1_indirection1 tso_n1_indirection1.s -finish_mask=7 -midas_args=-DTHREAD_COUNT=3 -vcs_run_args=+show_delta -vcs_run_args=+thread=7 -nosas
344tso_n1_indirection2 tso_n1_indirection2.s -finish_mask=7 -midas_args=-DTHREAD_COUNT=3 -vcs_run_args=+show_delta -vcs_run_args=+thread=7 -nosas
345tso_n1_membar1 tso_n1_membar1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
346tso_n1_mutex1 tso_n1_mutex1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
347tso_n1_mutex2_ldstub tso_n1_mutex2_ldstub.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
348tso_n1_mutex3_cas tso_n1_mutex3_cas.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
349tso_n1_mutex4_casx tso_n1_mutex4_casx.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
350tso_n1_mutex5_swap_casx tso_n1_mutex5_swap_casx.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
351tso_n1_prod_cons1 tso_n1_prod_cons1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
352tso_n1_prod_cons2 tso_n1_prod_cons2.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
353tso_n1_prod_cons_variation1_1 tso_n1_prod_cons_variation1_1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
354tso_n1_prod_cons_variation2_1 tso_n1_prod_cons_variation2_1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
355tso_n1_self_mod1 tso_n1_self_mod1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
356tso_n1_self_mod2 tso_n1_self_mod2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
357tso_n1_self_mod3 tso_n1_self_mod3.s -midas_args=-DCMP_THREAD_START=0x11 -finish_mask=11 -vcs_run_args=+show_delta
358tso_n1_self_mod5 tso_n1_self_mod5.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
359tso_n1_self_mod6 tso_n1_self_mod6.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
360tso_n1_self_mod7 tso_n1_self_mod7.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
361tso_n1_self_mod8 tso_n1_self_mod8.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
362tso_n1_self_mod9 tso_n1_self_mod9.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
363tso_n1_self_mod10 tso_n1_self_mod10.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
364tso_n1_self_mod11 tso_n1_self_mod11.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
365tso_n1_self_mod101 tso_n1_self_mod101.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
366tso_n1_self_mod102 tso_n1_self_mod102.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
367tso_n1_self_mod103 tso_n1_self_mod103.s -finish_mask=11 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=11 -nosas
368tso_n1_self_mod104 tso_n1_self_mod104.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
369tso_n1_self_mod105 tso_n1_self_mod105.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
370
371tso_n1_self_mod106 tso_n1_self_mod106.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
372tso_n1_self_mod107 tso_n1_self_mod107.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
373tso_n1_self_mod108 tso_n1_self_mod108.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
374tso_n1_self_mod109 tso_n1_self_mod109.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
375tso_n1_self_mod110 tso_n1_self_mod110.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
376tso_n1_self_mod111 tso_n1_self_mod111.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
377tso_n1_self_mod201 tso_n1_self_mod201.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
378tso_n1_self_mod202 tso_n1_self_mod202.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
379tso_n1_self_mod203 tso_n1_self_mod203.s -finish_mask=11 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=11 -nosas
380tso_n1_self_mod206 tso_n1_self_mod206.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
381tso_n1_self_mod207 tso_n1_self_mod207.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
382tso_n1_starve0 tso_n1_starve0.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
383tso_n1_starve1 tso_n1_starve1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
384
385
386tso_n1_prod_cons1_pio tso_n1_prod_cons1_pio.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
387tso_n1_prod_cons2_pio tso_n1_prod_cons1_pio.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
388tso_n1_dekker1_pio tso_n1_dekker1_pio.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+thread=3
389tso_n1_dekker2_pio tso_n1_dekker2_pio.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+thread=3
390tso_n1_dekker7 tso_n1_dekker7.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
391tso_n1_dekker8 tso_n1_dekker8.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
392tso_n1_dekker9 tso_n1_dekker9.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
393tso_n1_peterson1 tso_n1_peterson1.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
394tso_n1_peterson2 tso_n1_peterson2.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
395tso_n1_peterson3 tso_n1_peterson3.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
396
397
398</tso_diags>
399
400
401// Really long running diags go here!
402
403<long_tso_diags name=long_tso_diags>
404
405tso_n1_ld_starve1 tso_n1_ld_starve1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
406tso_n1_ld_starve2 tso_n1_ld_starve2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
407
408</long_tso_diags>
409
410
411<runargs -vcs_run_args=+noredwdrkill>
412<tlu_long name=tlu_long>
413
414#if (! defined FC)
415<runargs -vcs_run_args=+thread=all>
416#endif
417
418#if (defined FC)
419<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
420#endif
421
422
423 tlu_rand01_ind_02 tlu_rand01_ind_02.s
424
425 tlu_rand02_ind_07 tlu_rand02_ind_07.s
426
427 tlu_rand02_ind_08 tlu_rand02_ind_08.s
428 tlu_rand02_ind_09 tlu_rand02_ind_09.s
429 tlu_rand02_ind_10 tlu_rand02_ind_10.s
430
431
432 tlu_rand03_ind_03 tlu_rand03_ind_03.s
433 tlu_rand03_ind_04 tlu_rand03_ind_04.s
434 tlu_rand03_ind_07 tlu_rand03_ind_07.s
435 tlu_rand03_ind_08 tlu_rand03_ind_08.s
436 tlu_rand03_ind_05 tlu_rand03_ind_05.s
437 tlu_rand03_ind_06 tlu_rand03_ind_06.s
438 tlu_rand03_ind_09 tlu_rand03_ind_09.s
439
440#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
441 tlu_rand04_ind_02 tlu_rand04_ind_02.s
442 tlu_rand04_ind_03 tlu_rand04_ind_03.s
443 tlu_rand04_ind_04 tlu_rand04_ind_04.s
444
445 tlu_rand04_ind_19 tlu_rand04_ind_19.s
446 tlu_rand04_ind_21 tlu_rand04_ind_21.s
447 tlu_rand04_ind_22 tlu_rand04_ind_22.s
448
449// TLU rand5 diags use user events
450#if (defined SPC)
451
452</runargs>
453
454<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off>
455 err_tcc_hstick_diag err_tcc_hstick_diag.s -vcs_run_args=+thread=01
456 err_tcc_hstick_diag_1 err_tcc_hstick_diag.s -vcs_run_args=+thread=02
457 err_tcc_hstick_diag_2 err_tcc_hstick_diag.s -vcs_run_args=+thread=04
458 err_tcc_hstick_diag_3 err_tcc_hstick_diag.s -vcs_run_args=+thread=08
459 err_tcc_hstick_diag_4 err_tcc_hstick_diag.s -vcs_run_args=+thread=10
460 err_tcc_hstick_diag_5 err_tcc_hstick_diag.s -vcs_run_args=+thread=20
461 err_tcc_hstick_diag_6 err_tcc_hstick_diag.s -vcs_run_args=+thread=40
462 err_tcc_hstick_diag_7 err_tcc_hstick_diag.s -vcs_run_args=+thread=80
463
464
465 err_inj_mondo_diag err_inj_mondo_diag.s -vcs_run_args=+thread=01
466 err_inj_mondo_diag_1 err_inj_mondo_diag.s -vcs_run_args=+thread=02
467 err_inj_mondo_diag_2 err_inj_mondo_diag.s -vcs_run_args=+thread=04
468 err_inj_mondo_diag_3 err_inj_mondo_diag.s -vcs_run_args=+thread=08
469 err_inj_mondo_diag_4 err_inj_mondo_diag.s -vcs_run_args=+thread=10
470 err_inj_mondo_diag_5 err_inj_mondo_diag.s -vcs_run_args=+thread=20
471 err_inj_mondo_diag_6 err_inj_mondo_diag.s -vcs_run_args=+thread=40
472 err_inj_mondo_diag_7 err_inj_mondo_diag.s -vcs_run_args=+thread=80
473
474 err_tsa_diag err_tsa_diag.s -vcs_run_args=+thread=01
475 err_tsa_diag_1 err_tsa_diag.s -vcs_run_args=+thread=02
476 err_tsa_diag_2 err_tsa_diag.s -vcs_run_args=+thread=04
477 err_tsa_diag_3 err_tsa_diag.s -vcs_run_args=+thread=08
478 err_tsa_diag_4 err_tsa_diag.s -vcs_run_args=+thread=10
479 err_tsa_diag_5 err_tsa_diag.s -vcs_run_args=+thread=20
480 err_tsa_diag_6 err_tsa_diag.s -vcs_run_args=+thread=40
481 err_tsa_diag_7 err_tsa_diag.s -vcs_run_args=+thread=80
482
483
484 err_stick_cmpr_cycle err_stick_cmpr_cycle.s -vcs_run_args=+thread=01
485 err_stick_cmpr_cycle_1 err_stick_cmpr_cycle.s -vcs_run_args=+thread=02
486 err_stick_cmpr_cycle_2 err_stick_cmpr_cycle.s -vcs_run_args=+thread=04
487 err_stick_cmpr_cycle_3 err_stick_cmpr_cycle.s -vcs_run_args=+thread=08
488 err_stick_cmpr_cycle_4 err_stick_cmpr_cycle.s -vcs_run_args=+thread=10
489 err_stick_cmpr_cycle_5 err_stick_cmpr_cycle.s -vcs_run_args=+thread=20
490 err_stick_cmpr_cycle_6 err_stick_cmpr_cycle.s -vcs_run_args=+thread=40
491 err_stick_cmpr_cycle_7 err_stick_cmpr_cycle.s -vcs_run_args=+thread=80
492
493
494 err_tick_cmpr_cycle_c1_n2 err_tick_cmpr_cycle_c1_n2.s -vcs_run_args=+thread=01
495
496
497</runargs>
498
499
500#if (! defined FC)
501<runargs -vcs_run_args=+thread=all>
502#endif
503
504#if (defined FC)
505<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
506#endif
507
508#endif
509
510 tlu_rand05_ind_10_11_8 tlu_rand05_ind_10_11_8.s
511 tlu_swtraps tlu_swtraps.pal
512#endif
513</runargs>
514</tlu_long>
515<tlu_fast name=tlu_fast>
516
517#if (! defined FC)
518<runargs -vcs_run_args=+thread=all>
519#endif
520
521#if (defined FC)
522<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
523#endif
524
525 tlu_allintvec1 tlu_allintvec1.s
526 tlu_allintvec2 tlu_allintvec2.s
527
528 tlu_simulint tlu_simulint.s -vcs_run_args=+err_chkrs_off
529#if (defined SPC)
530
531 tlu_rand01_ind_01 tlu_rand01_ind_01.s
532 tlu_rand01_ind_04 tlu_rand01_ind_04.s
533
534 tlu_rand02_ind_03 tlu_rand02_ind_03.s
535 tlu_rand02_ind_05 tlu_rand02_ind_05.s
536
537#endif
538
539 tlu_rand04_ind_01 tlu_rand04_ind_01.s
540 tlu_rand05_ind_01_13_1 tlu_rand05_ind_01_13_1.s
541 tlu_rand05_ind_39 tlu_rand05_ind_39.s
542 tlu_rand01_ind_09 tlu_rand01_ind_09.s
543
544
545</runargs>
546
547// SingleThread ONLY
548
549
550 tlu_rand01_ind_11 tlu_rand01_ind_11.s
551
552 tlu_rand02_ind_02 tlu_rand02_ind_02.s
553
554 tlu_rand03_ind_02 tlu_rand03_ind_02.s
555 tlu_rand04_ind_02 tlu_rand04_ind_02.s
556
557 tlu_rand04_ind_14 tlu_rand04_ind_14.s
558 tlu_rand04_ind_15 tlu_rand04_ind_15.s
559 tlu_rand04_ind_21 tlu_rand04_ind_21.s
560
561 tlu_rand03_ind_05 tlu_rand03_ind_05.s
562 tlu_rand03_ind_06 tlu_rand03_ind_06.s
563 tlu_rand03_ind_09 tlu_rand03_ind_09.s
564 tlu_rand04_ind_03 tlu_rand04_ind_03.s
565 tlu_rand04_ind_04 tlu_rand04_ind_04.s
566 tlu_rand04_ind_06 tlu_rand04_ind_06.s
567 tlu_rand04_ind_07 tlu_rand04_ind_07.s
568 tlu_rand04_ind_16 tlu_rand04_ind_16.s
569 tlu_rand04_ind_19 tlu_rand04_ind_19.s
570 tlu_rand04_ind_20 tlu_rand04_ind_20.s
571 tlu_rand04_ind_22 tlu_rand04_ind_22.s
572 tlu_rand04_ind_08 tlu_rand04_ind_08.s
573
574 tlu_rand04_ind_11 tlu_rand04_ind_11.s -midas_args=-DCMP_THREAD_START=0xe7 -finish_mask=e7
575
576
577 tlu_107450 tlu_107450.s
578 tlu_107450_mt tlu_107450_mt.s
579</tlu_fast>
580
581<tlu_disrupting name=tlu_disrupting>
582
583 tlu_rand05_ind_08 tlu_rand05_ind_08.s
584 tlu_rand05_ind_10 tlu_rand05_ind_10.s
585 tlu_rand05_ind_11 tlu_rand05_ind_11.s
586 tlu_rand05_ind_12 tlu_rand05_ind_12.s
587 tlu_rand05_ind_15 tlu_rand05_ind_15.s
588 tlu_rand05_ind_16 tlu_rand05_ind_16.s
589
590
591 tlu_rand05_ind_01 tlu_rand05_ind_01.s
592 tlu_rand05_ind_02 tlu_rand05_ind_02.s
593 tlu_rand05_ind_03 tlu_rand05_ind_03.s
594 tlu_rand05_ind_04 tlu_rand05_ind_04.s
595 tlu_rand05_ind_06 tlu_rand05_ind_06.s
596 tlu_rand05_ind_07 tlu_rand05_ind_07.s
597
598 tlu_rand05_ind_01_mt tlu_rand05_ind_01.s -vcs_run_args=+thread=all
599
600 // tlu_rand05_ind_23 tlu_rand05_ind_23.s -vcs_run_args=+thread=ff
601
602 isa3_1215ivtrap2 isa3_1215ivtrap2.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
603
604
605 isa3_1215ivtrap isa3_1215ivtrap.s -vcs_run_args=+thread=all
606 isa3_intlevel_121503 isa3_intlevel_121503.s -vcs_run_args=+thread=all
607 isa3_mondo_121503 isa3_mondo_121503.s -vcs_run_args=+thread=all
608
609
610 isa3_1215hsysmatrap isa3_1215hsysmatrap.s -vcs_run_args=+thread=all
611 isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -vcs_run_args=+thread=1
612 isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -vcs_run_args=+thread=ff
613
614</tlu_disrupting>
615
616
617<tlu_halt name=tlu_halt>
618
619 err_dcdp_halt err_dcdp_halt_diag.s -vcs_run_args=+err_chkrs_off -nosas -midas_args=-DNOERRCHK
620 err_tcc_hstick_halt err_tcc_hstick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
621 err_tcc_stick_halt err_tcc_stick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
622 err_tcc_tick_halt err_tcc_tick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
623 tlu_halt_hstmatch tlu_halt_hstmatch.s -vcs_run_args=+thread=all
624 tlu_halt_intvec tlu_halt_intvec.s -vcs_run_args=+thread=all
625// tlu_halt_modint tlu_halt_modint.s -vcs_run_args=+thread=all
626// tlu_halt_cwqint tlu_halt_cwqint.s -vcs_run_args=+thread=all
627 tlu_halt_park tlu_halt_park.s -vcs_run_args=+thread=all
628 tlu_halt_stickint tlu_halt_stickint.s -vcs_run_args=+thread=all
629 tlu_halt_tickint tlu_halt_tickint.s -vcs_run_args=+thread=all
630 tlu_halt_xir tlu_halt_xir.s -vcs_run_args=+thread=all
631</tlu_halt>
632
633</runargs>
634
635<mmu_core name=mmu_core>
636
637
638#if (!defined FC)
639<runargs -sas -vcs_run_args=+thread=01>
640#endif
641
642#if (defined FC)
643<runargs -sas -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=1 >
644#endif
645
646 mmu_st_unsupport_psize mmu_st_unsupport_psize.s
647 mmu_st_h2p mmu_st_h2p.s
648#ifdef SPC
649 mmu_st_tsb_va_hole mmu_st_tsb_va_hole.s -midas_args=-DCUSTOM_TRAP_0X9
650 mmu_st_tsb_va_hole_1 mmu_st_tsb_va_hole_1.s -midas_args=-DCUSTOM_TRAP_0X9
651#endif
652 mmu_st_ext_ra mmu_st_ext_ra.s
653 mmu_use_bit_test mmu_tag_read_use_bit_test.s
654 mmu_st_hwtw_enable mmu_st_hwtw_enable.s
655</runargs>
656
657#if (!defined FC)
658<runargs -sas -vcs_run_args=+thread=all>
659#endif
660
661#if (defined FC)
662<runargs -sas -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
663#endif
664
665 mmu_mt_ranotpa_0 mmu_mt_ranotpa_0.s
666 mmu_mt_no_hboot_hwtw_0 mmu_mt_no_hboot_hwtw_0.s
667 mmu_mt_no_hboot_hwtw_0a mmu_mt_no_hboot_hwtw_0.s -midas_args=-DNOHWTW
668 mmu_mt_ep_0 mmu_mt_ep_0.s
669 mmu_mt_psize_1 mmu_mt_psize_1.s
670 mmu_mt_realrange_0 mmu_mt_realrange_0.s
671 mmu_mt_realrange_1 mmu_mt_realrange_1.s
672 mmu_mt_hwtw_demap mmu_mt_hwtw_demap.s
673 mmu_mt_tsb_ptr_0 mmu_mt_tsb_ptr_0.s
674 mmu_mt_tsb_ptr_1 mmu_mt_tsb_ptr_1.s
675#if (!defined FC)
676 mmu_mt_htba mmu_mt_htba.s -vcs_run_args=+thread=ff
677#endif
678#if (defined FC)
679 mmu_mt_htba mmu_mt_htba.s -midas_args=-DCMP_THREAD_START=ff -finish_mask=all
680#endif
681 mmu_mt_real_0 mmu_mt_real_0.s
682 mmu_mt_real_1 mmu_mt_real_1.s
683 mmu_mt_bypass_use_ctx_0 mmu_mt_bypass_use_ctx_0.s
684 mmu_mt_write_tsb_0 mmu_mt_write_tsb_0.s
685 mmu_mt_rr_0 mmu_mt_rr_0.s
686 mmu_mt_demap_page mmu_mt_demap_page.s
687 mmu_mt_demap_page_1 mmu_mt_demap_page_1.s
688
689</runargs>
690
691#ifdef SPC
692
693<runargs -sas -vcs_run_args=+thread=07 -vcs_run_args=+err_chkrs_off>
694 mmu_mt_mhit_0 mmu_mt_mhit_0.s -vcs_run_args=+err_sync_on
695</runargs>
696
697<runargs -sas -vcs_run_args=+thread=13>
698 mmu_mt_mhit_1 mmu_mt_mhit_1.s -vcs_run_args=+err_sync_on
699</runargs>
700
701<runargs -sas -vcs_run_args=+thread=21 -vcs_run_args=+err_chkrs_off>
702 mmu_st_mhit_2 mmu_st_mhit_2.s -vcs_run_args=+err_sync_on
703</runargs>
704
705#endif
706
707#if (!defined FC)
708<runargs -sas -vcs_run_args=+thread=03>
709#endif
710#if (defined FC)
711<runargs -sas -midas_args=-DCMP_THREAD_START=0x03 -finish_mask=3 >
712#endif
713
714 mmu_mt_use_ctx0 mmu_mt_use_ctx0.s
715 mmu_mt_use_ctx1 mmu_mt_use_ctx1.s
716 mmu_mt_rtrans_0 mmu_mt_rtrans_0.s
717
718</runargs>
719
720#if (!defined FC)
721<runargs -sas -vcs_run_args=+thread=1f>
722#endif
723#if (defined FC)
724<runargs -sas -midas_args=-DCMP_THREAD_START=0x1f -finish_mask=1f >
725#endif
726
727 mmu_mt_asi_cp mmu_mt_asi_cp.s
728
729</runargs>
730
731
732#if (!defined FC)
733<runargs -sas -vcs_run_args=+thread=01 -midas_args=-DTSB_SEARCH_BURST>
734#endif
735#if (defined FC)
736<runargs -sas -midas_args=-DCMP_THREAD_START=0x01 -midas_args=-DTSB_SEARCH_BURST -finish_mask=1 >
737#endif
738
739 mmu_st_unsupport_psize_burst mmu_st_unsupport_psize.s
740 mmu_st_h2p_burst mmu_st_h2p.s
741#ifdef SPC
742 mmu_st_tsb_va_hole_burst mmu_st_tsb_va_hole.s -midas_args=-DCUSTOM_TRAP_0X9
743 mmu_st_tsb_va_hole_1_burst mmu_st_tsb_va_hole_1.s -midas_args=-DCUSTOM_TRAP_0X9
744 mmu_st_ext_ra_burst mmu_st_ext_ra.s
745#endif
746
747</runargs>
748
749#if (!defined FC)
750<runargs -sas -vcs_run_args=+thread=all -midas_args=-DTSB_SEARCH_BURST>
751#endif
752#if (defined FC)
753<runargs -sas -midas_args=-DCMP_THREAD_START=all -midas_args=-DTSB_SEARCH_BURST -finish_mask=all >
754#endif
755
756 mmu_mt_ranotpa_0_burst mmu_mt_ranotpa_0.s
757 mmu_mt_no_hboot_hwtw_0_burst mmu_mt_no_hboot_hwtw_0.s
758 mmu_mt_no_hboot_hwtw_0a_burst mmu_mt_no_hboot_hwtw_0.s -midas_args=-DNOHWTW
759 mmu_mt_ep_0_burst mmu_mt_ep_0.s
760 mmu_mt_psize_1_burst mmu_mt_psize_1.s
761 mmu_mt_realrange_0_burst mmu_mt_realrange_0.s
762 mmu_mt_realrange_1_burst mmu_mt_realrange_1.s
763 mmu_mt_hwtw_demap_burst mmu_mt_hwtw_demap.s
764 mmu_mt_tsb_ptr_0_burst mmu_mt_tsb_ptr_0.s
765 mmu_mt_tsb_ptr_1_burst mmu_mt_tsb_ptr_1.s
766
767#if (!defined FC)
768 mmu_mt_htba_burst mmu_mt_htba.s -vcs_run_args=+thread=ff
769#endif
770#if (defined FC)
771 mmu_mt_htba_burst mmu_mt_htba.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
772#endif
773
774 mmu_mt_real_0_burst mmu_mt_real_0.s
775 mmu_mt_real_1_burst mmu_mt_real_1.s
776 mmu_mt_bypass_use_ctx_0_burst mmu_mt_bypass_use_ctx_0.s
777 mmu_mt_write_tsb_0_burst mmu_mt_write_tsb_0.s
778 mmu_mt_rr_0_burst mmu_mt_rr_0.s
779 mmu_mt_demap_page_burst mmu_mt_demap_page.s
780 mmu_mt_demap_page_1_burst mmu_mt_demap_page_1.s
781
782</runargs>
783
784#ifdef SPC
785
786<runargs -sas -vcs_run_args=+thread=07 -midas_args=-DTSB_SEARCH_BURST -vcs_run_args=+err_chkrs_off>
787 mmu_mt_mhit_0_burst mmu_mt_mhit_0.s -vcs_run_args=+err_sync_on
788</runargs>
789
790#if (!defined FC)
791<runargs -sas -vcs_run_args=+thread=13 -midas_args=-DTSB_SEARCH_BURST>
792#endif
793#if (defined FC)
794<runargs -sas -midas_args=-DCMP_THREAD_START=0x13 -midas_args=-DTSB_SEARCH_BURST -finish_mask=13 >
795#endif
796 mmu_mt_mhit_1_burst mmu_mt_mhit_1.s -vcs_run_args=+err_sync_on
797</runargs>
798
799#endif
800
801#if (!defined FC)
802<runargs -sas -vcs_run_args=+thread=03 -midas_args=-DTSB_SEARCH_BURST>
803#endif
804#if (defined FC)
805<runargs -sas -midas_args=-DCMP_THREAD_START=0x03 -midas_args=-DTSB_SEARCH_BURST -finish_mask=3 >
806#endif
807
808 mmu_mt_use_ctx0_burst mmu_mt_use_ctx0.s
809 mmu_mt_use_ctx1_burst mmu_mt_use_ctx1.s
810 mmu_mt_rtrans_0_burst mmu_mt_rtrans_0.s
811
812</runargs>
813
814#if (!defined FC)
815<runargs -sas -vcs_run_args=+thread=1f -midas_args=-DTSB_SEARCH_BURST>
816#endif
817#if (defined FC)
818<runargs -sas -midas_args=-DCMP_THREAD_START=0x1f -midas_args=-DTSB_SEARCH_BURST -finish_mask=1f >
819#endif
820
821 mmu_mt_asi_cp_burst mmu_mt_asi_cp.s
822
823</runargs>
824
825
826#if (!defined FC)
827<runargs -sas -vcs_run_args=+thread=01 -midas_args=-DTSB_SEARCH_PREDICTION>
828#endif
829#if (defined FC)
830<runargs -sas -midas_args=-DCMP_THREAD_START=0x01 -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=1 >
831#endif
832
833 mmu_st_unsupport_psize_prediction mmu_st_unsupport_psize.s
834 mmu_st_h2p_prediction mmu_st_h2p.s
835#ifdef SPC
836 mmu_st_tsb_va_hole_prediction mmu_st_tsb_va_hole.s -midas_args=-DCUSTOM_TRAP_0X9
837 mmu_st_tsb_va_hole_1_prediction mmu_st_tsb_va_hole_1.s -midas_args=-DCUSTOM_TRAP_0X9
838 mmu_st_ext_ra_prediction mmu_st_ext_ra.s
839#endif
840
841</runargs>
842
843#if (!defined FC)
844<runargs -sas -vcs_run_args=+thread=all -midas_args=-DTSB_SEARCH_PREDICTION>
845#endif
846#if (defined FC)
847<runargs -sas -midas_args=-DCMP_THREAD_START=all -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=all >
848#endif
849
850 mmu_mt_ranotpa_0_prediction mmu_mt_ranotpa_0.s
851 mmu_mt_no_hboot_hwtw_0_prediction mmu_mt_no_hboot_hwtw_0.s
852 mmu_mt_no_hboot_hwtw_0a_prediction mmu_mt_no_hboot_hwtw_0.s -midas_args=-DNOHWTW
853 mmu_mt_ep_0_prediction mmu_mt_ep_0.s
854 mmu_mt_psize_1_prediction mmu_mt_psize_1.s
855 mmu_mt_realrange_0_prediction mmu_mt_realrange_0.s
856 mmu_mt_realrange_1_prediction mmu_mt_realrange_1.s
857 mmu_mt_hwtw_demap_prediction mmu_mt_hwtw_demap.s
858 mmu_mt_tsb_ptr_0_prediction mmu_mt_tsb_ptr_0.s
859 mmu_mt_tsb_ptr_1_prediction mmu_mt_tsb_ptr_1.s
860#if (!defined FC)
861 mmu_mt_htba_prediction mmu_mt_htba.s -vcs_run_args=+thread=ff
862#endif
863#if (defined FC)
864 mmu_mt_htba_prediction mmu_mt_htba.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
865#endif
866 mmu_mt_real_0_prediction mmu_mt_real_0.s
867// mmu_mt_real_1_prediction mmu_mt_real_1.s
868 mmu_mt_bypass_use_ctx_0_prediction mmu_mt_bypass_use_ctx_0.s
869 mmu_mt_write_tsb_0_prediction mmu_mt_write_tsb_0.s
870 mmu_mt_rr_0_prediction mmu_mt_rr_0.s
871 mmu_mt_demap_page_prediction mmu_mt_demap_page.s
872 mmu_mt_demap_page_1_prediction mmu_mt_demap_page_1.s
873
874</runargs>
875
876#ifdef SPC
877
878#if (!defined FC)
879<runargs -sas -vcs_run_args=+thread=07 -midas_args=-DTSB_SEARCH_PREDICTION -vcs_run_args=+err_chkrs_off>
880#endif
881#if (defined FC)
882<runargs -sas -midas_args=-DCMP_THREAD_START=0x07 -midas_args=-DTSB_SEARCH_PREDICTION -vcs_run_args=+err_chkrs_off -finish_mask=7 >
883#endif
884
885 mmu_mt_mhit_0_prediction mmu_mt_mhit_0.s -vcs_run_args=+err_sync_on
886</runargs>
887
888#if (!defined FC)
889<runargs -sas -vcs_run_args=+thread=13 -midas_args=-DTSB_SEARCH_PREDICTION>
890#endif
891#if (defined FC)
892<runargs -sas -midas_args=-DCMP_THREAD_START=0x13 -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=13 >
893#endif
894
895 mmu_mt_mhit_1_prediction mmu_mt_mhit_1.s -vcs_run_args=+err_sync_on
896</runargs>
897
898#endif
899
900#if (!defined FC)
901<runargs -sas -vcs_run_args=+thread=03 -midas_args=-DTSB_SEARCH_PREDICTION>
902#endif
903#if (defined FC)
904<runargs -sas -midas_args=-DCMP_THREAD_START=0x03 -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=3 >
905#endif
906
907 mmu_mt_use_ctx0_prediction mmu_mt_use_ctx0.s
908 mmu_mt_use_ctx1_prediction mmu_mt_use_ctx1.s
909 mmu_mt_rtrans_0_prediction mmu_mt_rtrans_0.s
910
911</runargs>
912
913#if (!defined FC)
914<runargs -sas -vcs_run_args=+thread=1f -midas_args=-DTSB_SEARCH_PREDICTION>
915#endif
916#if (defined FC)
917<runargs -sas -midas_args=-DCMP_THREAD_START=0x1f -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=1f >
918#endif
919
920 mmu_mt_asi_cp_prediction mmu_mt_asi_cp.s
921
922</runargs>
923
924#ifdef SPC
925
926<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off>
927 err_sca_diag err_sca_diag.s
928 err_scau_diag err_scau_diag.s
929 err_mra_diag err_mra_diag.s
930</runargs>
931
932#endif
933
934
935#if (!defined FC)
936<runargs -sas -vcs_run_args=+thread=all -midas_args=-DTSB_SEARCH_PREDICTION>
937#endif
938#if (defined FC)
939<runargs -sas -midas_args=-DCMP_THREAD_START=all -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=all >
940#endif
941
942 mmu_mt_real_1_prediction mmu_mt_real_1.s
943</runargs>
944</mmu_core>
945
946<mmu_tlb_sync name=mmu_tlb_sync>
947 mmu_tag_read_use_bit_test mmu_tag_read_use_bit_test.s
948</mmu_tlb_sync>
949<mmu_cmp_test name=mmu_cmp_test>
950
951
952#if (!defined FC)
953<runargs -midas_args=-DMMU247 -vcs_run_args=+thread=all -midas_args=-DENABLE_ITTM_DTTM -midas_args=-DPORTABLE_CORE>
954#endif
955#if (defined FC)
956<runargs -midas_args=-DMMU247 -midas_args=-DCMP_THREAD_START=all -midas_args=-DENABLE_ITTM_DTTM -midas_args=-DPORTABLE_CORE -finish_mask=all >
957#endif
958
959// mmu_cmp_test_0 mmu_cmp_test_0.s
960// mmu_cmp_test_1 mmu_cmp_test_1.s
961 mmu_cmp_test_2 mmu_cmp_test_2.s
962 mmu_cmp_test_3 mmu_cmp_test_3.s
963// mmu_cmp_test_4 mmu_cmp_test_4.s
964</runargs>
965</mmu_cmp_test>
966
967<kaos_st name=kaos_st>
968
969<runargs -midas_args=-allow_tsb_conflicts>
970 kaos_01_07_2004_1 kaos_01_07_2004_1.s
971 kaos_02_03_04_18 kaos_02_03_04_18.s
972 kaos_02_05_2004_20 kaos_02_05_2004_20.s
973 kaos_02_05_2004_91 kaos_02_05_2004_91.s
974 kaos_02_06_2004_11 kaos_02_06_2004_11.s
975 kaos_02_06_2004_135 kaos_02_06_2004_135.s
976 kaos_02_06_2004_152 kaos_02_06_2004_152.s
977 kaos_02_06_2004_71 kaos_02_06_2004_71.s
978 kaos_27_1_2004_0_11 kaos_27_1_2004_0_11.s
979 kaos_27_1_2004_0_13 kaos_27_1_2004_0_13.s
980 kaos_27_1_2004_0_22 kaos_27_1_2004_0_22.s
981 kaos_27_1_2004_0_42 kaos_27_1_2004_0_42.s
982 kaos_27_1_2004_0_49 kaos_27_1_2004_0_49.s
983 v9_kao_02_10_04_19 v9_kao_02_10_04_19.s
984 v9_kao_02_11_04_31 v9_kao_02_11_04_31.s
985 v9_kao_02_14_04_101 v9_kao_02_14_04_101.s
986 v9_kao_02_14_04_103 v9_kao_02_14_04_103.s
987 v9_kao_02_14_04_112 v9_kao_02_14_04_112.s
988 ifu_kao_02_18_04_109 ifu_kao_02_18_04_109.s
989
990</runargs>
991</kaos_st>
992<kaos_2t name=kaos_2t>
993<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=03 -midas_args=-DNOHWTW>
994 kaos_01_06_2004_1 kaos_01_06_2004_1.s
995 //v9_2th_kao_02_20_04_88 v9_2th_kao_02_20_04_88.s
996 v9_2th_kao_02_20_04_125 v9_2th_kao_02_20_04_125.s
997 v9_2th_kao_02_20_04_131 v9_2th_kao_02_20_04_131.s
998 v9_2th_kao_02_20_04_219 v9_2th_kao_02_20_04_219.s
999 v9_2th_kao_02_20_04_434 v9_2th_kao_02_20_04_434.s
1000 v9_2th_kao_02_20_04_71 v9_2th_kao_02_20_04_71.s
1001
1002</runargs>
1003</kaos_2t>
1004
1005<kaos_4t name=kaos_4t>
1006<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=0f -midas_args=-DNOHWTW>
1007 v9_4th_kao_02_25_04_4 v9_4th_kao_02_25_04_4.s
1008 //v9_kao_4th_02_23_04_0 v9_kao_4th_02_23_04_0.s
1009 v9_kao_4th_02_27_04_2 v9_kao_4th_02_27_04_2.s
1010 v9_kao_4th_02_27_04_199 v9_kao_4th_02_27_04_199.s
1011 v9_kao_4th_02_27_04_34 v9_kao_4th_02_27_04_34.s
1012 v9_kao_4th_03_04_04_100 v9_kao_4th_03_04_04_100.s
1013 v9_kao_4th_02_27_04_199 v9_kao_4th_02_27_04_199.s
1014 v9_4th_kaos_03_05_04_500 v9_4th_kaos_03_05_04_500.s
1015 v9_4th_kaos_03_05_04_105 v9_4th_kaos_03_05_04_105.s
1016 v9_4th_kaos_03_05_04_130 v9_4th_kaos_03_05_04_130.s
1017 v9_4th_kaos_03_05_04_101 v9_4th_kaos_03_05_04_101.s
1018 v9_4th_kaos_03_05_04_153 v9_4th_kaos_03_05_04_153.s
1019 v9_4th_kaos_03_05_04_501 v9_4th_kaos_03_05_04_501.s
1020
1021</runargs>
1022</kaos_4t>
1023
1024
1025<kaos_8t name=kaos_8t>
1026<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=all>
1027
1028 v9_8th_sp_kaos_03_11_04_0 v9_8th_sp_kaos_03_11_04_0.s
1029 v9_8th_sp_kaos_03_11_04_15 v9_8th_sp_kaos_03_11_04_15.s
1030 v9_8th_kaos_03_16_04_0 v9_8th_kaos_03_16_04_0.s
1031 ifu_8th_sp_kaos_03_10_04_1 ifu_8th_sp_kaos_03_10_04_1.s
1032 v9_8th_kaos_02_08_04_20 v9_8th_kaos_02_08_04_20.s
1033 v9_8th_sp_kaos_03_11_04_17 v9_8th_sp_kaos_03_11_04_17.s
1034 v9_8th_kaos_03_17_04_133 v9_8th_kaos_03_17_04_133.s
1035 v9_8th_kaos_03_17_04_0 v9_8th_kaos_03_17_04_0.s
1036 v9_8th_kaos_03_23_04_14 v9_8th_kaos_03_23_04_14.s
1037 v9_8th_kaos_03_17_04_10 v9_8th_kaos_03_17_04_10.s
1038 v9_8th_kaos_02_08_04_20 v9_8th_kaos_02_08_04_20.s
1039 v9_8th_kaos_03_14_04_396 v9_8th_kaos_03_14_04_396.s
1040 isa_8th_kaos_03_30_04_101 isa_8th_kaos_03_30_04_101.s
1041
1042 v9_8th_kaos_03_01_04_102 v9_8th_kaos_03_01_04_102.s
1043 v9_8th_kao_03_01_04_0 v9_8th_kao_03_01_04_0.s
1044 v9_8th_kaos_02_08_04_0 v9_8th_kaos_02_08_04_0.s
1045</runargs>
1046</kaos_8t>
1047
1048
1049<kaos_tlb name=kaos_tlb>
1050
1051<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=all>
1052
1053 // These diags require TLB Sync
1054 // Add these back into kaos_8t once CMP has TLB Sync
1055 v9_8th_kaos_03_01_04_102 v9_8th_kaos_03_01_04_102.s
1056 v9_8th_kao_03_01_04_0 v9_8th_kao_03_01_04_0.s
1057 v9_8th_kaos_02_08_04_0 v9_8th_kaos_02_08_04_0.s
1058
1059</runargs>
1060</kaos_tlb>
1061
1062
1063<isa2_mt name=isa2_mt>
1064#if (!defined FC)
1065<runargs -vcs_run_args=+thread=all>
1066#endif
1067#if (defined FC)
1068<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
1069#endif
1070isa2_raw_fc_2 isa2_raw_fc_2.s
1071isa2_all_fail_fc_3 isa2_all_fail_fc_3.s
1072spc_isa2mt_fail_fc_9 spc_isa2mt_fail_fc_9.s
1073spc_isa2mt_fail_fc_7 spc_isa2mt_fail_fc_7.s
1074spc_isa2mt_fail_fc_11 spc_isa2mt_fail_fc_11.s
1075
1076isa2_basic_fc0 isa2_basic_fc0.s
1077isa2_basic_fc1 isa2_basic_fc1.s
1078isa2_basic_fc2 isa2_basic_fc2.s
1079isa2_basic_fc3 isa2_basic_fc3.s
1080isa2_basic_fc4 isa2_basic_fc4.s
1081isa2_basic_fc5 isa2_basic_fc5.s
1082isa2_basic_fc6 isa2_basic_fc6.s
1083isa2_basic_fc7 isa2_basic_fc7.s
1084isa2_basic_fc8 isa2_basic_fc8.s
1085isa2_basic_fc9 isa2_basic_fc9.s
1086isa2_basic_fc10 isa2_basic_fc10.s
1087isa2_basic_fc11 isa2_basic_fc11.s
1088isa2_basic_fc12 isa2_basic_fc12.s
1089isa2_basic_fc13 isa2_basic_fc13.s
1090isa2_basic_fc14 isa2_basic_fc14.s
1091isa2_basic_fc15 isa2_basic_fc15.s
1092isa2_basic_fc16 isa2_basic_fc16.s
1093isa2_basic_fc17 isa2_basic_fc17.s
1094isa2_basic_fc18 isa2_basic_fc18.s
1095isa2_basic_fc19 isa2_basic_fc19.s
1096isa2_basic_fc20 isa2_basic_fc20.s
1097isa2_basic_fc21 isa2_basic_fc21.s
1098isa2_basic_fc22 isa2_basic_fc22.s
1099isa2_basic_fc23 isa2_basic_fc23.s
1100isa2_basic_fc24 isa2_basic_fc24.s
1101isa2_basic_fc25 isa2_basic_fc25.s
1102isa2_basic_fc26 isa2_basic_fc26.s
1103isa2_basic_fc27 isa2_basic_fc27.s
1104isa2_basic_fc28 isa2_basic_fc28.s
1105isa2_basic_fc29 isa2_basic_fc29.s
1106
1107</runargs>
1108</isa2_mt>
1109<isa3_saverestore name=isa3_saverestore>
1110
1111 isa3_saverestore_fc0 isa3_saverestore_fc0.s
1112 isa3_saverestore_fc1 isa3_saverestore_fc1.s
1113 isa3_saverestore_fc2 isa3_saverestore_fc2.s
1114 isa3_saverestore_fc3 isa3_saverestore_fc3.s
1115 isa3_saverestore_fc4 isa3_saverestore_fc4.s
1116</isa3_saverestore>
1117
1118<isa3_mt name=isa3_mt>
1119
1120#if (!defined FC)
1121<runargs -vcs_run_args=+thread=all>
1122#endif
1123#if (defined FC)
1124<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
1125#endif
1126
1127 isa3_basic3_f0 isa3_basic3_f0.s
1128 isa3_basic3_f1 isa3_basic3_f1.s
1129 isa3_basic3_f2 isa3_basic3_f2.s
1130 isa3_basic3_f3 isa3_basic3_f3.s
1131 isa3_basic3_f5 isa3_basic3_f5.s
1132 isa3_basic3_f6 isa3_basic3_f6.s
1133 isa3_basic3_f7 isa3_basic3_f7.s
1134 isa3_basic3_f8 isa3_basic3_f8.s
1135 isa3_basic3_f10 isa3_basic3_f10.s
1136 isa3_basic3_f11 isa3_basic3_f11.s
1137 isa3_basic3_f12 isa3_basic3_f12.s
1138 isa3_basic3_f13 isa3_basic3_f13.s
1139 isa3_basic3_f14 isa3_basic3_f14.s
1140 isa3_basic3_f15 isa3_basic3_f15.s
1141 isa3_basic3_f16 isa3_basic3_f16.s
1142 isa3_basic3_f17 isa3_basic3_f17.s
1143 isa3_basic3_f18 isa3_basic3_f18.s
1144 isa3_basic3_f19 isa3_basic3_f19.s
1145 isa3_window3_f0 isa3_window3_f0.s
1146 isa3_window3_f1 isa3_window3_f1.s
1147 isa3_window3_f2 isa3_window3_f2.s
1148 isa3_window3_f3 isa3_window3_f3.s
1149 isa3_window3_f4 isa3_window3_f4.s
1150 isa3_window3_f5 isa3_window3_f5.s
1151 isa3_window3_f6 isa3_window3_f6.s
1152 isa3_window3_f7 isa3_window3_f7.s
1153 isa3_window3_f8 isa3_window3_f8.s
1154 isa3_window3_f9 isa3_window3_f9.s
1155 isa3_window3_f10 isa3_window3_f10.s
1156 isa3_window3_f11 isa3_window3_f11.s
1157 isa3_window3_f12 isa3_window3_f12.s
1158 isa3_window3_f13 isa3_window3_f13.s
1159 isa3_window3_f14 isa3_window3_f14.s
1160 isa3_window3_f15 isa3_window3_f15.s
1161 isa3_window3_f16 isa3_window3_f16.s
1162 isa3_window3_f17 isa3_window3_f17.s
1163 isa3_window3_f18 isa3_window3_f18.s
1164 isa3_window3_f19 isa3_window3_f19.s
1165 isa3_fsr3_f1 isa3_fsr3_f1.s
1166 isa3_fsr3_f2 isa3_fsr3_f2.s
1167 isa3_fsr3_f3 isa3_fsr3_f3.s
1168 isa3_fsr3_f4 isa3_fsr3_f4.s
1169 isa3_fsr3_f5 isa3_fsr3_f5.s
1170 isa3_fsr3_f6 isa3_fsr3_f6.s
1171 isa3_fsr3_f8 isa3_fsr3_f8.s
1172 isa3_fsr3_f9 isa3_fsr3_f9.s
1173 isa3_fsr3_f10 isa3_fsr3_f10.s
1174 isa3_fsr3_f11 isa3_fsr3_f11.s
1175 isa3_fsr3_f12 isa3_fsr3_f12.s
1176 isa3_fsr3_f13 isa3_fsr3_f13.s
1177 isa3_fsr3_f14 isa3_fsr3_f14.s
1178 isa3_fsr3_f15 isa3_fsr3_f15.s
1179 isa3_fsr3_f16 isa3_fsr3_f16.s
1180 isa3_fsr3_f17 isa3_fsr3_f17.s
1181 isa3_fsr3_f18 isa3_fsr3_f18.s
1182
1183isa3_asr_pr_hpr_f1 isa3_asr_pr_hpr_f1.s
1184isa3_asr_pr_hpr_f2 isa3_asr_pr_hpr_f2.s
1185isa3_asr_pr_hpr_f3 isa3_asr_pr_hpr_f3.s
1186isa3_asr_pr_hpr_f4 isa3_asr_pr_hpr_f4.s
1187isa3_asr_pr_hpr_f5 isa3_asr_pr_hpr_f5.s
1188isa3_asr_pr_hpr_f6 isa3_asr_pr_hpr_f6.s
1189isa3_asr_pr_hpr_f7 isa3_asr_pr_hpr_f7.s
1190
1191#if (!defined NO_IDTLB)
1192#if (!defined FC)
1193<runargs -vcs_run_args=+thread=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
1194#endif
1195#if (defined FC)
1196<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
1197#endif
1198
1199 isa3_basic_idtlb1 isa3_basic_idtlb1.s
1200 isa3_basic_idtlb1_nohw isa3_basic_idtlb1.s -midas_args=-DNOHWTW
1201 isa3_basic_idtlb2 isa3_basic_idtlb2.s
1202 isa3_basic_idtlb3 isa3_basic_idtlb3.s
1203 isa3_basic_idtlb4 isa3_basic_idtlb4.s
1204 isa3_basic_idtlb4_nohw isa3_basic_idtlb4.s -midas_args=-DNOHWTW
1205 isa3_basic_idtlb5 isa3_basic_idtlb5.s
1206 isa3_basic_idtlb6 isa3_basic_idtlb6.s
1207 isa3_basic_dtlb1 isa3_basic_dtlb1.s
1208 isa3_basic_idtlb6_nohw isa3_basic_idtlb6.s -midas_args=-DNOHWTW
1209 isa3_basic_dtlb1_nohw isa3_basic_dtlb1.s -midas_args=-DNOHWTW
1210</runargs>
1211#endif
1212
1213isa3_mmu_f1 isa3_mmu_f1.s
1214isa3_mmu_f2 isa3_mmu_f2.s
1215isa3_scratchpad_f1 isa3_scratchpad_f1.s
1216isa3_scratchpad_f2 isa3_scratchpad_f2.s
1217isa3_mmu_21_52_f1 isa3_mmu_21_52_f1.s
1218
1219isa3_mmu_htw_4v_phy isa3_mmu_htw_0.s -vcs_run_args=+thread=all
1220isa3_mmu_htw_4v_real isa3_mmu_htw_3.s -vcs_run_args=+thread=all
1221
1222
1223 isa3_flushw_fc0 isa3_flushw_fc0.s
1224 isa3_basic0_f0 isa3_basic0_f0.s
1225 isa3_fsr0_f0 isa3_fsr0_f0.s
1226 isa3_window0_f0 isa3_window0_f0.s
1227
1228 spc2_hboot_test spc2_hboot_test.s
1229 spc_shutdown spc_shutdown.s
1230
1231</runargs>
1232</isa3_mt>
1233
1234<isa3_st name=isa3_st>
1235 isa3_basic3_f0 isa3_basic3_f0.s
1236 isa3_basic3_f1 isa3_basic3_f1.s
1237 isa3_basic3_f2 isa3_basic3_f2.s
1238 isa3_basic3_f3 isa3_basic3_f3.s
1239 isa3_basic3_f5 isa3_basic3_f5.s
1240 isa3_basic3_f6 isa3_basic3_f6.s
1241 isa3_basic3_f7 isa3_basic3_f7.s
1242 isa3_basic3_f8 isa3_basic3_f8.s
1243 isa3_basic3_f10 isa3_basic3_f10.s
1244 isa3_basic3_f11 isa3_basic3_f11.s
1245 isa3_basic3_f12 isa3_basic3_f12.s
1246 isa3_basic3_f13 isa3_basic3_f13.s
1247 isa3_basic3_f14 isa3_basic3_f14.s
1248 isa3_basic3_f15 isa3_basic3_f15.s
1249 isa3_basic3_f16 isa3_basic3_f16.s
1250 isa3_basic3_f17 isa3_basic3_f17.s
1251 isa3_basic3_f18 isa3_basic3_f18.s
1252 isa3_basic3_f19 isa3_basic3_f19.s
1253 isa3_window3_f0 isa3_window3_f0.s
1254 isa3_window3_f1 isa3_window3_f1.s
1255 isa3_window3_f2 isa3_window3_f2.s
1256 isa3_window3_f3 isa3_window3_f3.s
1257 isa3_window3_f4 isa3_window3_f4.s
1258 isa3_window3_f5 isa3_window3_f5.s
1259 isa3_window3_f6 isa3_window3_f6.s
1260 isa3_window3_f7 isa3_window3_f7.s
1261 isa3_window3_f8 isa3_window3_f8.s
1262 isa3_window3_f9 isa3_window3_f9.s
1263 isa3_window3_f10 isa3_window3_f10.s
1264 isa3_window3_f11 isa3_window3_f11.s
1265 isa3_window3_f12 isa3_window3_f12.s
1266 isa3_window3_f13 isa3_window3_f13.s
1267 isa3_window3_f14 isa3_window3_f14.s
1268 isa3_window3_f15 isa3_window3_f15.s
1269 isa3_window3_f16 isa3_window3_f16.s
1270 isa3_window3_f17 isa3_window3_f17.s
1271 isa3_window3_f18 isa3_window3_f18.s
1272 isa3_window3_f19 isa3_window3_f19.s
1273 isa3_fsr3_f1 isa3_fsr3_f1.s
1274 isa3_fsr3_f2 isa3_fsr3_f2.s
1275 isa3_fsr3_f3 isa3_fsr3_f3.s
1276 isa3_fsr3_f4 isa3_fsr3_f4.s
1277 isa3_fsr3_f5 isa3_fsr3_f5.s
1278 isa3_fsr3_f6 isa3_fsr3_f6.s
1279 isa3_fsr3_f8 isa3_fsr3_f8.s
1280 isa3_fsr3_f9 isa3_fsr3_f9.s
1281 isa3_fsr3_f10 isa3_fsr3_f10.s
1282 isa3_fsr3_f11 isa3_fsr3_f11.s
1283 isa3_fsr3_f12 isa3_fsr3_f12.s
1284 isa3_fsr3_f13 isa3_fsr3_f13.s
1285 isa3_fsr3_f14 isa3_fsr3_f14.s
1286 isa3_fsr3_f15 isa3_fsr3_f15.s
1287 isa3_fsr3_f16 isa3_fsr3_f16.s
1288 isa3_fsr3_f17 isa3_fsr3_f17.s
1289 isa3_fsr3_f18 isa3_fsr3_f18.s
1290
1291isa3_asr_pr_hpr_f1 isa3_asr_pr_hpr_f1.s
1292isa3_asr_pr_hpr_f2 isa3_asr_pr_hpr_f2.s
1293isa3_asr_pr_hpr_f3 isa3_asr_pr_hpr_f3.s
1294isa3_asr_pr_hpr_f4 isa3_asr_pr_hpr_f4.s
1295isa3_asr_pr_hpr_f5 isa3_asr_pr_hpr_f5.s
1296isa3_asr_pr_hpr_f6 isa3_asr_pr_hpr_f6.s
1297isa3_asr_pr_hpr_f7 isa3_asr_pr_hpr_f7.s
1298
1299#define NO_IDTLB
1300#if (!defined NO_IDTLB)
1301
1302
1303#if (!defined FC)
1304<runargs -vcs_run_args=+thread=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
1305#endif
1306#if (defined FC)
1307<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
1308#endif
1309
1310 isa3_basic_idtlb1 isa3_basic_idtlb1.s
1311 isa3_basic_idtlb1_nohw isa3_basic_idtlb1.s -midas_args=-DNOHWTW
1312 isa3_basic_idtlb2 isa3_basic_idtlb2.s
1313 isa3_basic_idtlb3 isa3_basic_idtlb3.s
1314 isa3_basic_idtlb4 isa3_basic_idtlb4.s
1315 isa3_basic_idtlb4_nohw isa3_basic_idtlb4.s -midas_args=-DNOHWTW
1316 isa3_basic_idtlb5 isa3_basic_idtlb5.s
1317 isa3_basic_idtlb6 isa3_basic_idtlb6.s
1318 isa3_basic_dtlb1 isa3_basic_dtlb1.s
1319 isa3_basic_idtlb6_nohw isa3_basic_idtlb6.s -midas_args=-DNOHWTW
1320 isa3_basic_dtlb1_nohw isa3_basic_dtlb1.s -midas_args=-DNOHWTW
1321</runargs>
1322#endif
1323
1324isa3_mmu_f1 isa3_mmu_f1.s
1325isa3_mmu_f2 isa3_mmu_f2.s
1326isa3_scratchpad_f1 isa3_scratchpad_f1.s
1327isa3_scratchpad_f2 isa3_scratchpad_f2.s
1328isa3_mmu_21_52_f1 isa3_mmu_21_52_f1.s
1329
1330isa3_mmu_htw_4v_phy isa3_mmu_htw_0.s -vcs_run_args=+thread=all
1331isa3_mmu_htw_4v_real isa3_mmu_htw_3.s -vcs_run_args=+thread=all
1332
1333#undef NO_IDTLB
1334 isa3_flushw_fc0 isa3_flushw_fc0.s
1335 isa3_basic0_f0 isa3_basic0_f0.s
1336 isa3_fsr0_f0 isa3_fsr0_f0.s
1337 isa3_window0_f0 isa3_window0_f0.s
1338</isa3_st>
1339
1340<isa_1215 name=isa_1215>
1341
1342 isa3_va_watchpoint isa3_va_watchpoint.s
1343 isa3_pa_watchpoint isa3_pa_watchpoint.s
1344 isa3_1215htraps1 isa3_1215htraps1.s
1345 isa3_privileged_action isa3_privileged_action.s
1346 isa3_fdacc_protection isa3_fdacc_protection.s
1347 spc_trans_test0 spc_trans_test0.s
1348 isa3_align_trap isa3_align_trap.s
1349 isa3_core_id isa3_core_id.s -nosas
1350 isa3_fp_disable_1215_0x20 isa3_fp_disable_1215_0x20.s -sas
1351 isa3_fp_excIeee_1215_0x21 isa3_fp_excIeee_1215_0x21.s -sas
1352 isa3_fp_excOther_1215_0x22 isa3_fp_excOther_1215_0x22.s -sas
1353 isa3_int_div0_1215_0x28 isa3_int_div0_1215_0x28.s -sas
1354// isa3_mod_arith_int_1215_0x3d isa3_mod_arith_int_1215_0x3d.s -nosas
1355 isa3_1215hsysmatrap isa3_1215hsysmatrap.s
1356 traps_34_35_36 traps_34_35_36.s
1357 traps_save_restore traps_save_restore.s
1358 isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -vcs_run_args=+thread=1
1359 isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -vcs_run_args=+thread=ff
1360 isa3_1215ivtrap isa3_1215ivtrap.s -vcs_run_args=+thread=ff
1361 isa3_trap_0x30 isa3_trap_0x30.s
1362 isa3_trap_0x3e isa3_trap_0x3e.s
1363 isa3_trap_0x3f isa3_trap_0x3f.s
1364 isa3_trap_0x8 isa3_trap_0x8.s
1365
1366 isa3_mt_hwtw1 isa3_mt_hwtw1.s -vcs_run_args=+thread=all
1367
1368#if (defined SPC)
1369 isa3_xir_121503 isa3_xir_121503.s -vcs_run_args=+thread=all -vcs_run_args=+intr_en=all -vcs_run_args=+intr_vect=3 -vcs_run_args=+intr_type=1 -vcs_run_args=+intr_wait=3000 -vcs_run_args=+intr_delay=100 -vcs_run_args=+lsu_mon_off
1370#endif
1371 isa3_intlevel_121503 isa3_intlevel_121503.s -vcs_run_args=+thread=all
1372 isa3_mondo_121503 isa3_mondo_121503.s -vcs_run_args=+thread=all
1373 tsotool_1t_75971 tsotool_1t_75971.s -midas_args=-allow_tsb_conflicts
1374</isa_1215>
1375
1376<pmu name=pmu>
1377
1378<runargs -nosas -midas_args=-DNOPMUENABLE>
1379 isa3_pmu_e2_t1 isa3_pmu_e2_t1.s
1380 isa3_pmu_imiss_idle isa3_pmu_imiss_idle.s
1381 isa3_pmu_int15 isa3_pmu_int15.s
1382 isa3_pmu_cpu_ldst isa3_pmu_cpu_ldst.s
1383 isa3_pmu_dmiss_idle isa3_pmu_dmiss_idle.s
1384 isa3_pmu_other isa3_pmu_other.s
1385
1386<runargs -vcs_run_args=+TIMEOUT=500000 -vcs_run_args=+skt_timeout=500000 -max_cycle=+5000000 -rtl_timeout=5000000>
1387
1388//CPU loads to CCX
1389pmu_ccx_sel5_0x04_thAll pmu_ccx_sel5_0x04_thAll.s -vcs_run_args=+thread=ff
1390
1391//CPU stores to CCX
1392pmu_ccx_sel5_0x10_thAll pmu_ccx_sel5_0x10_thAll.s -vcs_run_args=+thread=ff
1393
1394</runargs> // timeout
1395</runargs> // -nosas
1396
1397//TLB Misses
1398 itlbMiss0 itlbSl3.pal -vcs_run_args=+thread=01
1399 itlbMiss1 itlbSl3.pal -vcs_run_args=+thread=02
1400 itlbMiss2 itlbSl3.pal -vcs_run_args=+thread=04
1401 itlbMiss3 itlbSl3.pal -vcs_run_args=+thread=08
1402 itlbMiss4 itlbSl3.pal -vcs_run_args=+thread=10
1403 itlbMiss5 itlbSl3.pal -vcs_run_args=+thread=20
1404 itlbMiss6 itlbSl3.pal -vcs_run_args=+thread=40
1405 itlbMiss7 itlbSl3.pal -vcs_run_args=+thread=80
1406
1407 dtlbMiss0 dtlbSl3.pal -vcs_run_args=+thread=01
1408 dtlbMiss1 dtlbSl3.pal -vcs_run_args=+thread=02
1409 dtlbMiss2 dtlbSl3.pal -vcs_run_args=+thread=04
1410 dtlbMiss3 dtlbSl3.pal -vcs_run_args=+thread=08
1411 dtlbMiss4 dtlbSl3.pal -vcs_run_args=+thread=10
1412 dtlbMiss5 dtlbSl3.pal -vcs_run_args=+thread=20
1413 dtlbMiss6 dtlbSl3.pal -vcs_run_args=+thread=40
1414 dtlbMiss7 dtlbSl3.pal -vcs_run_args=+thread=80
1415
1416 itlbMissLoOv0 itlbSl3OvL.pal -vcs_run_args=+thread=01
1417 itlbMissLoOv1 itlbSl3OvL.pal -vcs_run_args=+thread=02
1418 itlbMissLoOv2 itlbSl3OvL.pal -vcs_run_args=+thread=04
1419 itlbMissLoOv3 itlbSl3OvL.pal -vcs_run_args=+thread=08
1420 itlbMissLoOv4 itlbSl3OvL.pal -vcs_run_args=+thread=10
1421 itlbMissLoOv5 itlbSl3OvL.pal -vcs_run_args=+thread=20
1422 itlbMissLoOv6 itlbSl3OvL.pal -vcs_run_args=+thread=40
1423 itlbMissLoOv7 itlbSl3OvL.pal -vcs_run_args=+thread=80
1424
1425 itlbMissHiOv0 itlbSl3OvH.pal -vcs_run_args=+thread=01
1426 itlbMissHiOv1 itlbSl3OvH.pal -vcs_run_args=+thread=02
1427 itlbMissHiOv2 itlbSl3OvH.pal -vcs_run_args=+thread=04
1428 itlbMissHiOv3 itlbSl3OvH.pal -vcs_run_args=+thread=08
1429 itlbMissHiOv4 itlbSl3OvH.pal -vcs_run_args=+thread=10
1430 itlbMissHiOv5 itlbSl3OvH.pal -vcs_run_args=+thread=20
1431 itlbMissHiOv6 itlbSl3OvH.pal -vcs_run_args=+thread=40
1432 itlbMissHiOv7 itlbSl3OvH.pal -vcs_run_args=+thread=80
1433
1434 dtlbMissLoOv0 dtlbSl3OvL.pal -vcs_run_args=+thread=01
1435 dtlbMissLoOv1 dtlbSl3OvL.pal -vcs_run_args=+thread=02
1436 dtlbMissLoOv2 dtlbSl3OvL.pal -vcs_run_args=+thread=04
1437 dtlbMissLoOv3 dtlbSl3OvL.pal -vcs_run_args=+thread=08
1438 dtlbMissLoOv4 dtlbSl3OvL.pal -vcs_run_args=+thread=10
1439 dtlbMissLoOv5 dtlbSl3OvL.pal -vcs_run_args=+thread=20
1440 dtlbMissLoOv6 dtlbSl3OvL.pal -vcs_run_args=+thread=40
1441 dtlbMissLoOv7 dtlbSl3OvL.pal -vcs_run_args=+thread=80
1442
1443 dtlbMissHiOv0 dtlbSl3OvH.pal -vcs_run_args=+thread=01
1444 dtlbMissHiOv1 dtlbSl3OvH.pal -vcs_run_args=+thread=02
1445 dtlbMissHiOv2 dtlbSl3OvH.pal -vcs_run_args=+thread=04
1446 dtlbMissHiOv3 dtlbSl3OvH.pal -vcs_run_args=+thread=08
1447 dtlbMissHiOv4 dtlbSl3OvH.pal -vcs_run_args=+thread=10
1448 dtlbMissHiOv5 dtlbSl3OvH.pal -vcs_run_args=+thread=20
1449 dtlbMissHiOv6 dtlbSl3OvH.pal -vcs_run_args=+thread=40
1450 dtlbMissHiOv7 dtlbSl3OvH.pal -vcs_run_args=+thread=80
1451
1452//Cache misses
1453 icacheMiss0 icacheMissSl3.s -vcs_run_args=+thread=01
1454 icacheMiss1 icacheMissSl3.s -vcs_run_args=+thread=02
1455 icacheMiss2 icacheMissSl3.s -vcs_run_args=+thread=04
1456 icacheMiss3 icacheMissSl3.s -vcs_run_args=+thread=08
1457 icacheMiss4 icacheMissSl3.s -vcs_run_args=+thread=10
1458 icacheMiss5 icacheMissSl3.s -vcs_run_args=+thread=20
1459 icacheMiss6 icacheMissSl3.s -vcs_run_args=+thread=40
1460// icacheMiss7 icacheMissSl3.s -vcs_run_args=+thread=80
1461
1462 dcacheMiss0 dcacheMissSl3.s -vcs_run_args=+thread=01
1463 dcacheMiss1 dcacheMissSl3.s -vcs_run_args=+thread=02
1464 dcacheMiss2 dcacheMissSl3.s -vcs_run_args=+thread=04
1465 dcacheMiss3 dcacheMissSl3.s -vcs_run_args=+thread=08
1466 dcacheMiss4 dcacheMissSl3.s -vcs_run_args=+thread=10
1467 dcacheMiss5 dcacheMissSl3.s -vcs_run_args=+thread=20
1468 dcacheMiss6 dcacheMissSl3.s -vcs_run_args=+thread=40
1469 dcacheMiss7 dcacheMissSl3.s -vcs_run_args=+thread=80
1470
1471 dcacheOvH0 dcacheOvH.s -vcs_run_args=+thread=01
1472 dcacheOvH1 dcacheOvH.s -vcs_run_args=+thread=02
1473 dcacheOvH2 dcacheOvH.s -vcs_run_args=+thread=04
1474 dcacheOvH3 dcacheOvH.s -vcs_run_args=+thread=08
1475 dcacheOvH4 dcacheOvH.s -vcs_run_args=+thread=10
1476 dcacheOvH5 dcacheOvH.s -vcs_run_args=+thread=20
1477 dcacheOvH6 dcacheOvH.s -vcs_run_args=+thread=40
1478 dcacheOvH7 dcacheOvH.s -vcs_run_args=+thread=80
1479
1480 dcacheOvL0 dcacheOvL.s -vcs_run_args=+thread=01
1481 dcacheOvL1 dcacheOvL.s -vcs_run_args=+thread=02
1482 dcacheOvL2 dcacheOvL.s -vcs_run_args=+thread=04
1483 dcacheOvL3 dcacheOvL.s -vcs_run_args=+thread=08
1484 dcacheOvL4 dcacheOvL.s -vcs_run_args=+thread=10
1485 dcacheOvL5 dcacheOvL.s -vcs_run_args=+thread=20
1486 dcacheOvL6 dcacheOvL.s -vcs_run_args=+thread=40
1487 dcacheOvL7 dcacheOvL.s -vcs_run_args=+thread=80
1488
1489#ifdef SPC
1490 dcacheMissL20 dcacheL2MissSl3.s -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1 -nosas
1491 dcacheMissL21 dcacheL2MissSl3.s -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
1492 dcacheMissL22 dcacheL2MissSl3.s -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
1493 dcacheMissL23 dcacheL2MissSl3.s -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
1494 dcacheMissL24 dcacheL2MissSl3.s -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
1495 dcacheMissL25 dcacheL2MissSl3.s -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
1496 dcacheMissL26 dcacheL2MissSl3.s -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
1497 dcacheMissL27 dcacheL2MissSl3.s -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1
1498
1499
1500 icMiss0 icMissL2Miss.pal -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1
1501 icMiss1 icMissL2Miss.pal -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
1502 icMiss2 icMissL2Miss.pal -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
1503 icMiss3 icMissL2Miss.pal -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
1504 icMiss4 icMissL2Miss.pal -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
1505 icMiss5 icMissL2Miss.pal -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
1506 icMiss6 icMissL2Miss.pal -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
1507 icMiss7 icMissL2Miss.pal -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1
1508#endif
1509
1510 pmuAtomic pmuAtomic.s -vcs_run_args=+thread=all
1511
1512 pmuOverflowBit ovBitTest.pal -vcs_run_args=+thread=all
1513
1514#ifdef SPC
1515//SL 4 test
1516 serviceLevel4 pmu_sl4_mask_n2.pal -vcs_run_args=+l2miss_type=1 -nosas
1517#endif
1518</pmu>
1519<fgu_traps name=fgu_traps>
1520
1521fgu_ieee_traps_01 fgu_ieee_traps_01.s
1522fgu_ieee_traps_02 fgu_ieee_traps_02.s
1523fgu_ieee_traps_03 fgu_ieee_traps_03.s
1524fgu_ieee_traps_04 fgu_ieee_traps_04.s
1525fgu_ieee_traps_05 fgu_ieee_traps_05.s
1526fgu_ieee_traps_06 fgu_ieee_traps_06.s
1527fgu_ieee_traps_07 fgu_ieee_traps_07.s
1528fgu_ieee_traps_08 fgu_ieee_traps_08.s
1529fgu_ieee_traps_09 fgu_ieee_traps_09.s
1530fgu_ieee_traps_10 fgu_ieee_traps_10.s
1531fgu_idiv_traps_01 fgu_idiv_traps_01.s
1532fgu_idiv_traps_02 fgu_idiv_traps_02.s
1533fgu_idiv_traps_03 fgu_idiv_traps_03.s
1534fgu_idiv_traps_04 fgu_idiv_traps_04.s
1535fgu_idiv_traps_05 fgu_idiv_traps_05.s
1536fgu_idiv_traps_06 fgu_idiv_traps_06.s
1537fgu_idiv_traps_07 fgu_idiv_traps_07.s
1538fgu_idiv_traps_08 fgu_idiv_traps_08.s
1539fgu_idiv_traps_09 fgu_idiv_traps_09.s
1540fgu_idiv_traps_10 fgu_idiv_traps_10.s
1541fgu_siam_traps_21 fgu_siam_traps_21.s
1542fgu_stfsr_traps_22 fgu_stfsr_traps_22.s
1543fgu_stxfsr_traps_23 fgu_stxfsr_traps_23.s
1544fgu_ieee_traps_24 fgu_ieee_traps_24.s
1545fgu_ieee_traps_25 fgu_ieee_traps_25.s
1546fgu_ieee_traps_26 fgu_ieee_traps_26.s
1547fgu_ieee_traps_27 fgu_ieee_traps_27.s
1548fgu_ieee_traps_28 fgu_ieee_traps_28.s
1549fgu_ieee_traps_29 fgu_ieee_traps_29.s
1550fgu_ieee_traps_30 fgu_ieee_traps_30.s
1551
1552</fgu_traps>
1553<runargs -vcs_run_args=+thread=01>
1554<exu_ported name=exu_ported>
1555
1556exu_add_n2 exu_add_n2.s
1557exu_irf_global_n2 exu_irf_global_n2.s
1558exu_irf_local_n2 exu_irf_local_n2.s
1559exu_logical_n2 exu_logical_n2.s
1560exu_move_n2 exu_move_n2.s
1561exu_muldiv_n2 exu_muldiv_n2.s
1562exu_shift_n2 exu_shift_n2.s
1563exu_sub_n2 exu_sub_n2.s
1564
1565exu_win_traps_n2 exu_win_traps_n2.s
1566
1567fp_addsub0_n2 fp_addsub0_n2.s
1568fp_fadd_norm_sv_n2 fp_fadd_norm_sv_n2.s
1569fp_fdiv_man_sv_n2 fp_fdiv_man_sv_n2.s
1570fp_fprs0_n2 fp_fprs0_n2.s
1571fp_ieee_flags_n2 fp_ieee_flags_n2.s
1572fp_movixcc0_n2 fp_movixcc0_n2.s
1573fp_movixcc1_n2 fp_movixcc1_n2.s
1574fp_movixcc2_n2 fp_movixcc2_n2.s
1575fp_muldiv0_a_n2 fp_muldiv0_a_n2.s
1576fp_muldiv0_n2 fp_muldiv0_n2.s
1577fp_sticky_bits_n2 fp_sticky_bits_n2.s
1578
1579
1580ffu_blkst_stall_n2 ffu_blkst_stall_n2.s
1581ffu_faligndata_n2 ffu_faligndata_n2.s
1582ffu_fpaddsub_n2 ffu_fpaddsub_n2.s
1583ffu_fplogic_n2 ffu_fplogic_n2.s
1584ffu_fpreg_rw_n2 ffu_fpreg_rw_n2.s
1585ffu_fsr_gsr_n2 ffu_fsr_gsr_n2.s
1586ffu_fsr_tem_n2 ffu_fsr_tem_n2.s
1587ffu_siam_n2 ffu_siam_n2.s
1588</exu_ported>
1589</runargs>
1590
1591<isa1_st name=isa1_st>
1592
1593 isa1_noldst_fc_0513 isa1_noldst_fc_0513.s
1594 lsu_align_raw lsu_align_raw.s
1595 lsu_storeraw_fc_0 lsu_storeraw_fc_0.s
1596 spc_basic_isa2_fc_0 spc_basic_isa2_fc_0.s
1597 spc_mul_ldst spc_mul_ldst.s
1598 spc_asi spc_asi.s
1599 spc_flush0 spc_flush0.s
1600 ldst_atomic ldst_atomic.s
1601</isa1_st>
1602<isa1_mt name=isa1_mt>
1603
1604
1605#if (!defined FC)
1606<runargs -vcs_run_args=+thread=all>
1607#endif
1608#if (defined FC)
1609<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
1610#endif
1611
1612 biccgen biccgen.s
1613 bpccgen bpccgen.s
1614 bprgen bprgen.s
1615 ifu_basic_bicc ifu_basic_bicc.s
1616 ifu_basic_br1 ifu_basic_br1.s
1617 ifu_basic_br2 ifu_basic_br2.s
1618 ifu_basic_br ifu_basic_br.s
1619 ifu_basic_ex1 ifu_basic_ex1.s
1620 ifu_basic_ex_raw ifu_basic_ex_raw.s
1621 ifu_basic_mov ifu_basic_mov.s
1622 ifu_basic_branch ifu_basic_branch.s
1623 lsu_cpqfill lsu_cpqfill.s
1624 spc_pmu_asr spc_pmu_asr.s
1625 spc_tlu_rml_asr spc_tlu_rml_asr.s
1626</runargs>
1627</isa1_mt>
1628<isa1_nospec name=isa1_nospec>
1629
1630<runargs -midas_args=-DNOSPEC_EN>
1631 ifu_basic_x ifu_basic_x.s
1632 ifu_basic_branch ifu_basic_branch.s
1633 biccgen biccgen.s
1634 bpccgen bpccgen.s
1635 bprgen bprgen.s
1636 isa1_noldst_fc_0513 isa1_noldst_fc_0513.s
1637 spc_basic_isa2_fc_0 spc_basic_isa2_fc_0.s
1638</runargs>
1639</isa1_nospec>
1640
1641
1642</runargs>
1643</runargs>
1644</sys(all_T2)>
1645
1646////////////////////////////////////////////////////////////////////////////////////////////////////
1647
1648#ifdef CMP
1649#undef ALL_THREADS
1650#undef CMP1
1651#undef CMP
1652#undef sys
1653#undef SYSNAME
1654#endif
Full OpenSPARC design & verification tarball including full HDL.