// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: cmp1.diaglist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
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// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
#define sys(x) cmp1_ ## x
////////////////////////////////////////////////////////////////////////////////////////////
// added this group of tests for OpenSparc T2 (called cmp1_mini_T2)
////////////////////////////////////////////////////////////////////////////////////////////
<runargs -sys=cmp1 -tg_seed=1 >
<runargs -sas -vcs_run_args=+show_delta>
// has 6 tests that should pass
<cmp_tso_diag name=cmp_tso_diag>
tso_n1_cross_mod103 tso_n1_cross_mod103.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3
<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=0f -midas_args=-DNOHWTW>
v9_4thread_kaos v9_4th_kao_02_25_04_4.s
<cmp_tlu_fast name=cmp_tlu_fast>
tlu_halt_park tlu_halt_park.s -vcs_run_args=+thread=all
<cmp_fgu_traps name=cmp_fgu_traps>
fgu_stfsr_traps_22 fgu_stfsr_traps_22.s
<cmp_lsu_fast name=cmp_lsu_fast>
mmu_mt_demap_0 mmu_mt_demap_0.s -midas_args=-DNOHWTW -vcs_run_args=+thread=all
////////////////////////////////////////////////////////////////////////////////////////////
// added this group of tests for OpenSparc T2 (called cmp1_all_T2)
////////////////////////////////////////////////////////////////////////////////////////////
<runargs -sys=cmp1 -tg_seed=1>
<runargs -nosas -vcs_run_args=+show_delta>
<core_qualify name=core_qualify>
// Always run with TSO_CHECKER enabled
<runargs -sas_run_args=-DTSO_CHECKER>
<runargs -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-allow_tsb_conflicts -fast_boot -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+8_FBDIMMS -vcs_run_args=+l2cpx_errmon_off>
n2_8tcasxa_2 n2_8tcasxa_2.s
n2_8t_ldst1_7 n2_8t_ldst1_7.s
n2_8t_bstbld_1 n2_8t_bstbld_1.s
<runargs -fast_boot -midas_args=-allow_tsb_conflicts -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DCMP_THREAD_START=ALL -finish_mask=all -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -vcs_run_args=+l2esr_mon_off -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+8_FBDIMMS -midas_args=-DL2_REG_PROG -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2cpx_errmon_off>
n2_cpx_fill_io_8b n2_cpx_fill_io_8b.s
n2_cpx_ifill8b n2_cpx_ifill8b.s
<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-allow_tsb_conflicts>
mpgen_semi_full_isa_1 mpgen_semi_full_isa_1.s
mpgen_semi_full_isa_2 mpgen_semi_full_isa_2.s
mpgen_semi_full_isa_3 mpgen_semi_full_isa_3.s
mpgen_ldst_mix mpgen_ldst_mix.s
mpgen_ldst_int_no_asi mpgen_ldst_int_no_asi.s
mpgen_ldst_all_l2_banks mpgen_ldst_all_l2_banks.s
mpgen_smc_1 mpgen_smc_1.s
mpgen_smc_2 mpgen_smc_2.s
mpgen_smc_3 mpgen_smc_3.s
mpgen_smc_4 mpgen_smc_4.s
mpgen_dynamic_spec_cache mpgen_dynamic_spec_cache.s
mpgen_tso_atomic_1_bank mpgen_tso_atomic_1_bank.s
<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+l2cpx_errmon_off>
<runargs -rtl_timeout=20000 -vcs_run_args=+skt_timeout=20000 -vcs_run_args=+th_timeout=50000>
tlu_fcrand05_ind_14 tlu_fcrand05_ind_14.s
// fcrand05_rand_38 fcrand05_rand_38.s -midas_args=-DMULTIPASS=2
fcrand05_rand_88 fcrand05_rand_88.s -midas_args=-DMULTIPASS=2
// fcrand05_rand_4 fcrand05_rand_4.s -midas_args=-DMULTIPASS=2
// fcrand05_rand_37 fcrand05_rand_37.s -midas_args=-DMULTIPASS=2
// fcrand05_rand_43 fcrand05_rand_43.s -midas_args=-DMULTIPASS=2
tlu_rand5fc_8149597 tlu_rand5fc_8149597.s -midas_args=-DMULTIPASS=1
dcache_diag_test_0 dcache_diag_test_0.s -nosas -vcs_run_args=+gchkr_off
lsu_dcache_diagnostic lsu_dcache_diagnostic.s -nosas -vcs_run_args=+gchkr_off
<runargs -midas_args=-allow_tsb_conflicts>
lsu_hang_cwp lsu_hang_cwp.s -vcs_run_args=+thread=all -vcs_run_args=+th_timeout=8000 -tg_seed=1
#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
lsu_casa_std_pst0 lsu_casa_std_pst0.s
lsu_casa_std_pst1 lsu_casa_std_pst1.s
lsu_casa_std_pst2 lsu_casa_std_pst2.s
lsu_casa_std_pst3 lsu_casa_std_pst3.s
lsu_casa_std_pst4 lsu_casa_std_pst4.s
lsu_casa_std_pst5 lsu_casa_std_pst5.s
lsu_casa_std_pst6 lsu_casa_std_pst6.s
lsu_casa_std_pst7 lsu_casa_std_pst7.s
lsu_casa_std_pst8 lsu_casa_std_pst8.s
lsu_casa_std_pst9 lsu_casa_std_pst9.s
#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
<runargs -vcs_run_args=+thread=all -sas -midas_args=-allow_tsb_conflicts>
n2_lsu_arb_hitl1_1.j_652649_rand_0 n2_lsu_arb_hitl1_1.j_652649_rand_0.s -midas_args=-allow_tsb_conflicts
<lsu_share name=lsu_share>
<runargs -vcs_run_args=+thread=all -sas -midas_args=-allow_tsb_conflicts>
ldst_sync_fc0 ldst_sync_fc0.s -vcs_run_args=+hash_on
ldst_sync_fc1 ldst_sync_fc1.s -vcs_run_args=+hash_on
ldst_sync_fc2 ldst_sync_fc2.s
ldst_sync_fc3 ldst_sync_fc3.s
#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
ldst_sync_fc4 ldst_sync_fc4.s -vcs_run_args=+hash_on
ldst_sync_fc5 ldst_sync_fc5.s -vcs_run_args=+hash_on
ldst_sync_fc6 ldst_sync_fc6.s
ldst_sync_fc9 ldst_sync_fc9.s
ldst_sync_fc10 ldst_sync_fc10.s -vcs_run_args=+inval_rate=300 -vcs_run_args=+hash_on
ldst_sync_fc11 ldst_sync_fc11.s -vcs_run_args=+inval_rate=300 -vcs_run_args=+hash_on
ldst_sync_fc13 ldst_sync_fc13.s -vcs_run_args=+inval_rate=400
ldst_sync_fc15 ldst_sync_fc15.s -vcs_run_args=+inval_rate=400
ldst_sync_fc16 ldst_sync_fc16.s -vcs_run_args=+inval_rate=500
ldst_sync_fc17 ldst_sync_fc17.s -vcs_run_args=+inval_rate=500
ldst_sync_fc18 ldst_sync_fc18.s -vcs_run_args=+inval_rate=500
ldst_sync_fc19 ldst_sync_fc19.s -vcs_run_args=+inval_rate=500
ifu_basic_ld ifu_basic_ld.s
ldst_sync_ldd ldst_sync_ldd.s
ldst_sync_fc7 ldst_sync_fc7.s
ldst_sync_fc8 ldst_sync_fc8.s
ldst_sync_fc12 ldst_sync_fc12.s -vcs_run_args=+inval_rate=300
ldst_sync_fc14 ldst_sync_fc14.s -vcs_run_args=+inval_rate=400
<runargs -vcs_run_args=-max_cycle=100000>
n2_lsu_asi_ring_01 n2_lsu_asi_ring_01.s -vcs_run_args=+thread=all
n2_lsu_asi_ring_02 n2_lsu_asi_ring_02.s -vcs_run_args=+thread=all
n2_lsu_asi_ring_03 n2_lsu_asi_ring_03.s -vcs_run_args=+thread=all
<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off -vcs_run_args=+noDebugModes>
err_dttp_diag err_dttp_diag.s -vcs_run_args=+thread=03
err_dtdp_diag err_dtdp_diag.s -vcs_run_args=+thread=03
err_sbdpu_diag_0 err_sbdpu_diag.s
err_sbdpu_diag_1 err_sbdpu_diag.s -vcs_run_args=+thread=02
err_sbdpu_diag_2 err_sbdpu_diag.s -vcs_run_args=+thread=04
err_sbdpu_diag_3 err_sbdpu_diag.s -vcs_run_args=+thread=08
err_sbdpu_diag_4 err_sbdpu_diag.s -vcs_run_args=+thread=10
err_sbdpu_diag_5 err_sbdpu_diag.s -vcs_run_args=+thread=20
err_sbdpu_diag_6 err_sbdpu_diag.s -vcs_run_args=+thread=40
err_sbdpu_diag_7 err_sbdpu_diag.s -vcs_run_args=+thread=80
<runargs -sas -vcs_run_args=+thread=all -midas_args=-DINC_ERR_TRAPS -vcs_run_args=+noDebugModes>
<runargs -midas_args=-allow_tsb_conflicts>
//---------------------------
<runargs -vcs_run_args=+thread=01>
blimp_rand1_st_2865865 blimp_rand1_st_2865865.s
// #90867 - 8t diag fails ST
blimp_rand1_8t_3148963 blimp_rand1_8t_3148963.s
//---------------------------
<runargs -vcs_run_args=+thread=11>
// #102229 TLU redirect with error injection
blimp_rand1_8t_11_7812675 blimp_rand1.knobs_7812675.s -tg_seed=1411795610 -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_ic_on -midas_args=-DINC_ERR_TRAPS
//---------------------------
<runargs -vcs_run_args=+thread=0f>
//---------------------------
<runargs -vcs_run_args=+thread=ff>
// #90696 PC miscmp on trap
blimp_rand1_8t_3033526 blimp_rand1_8t_3033526.s
blimp_rand1_8t_4240359 blimp_rand1_8t_4240359.s
blimp_rand1_8t_4527139 blimp_rand1_8t_4527139.s
blimp_rand4_8t_4528891 blimp_rand4_8t_4528891.s
blimp_rand5_8t_6471004 blimp_rand5_8t_6471004.s
// #100870 - 2 traps taken at once
blimp_rand3.knobs_7246351 blimp_rand3.knobs_7246351.s -vcs_run_args=+random_ccx_gnt -vcs_run_args=+min_ccx_gnt_delay=2 -vcs_run_args=+max_ccx_gnt_delay=10 -vcs_run_args=+TIMEOUT=10000 -max_cycle=+4000000 -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_irf_on -vcs_run_args=+err_irf_freq=45 -midas_args=-DINC_ERR_TRAPS -vcs_run_args=+thread=ff -tg_seed=1344387010
<tso_diags name=tso_diags>
tso_n1_bcopy tso_n1_bcopy.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
tso_n1_binit1 tso_n1_binit1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
tso_n1_binit2 tso_n1_binit2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
tso_n1_binit3 tso_n1_binit3.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
tso_n1_cross_mod1 tso_n1_cross_mod1.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_cross_mod101 tso_n1_cross_mod101.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_cross_mod102 tso_n1_cross_mod102.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_cross_mod103 tso_n1_cross_mod103.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_cross_mod2 tso_n1_cross_mod2.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_cross_mod201 tso_n1_cross_mod201.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_cross_mod203 tso_n1_cross_mod203.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_cross_mod3 tso_n1_cross_mod3.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+inst_check_off=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_cross_mod4 tso_n1_cross_mod4.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
tso_n1_cross_mod5 tso_n1_cross_mod5.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_cross_mod6_bug6372 tso_n1_cross_mod6_bug6372.s -midas_args=-DTHREAD_COUNT=4 -finish_mask=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=f
tso_n1_dekker1 tso_n1_dekker1.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_dekker2 tso_n1_dekker2.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3
tso_n1_dekker10 tso_n1_dekker10.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_dekker11 tso_n1_dekker11.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
tso_n1_false_sharing1 tso_n1_false_sharing1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_false_sharing2 tso_n1_false_sharing2.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
tso_n1_false_sharing_vershort tso_n1_false_sharing_vershort.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
tso_n1_indirection1 tso_n1_indirection1.s -finish_mask=7 -midas_args=-DTHREAD_COUNT=3 -vcs_run_args=+show_delta -vcs_run_args=+thread=7 -nosas
tso_n1_indirection2 tso_n1_indirection2.s -finish_mask=7 -midas_args=-DTHREAD_COUNT=3 -vcs_run_args=+show_delta -vcs_run_args=+thread=7 -nosas
tso_n1_membar1 tso_n1_membar1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
tso_n1_mutex1 tso_n1_mutex1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_mutex2_ldstub tso_n1_mutex2_ldstub.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_mutex3_cas tso_n1_mutex3_cas.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_mutex4_casx tso_n1_mutex4_casx.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_mutex5_swap_casx tso_n1_mutex5_swap_casx.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_prod_cons1 tso_n1_prod_cons1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_prod_cons2 tso_n1_prod_cons2.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_prod_cons_variation1_1 tso_n1_prod_cons_variation1_1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_prod_cons_variation2_1 tso_n1_prod_cons_variation2_1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
tso_n1_self_mod1 tso_n1_self_mod1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod2 tso_n1_self_mod2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod3 tso_n1_self_mod3.s -midas_args=-DCMP_THREAD_START=0x11 -finish_mask=11 -vcs_run_args=+show_delta
tso_n1_self_mod5 tso_n1_self_mod5.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod6 tso_n1_self_mod6.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod7 tso_n1_self_mod7.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod8 tso_n1_self_mod8.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod9 tso_n1_self_mod9.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod10 tso_n1_self_mod10.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod11 tso_n1_self_mod11.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod101 tso_n1_self_mod101.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod102 tso_n1_self_mod102.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod103 tso_n1_self_mod103.s -finish_mask=11 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=11 -nosas
tso_n1_self_mod104 tso_n1_self_mod104.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod105 tso_n1_self_mod105.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod106 tso_n1_self_mod106.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod107 tso_n1_self_mod107.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod108 tso_n1_self_mod108.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod109 tso_n1_self_mod109.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod110 tso_n1_self_mod110.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod111 tso_n1_self_mod111.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod201 tso_n1_self_mod201.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod202 tso_n1_self_mod202.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod203 tso_n1_self_mod203.s -finish_mask=11 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=11 -nosas
tso_n1_self_mod206 tso_n1_self_mod206.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_self_mod207 tso_n1_self_mod207.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
tso_n1_starve0 tso_n1_starve0.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
tso_n1_starve1 tso_n1_starve1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
tso_n1_prod_cons1_pio tso_n1_prod_cons1_pio.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
tso_n1_prod_cons2_pio tso_n1_prod_cons1_pio.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
tso_n1_dekker1_pio tso_n1_dekker1_pio.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+thread=3
tso_n1_dekker2_pio tso_n1_dekker2_pio.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+thread=3
tso_n1_dekker7 tso_n1_dekker7.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
tso_n1_dekker8 tso_n1_dekker8.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
tso_n1_dekker9 tso_n1_dekker9.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
tso_n1_peterson1 tso_n1_peterson1.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
tso_n1_peterson2 tso_n1_peterson2.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
tso_n1_peterson3 tso_n1_peterson3.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
// Really long running diags go here!
<long_tso_diags name=long_tso_diags>
tso_n1_ld_starve1 tso_n1_ld_starve1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
tso_n1_ld_starve2 tso_n1_ld_starve2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
<runargs -vcs_run_args=+noredwdrkill>
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
tlu_rand01_ind_02 tlu_rand01_ind_02.s
tlu_rand02_ind_07 tlu_rand02_ind_07.s
tlu_rand02_ind_08 tlu_rand02_ind_08.s
tlu_rand02_ind_09 tlu_rand02_ind_09.s
tlu_rand02_ind_10 tlu_rand02_ind_10.s
tlu_rand03_ind_03 tlu_rand03_ind_03.s
tlu_rand03_ind_04 tlu_rand03_ind_04.s
tlu_rand03_ind_07 tlu_rand03_ind_07.s
tlu_rand03_ind_08 tlu_rand03_ind_08.s
tlu_rand03_ind_05 tlu_rand03_ind_05.s
tlu_rand03_ind_06 tlu_rand03_ind_06.s
tlu_rand03_ind_09 tlu_rand03_ind_09.s
#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
tlu_rand04_ind_02 tlu_rand04_ind_02.s
tlu_rand04_ind_03 tlu_rand04_ind_03.s
tlu_rand04_ind_04 tlu_rand04_ind_04.s
tlu_rand04_ind_19 tlu_rand04_ind_19.s
tlu_rand04_ind_21 tlu_rand04_ind_21.s
tlu_rand04_ind_22 tlu_rand04_ind_22.s
// TLU rand5 diags use user events
<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off>
err_tcc_hstick_diag err_tcc_hstick_diag.s -vcs_run_args=+thread=01
err_tcc_hstick_diag_1 err_tcc_hstick_diag.s -vcs_run_args=+thread=02
err_tcc_hstick_diag_2 err_tcc_hstick_diag.s -vcs_run_args=+thread=04
err_tcc_hstick_diag_3 err_tcc_hstick_diag.s -vcs_run_args=+thread=08
err_tcc_hstick_diag_4 err_tcc_hstick_diag.s -vcs_run_args=+thread=10
err_tcc_hstick_diag_5 err_tcc_hstick_diag.s -vcs_run_args=+thread=20
err_tcc_hstick_diag_6 err_tcc_hstick_diag.s -vcs_run_args=+thread=40
err_tcc_hstick_diag_7 err_tcc_hstick_diag.s -vcs_run_args=+thread=80
err_inj_mondo_diag err_inj_mondo_diag.s -vcs_run_args=+thread=01
err_inj_mondo_diag_1 err_inj_mondo_diag.s -vcs_run_args=+thread=02
err_inj_mondo_diag_2 err_inj_mondo_diag.s -vcs_run_args=+thread=04
err_inj_mondo_diag_3 err_inj_mondo_diag.s -vcs_run_args=+thread=08
err_inj_mondo_diag_4 err_inj_mondo_diag.s -vcs_run_args=+thread=10
err_inj_mondo_diag_5 err_inj_mondo_diag.s -vcs_run_args=+thread=20
err_inj_mondo_diag_6 err_inj_mondo_diag.s -vcs_run_args=+thread=40
err_inj_mondo_diag_7 err_inj_mondo_diag.s -vcs_run_args=+thread=80
err_tsa_diag err_tsa_diag.s -vcs_run_args=+thread=01
err_tsa_diag_1 err_tsa_diag.s -vcs_run_args=+thread=02
err_tsa_diag_2 err_tsa_diag.s -vcs_run_args=+thread=04
err_tsa_diag_3 err_tsa_diag.s -vcs_run_args=+thread=08
err_tsa_diag_4 err_tsa_diag.s -vcs_run_args=+thread=10
err_tsa_diag_5 err_tsa_diag.s -vcs_run_args=+thread=20
err_tsa_diag_6 err_tsa_diag.s -vcs_run_args=+thread=40
err_tsa_diag_7 err_tsa_diag.s -vcs_run_args=+thread=80
err_stick_cmpr_cycle err_stick_cmpr_cycle.s -vcs_run_args=+thread=01
err_stick_cmpr_cycle_1 err_stick_cmpr_cycle.s -vcs_run_args=+thread=02
err_stick_cmpr_cycle_2 err_stick_cmpr_cycle.s -vcs_run_args=+thread=04
err_stick_cmpr_cycle_3 err_stick_cmpr_cycle.s -vcs_run_args=+thread=08
err_stick_cmpr_cycle_4 err_stick_cmpr_cycle.s -vcs_run_args=+thread=10
err_stick_cmpr_cycle_5 err_stick_cmpr_cycle.s -vcs_run_args=+thread=20
err_stick_cmpr_cycle_6 err_stick_cmpr_cycle.s -vcs_run_args=+thread=40
err_stick_cmpr_cycle_7 err_stick_cmpr_cycle.s -vcs_run_args=+thread=80
err_tick_cmpr_cycle_c1_n2 err_tick_cmpr_cycle_c1_n2.s -vcs_run_args=+thread=01
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
tlu_rand05_ind_10_11_8 tlu_rand05_ind_10_11_8.s
tlu_swtraps tlu_swtraps.pal
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
tlu_allintvec1 tlu_allintvec1.s
tlu_allintvec2 tlu_allintvec2.s
tlu_simulint tlu_simulint.s -vcs_run_args=+err_chkrs_off
tlu_rand01_ind_01 tlu_rand01_ind_01.s
tlu_rand01_ind_04 tlu_rand01_ind_04.s
tlu_rand02_ind_03 tlu_rand02_ind_03.s
tlu_rand02_ind_05 tlu_rand02_ind_05.s
tlu_rand04_ind_01 tlu_rand04_ind_01.s
tlu_rand05_ind_01_13_1 tlu_rand05_ind_01_13_1.s
tlu_rand05_ind_39 tlu_rand05_ind_39.s
tlu_rand01_ind_09 tlu_rand01_ind_09.s
tlu_rand01_ind_11 tlu_rand01_ind_11.s
tlu_rand02_ind_02 tlu_rand02_ind_02.s
tlu_rand03_ind_02 tlu_rand03_ind_02.s
tlu_rand04_ind_02 tlu_rand04_ind_02.s
tlu_rand04_ind_14 tlu_rand04_ind_14.s
tlu_rand04_ind_15 tlu_rand04_ind_15.s
tlu_rand04_ind_21 tlu_rand04_ind_21.s
tlu_rand03_ind_05 tlu_rand03_ind_05.s
tlu_rand03_ind_06 tlu_rand03_ind_06.s
tlu_rand03_ind_09 tlu_rand03_ind_09.s
tlu_rand04_ind_03 tlu_rand04_ind_03.s
tlu_rand04_ind_04 tlu_rand04_ind_04.s
tlu_rand04_ind_06 tlu_rand04_ind_06.s
tlu_rand04_ind_07 tlu_rand04_ind_07.s
tlu_rand04_ind_16 tlu_rand04_ind_16.s
tlu_rand04_ind_19 tlu_rand04_ind_19.s
tlu_rand04_ind_20 tlu_rand04_ind_20.s
tlu_rand04_ind_22 tlu_rand04_ind_22.s
tlu_rand04_ind_08 tlu_rand04_ind_08.s
tlu_rand04_ind_11 tlu_rand04_ind_11.s -midas_args=-DCMP_THREAD_START=0xe7 -finish_mask=e7
tlu_107450_mt tlu_107450_mt.s
<tlu_disrupting name=tlu_disrupting>
tlu_rand05_ind_08 tlu_rand05_ind_08.s
tlu_rand05_ind_10 tlu_rand05_ind_10.s
tlu_rand05_ind_11 tlu_rand05_ind_11.s
tlu_rand05_ind_12 tlu_rand05_ind_12.s
tlu_rand05_ind_15 tlu_rand05_ind_15.s
tlu_rand05_ind_16 tlu_rand05_ind_16.s
tlu_rand05_ind_01 tlu_rand05_ind_01.s
tlu_rand05_ind_02 tlu_rand05_ind_02.s
tlu_rand05_ind_03 tlu_rand05_ind_03.s
tlu_rand05_ind_04 tlu_rand05_ind_04.s
tlu_rand05_ind_06 tlu_rand05_ind_06.s
tlu_rand05_ind_07 tlu_rand05_ind_07.s
tlu_rand05_ind_01_mt tlu_rand05_ind_01.s -vcs_run_args=+thread=all
// tlu_rand05_ind_23 tlu_rand05_ind_23.s -vcs_run_args=+thread=ff
isa3_1215ivtrap2 isa3_1215ivtrap2.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
isa3_1215ivtrap isa3_1215ivtrap.s -vcs_run_args=+thread=all
isa3_intlevel_121503 isa3_intlevel_121503.s -vcs_run_args=+thread=all
isa3_mondo_121503 isa3_mondo_121503.s -vcs_run_args=+thread=all
isa3_1215hsysmatrap isa3_1215hsysmatrap.s -vcs_run_args=+thread=all
isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -vcs_run_args=+thread=1
isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -vcs_run_args=+thread=ff
err_dcdp_halt err_dcdp_halt_diag.s -vcs_run_args=+err_chkrs_off -nosas -midas_args=-DNOERRCHK
err_tcc_hstick_halt err_tcc_hstick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
err_tcc_stick_halt err_tcc_stick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
err_tcc_tick_halt err_tcc_tick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
tlu_halt_hstmatch tlu_halt_hstmatch.s -vcs_run_args=+thread=all
tlu_halt_intvec tlu_halt_intvec.s -vcs_run_args=+thread=all
// tlu_halt_modint tlu_halt_modint.s -vcs_run_args=+thread=all
// tlu_halt_cwqint tlu_halt_cwqint.s -vcs_run_args=+thread=all
tlu_halt_park tlu_halt_park.s -vcs_run_args=+thread=all
tlu_halt_stickint tlu_halt_stickint.s -vcs_run_args=+thread=all
tlu_halt_tickint tlu_halt_tickint.s -vcs_run_args=+thread=all
tlu_halt_xir tlu_halt_xir.s -vcs_run_args=+thread=all
<runargs -sas -vcs_run_args=+thread=01>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=1 >
mmu_st_unsupport_psize mmu_st_unsupport_psize.s
mmu_st_tsb_va_hole mmu_st_tsb_va_hole.s -midas_args=-DCUSTOM_TRAP_0X9
mmu_st_tsb_va_hole_1 mmu_st_tsb_va_hole_1.s -midas_args=-DCUSTOM_TRAP_0X9
mmu_st_ext_ra mmu_st_ext_ra.s
mmu_use_bit_test mmu_tag_read_use_bit_test.s
mmu_st_hwtw_enable mmu_st_hwtw_enable.s
<runargs -sas -vcs_run_args=+thread=all>
<runargs -sas -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
mmu_mt_ranotpa_0 mmu_mt_ranotpa_0.s
mmu_mt_no_hboot_hwtw_0 mmu_mt_no_hboot_hwtw_0.s
mmu_mt_no_hboot_hwtw_0a mmu_mt_no_hboot_hwtw_0.s -midas_args=-DNOHWTW
mmu_mt_ep_0 mmu_mt_ep_0.s
mmu_mt_psize_1 mmu_mt_psize_1.s
mmu_mt_realrange_0 mmu_mt_realrange_0.s
mmu_mt_realrange_1 mmu_mt_realrange_1.s
mmu_mt_hwtw_demap mmu_mt_hwtw_demap.s
mmu_mt_tsb_ptr_0 mmu_mt_tsb_ptr_0.s
mmu_mt_tsb_ptr_1 mmu_mt_tsb_ptr_1.s
mmu_mt_htba mmu_mt_htba.s -vcs_run_args=+thread=ff
mmu_mt_htba mmu_mt_htba.s -midas_args=-DCMP_THREAD_START=ff -finish_mask=all
mmu_mt_real_0 mmu_mt_real_0.s
mmu_mt_real_1 mmu_mt_real_1.s
mmu_mt_bypass_use_ctx_0 mmu_mt_bypass_use_ctx_0.s
mmu_mt_write_tsb_0 mmu_mt_write_tsb_0.s
mmu_mt_rr_0 mmu_mt_rr_0.s
mmu_mt_demap_page mmu_mt_demap_page.s
mmu_mt_demap_page_1 mmu_mt_demap_page_1.s
<runargs -sas -vcs_run_args=+thread=07 -vcs_run_args=+err_chkrs_off>
mmu_mt_mhit_0 mmu_mt_mhit_0.s -vcs_run_args=+err_sync_on
<runargs -sas -vcs_run_args=+thread=13>
mmu_mt_mhit_1 mmu_mt_mhit_1.s -vcs_run_args=+err_sync_on
<runargs -sas -vcs_run_args=+thread=21 -vcs_run_args=+err_chkrs_off>
mmu_st_mhit_2 mmu_st_mhit_2.s -vcs_run_args=+err_sync_on
<runargs -sas -vcs_run_args=+thread=03>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x03 -finish_mask=3 >
mmu_mt_use_ctx0 mmu_mt_use_ctx0.s
mmu_mt_use_ctx1 mmu_mt_use_ctx1.s
mmu_mt_rtrans_0 mmu_mt_rtrans_0.s
<runargs -sas -vcs_run_args=+thread=1f>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x1f -finish_mask=1f >
mmu_mt_asi_cp mmu_mt_asi_cp.s
<runargs -sas -vcs_run_args=+thread=01 -midas_args=-DTSB_SEARCH_BURST>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x01 -midas_args=-DTSB_SEARCH_BURST -finish_mask=1 >
mmu_st_unsupport_psize_burst mmu_st_unsupport_psize.s
mmu_st_h2p_burst mmu_st_h2p.s
mmu_st_tsb_va_hole_burst mmu_st_tsb_va_hole.s -midas_args=-DCUSTOM_TRAP_0X9
mmu_st_tsb_va_hole_1_burst mmu_st_tsb_va_hole_1.s -midas_args=-DCUSTOM_TRAP_0X9
mmu_st_ext_ra_burst mmu_st_ext_ra.s
<runargs -sas -vcs_run_args=+thread=all -midas_args=-DTSB_SEARCH_BURST>
<runargs -sas -midas_args=-DCMP_THREAD_START=all -midas_args=-DTSB_SEARCH_BURST -finish_mask=all >
mmu_mt_ranotpa_0_burst mmu_mt_ranotpa_0.s
mmu_mt_no_hboot_hwtw_0_burst mmu_mt_no_hboot_hwtw_0.s
mmu_mt_no_hboot_hwtw_0a_burst mmu_mt_no_hboot_hwtw_0.s -midas_args=-DNOHWTW
mmu_mt_ep_0_burst mmu_mt_ep_0.s
mmu_mt_psize_1_burst mmu_mt_psize_1.s
mmu_mt_realrange_0_burst mmu_mt_realrange_0.s
mmu_mt_realrange_1_burst mmu_mt_realrange_1.s
mmu_mt_hwtw_demap_burst mmu_mt_hwtw_demap.s
mmu_mt_tsb_ptr_0_burst mmu_mt_tsb_ptr_0.s
mmu_mt_tsb_ptr_1_burst mmu_mt_tsb_ptr_1.s
mmu_mt_htba_burst mmu_mt_htba.s -vcs_run_args=+thread=ff
mmu_mt_htba_burst mmu_mt_htba.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
mmu_mt_real_0_burst mmu_mt_real_0.s
mmu_mt_real_1_burst mmu_mt_real_1.s
mmu_mt_bypass_use_ctx_0_burst mmu_mt_bypass_use_ctx_0.s
mmu_mt_write_tsb_0_burst mmu_mt_write_tsb_0.s
mmu_mt_rr_0_burst mmu_mt_rr_0.s
mmu_mt_demap_page_burst mmu_mt_demap_page.s
mmu_mt_demap_page_1_burst mmu_mt_demap_page_1.s
<runargs -sas -vcs_run_args=+thread=07 -midas_args=-DTSB_SEARCH_BURST -vcs_run_args=+err_chkrs_off>
mmu_mt_mhit_0_burst mmu_mt_mhit_0.s -vcs_run_args=+err_sync_on
<runargs -sas -vcs_run_args=+thread=13 -midas_args=-DTSB_SEARCH_BURST>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x13 -midas_args=-DTSB_SEARCH_BURST -finish_mask=13 >
mmu_mt_mhit_1_burst mmu_mt_mhit_1.s -vcs_run_args=+err_sync_on
<runargs -sas -vcs_run_args=+thread=03 -midas_args=-DTSB_SEARCH_BURST>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x03 -midas_args=-DTSB_SEARCH_BURST -finish_mask=3 >
mmu_mt_use_ctx0_burst mmu_mt_use_ctx0.s
mmu_mt_use_ctx1_burst mmu_mt_use_ctx1.s
mmu_mt_rtrans_0_burst mmu_mt_rtrans_0.s
<runargs -sas -vcs_run_args=+thread=1f -midas_args=-DTSB_SEARCH_BURST>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x1f -midas_args=-DTSB_SEARCH_BURST -finish_mask=1f >
mmu_mt_asi_cp_burst mmu_mt_asi_cp.s
<runargs -sas -vcs_run_args=+thread=01 -midas_args=-DTSB_SEARCH_PREDICTION>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x01 -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=1 >
mmu_st_unsupport_psize_prediction mmu_st_unsupport_psize.s
mmu_st_h2p_prediction mmu_st_h2p.s
mmu_st_tsb_va_hole_prediction mmu_st_tsb_va_hole.s -midas_args=-DCUSTOM_TRAP_0X9
mmu_st_tsb_va_hole_1_prediction mmu_st_tsb_va_hole_1.s -midas_args=-DCUSTOM_TRAP_0X9
mmu_st_ext_ra_prediction mmu_st_ext_ra.s
<runargs -sas -vcs_run_args=+thread=all -midas_args=-DTSB_SEARCH_PREDICTION>
<runargs -sas -midas_args=-DCMP_THREAD_START=all -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=all >
mmu_mt_ranotpa_0_prediction mmu_mt_ranotpa_0.s
mmu_mt_no_hboot_hwtw_0_prediction mmu_mt_no_hboot_hwtw_0.s
mmu_mt_no_hboot_hwtw_0a_prediction mmu_mt_no_hboot_hwtw_0.s -midas_args=-DNOHWTW
mmu_mt_ep_0_prediction mmu_mt_ep_0.s
mmu_mt_psize_1_prediction mmu_mt_psize_1.s
mmu_mt_realrange_0_prediction mmu_mt_realrange_0.s
mmu_mt_realrange_1_prediction mmu_mt_realrange_1.s
mmu_mt_hwtw_demap_prediction mmu_mt_hwtw_demap.s
mmu_mt_tsb_ptr_0_prediction mmu_mt_tsb_ptr_0.s
mmu_mt_tsb_ptr_1_prediction mmu_mt_tsb_ptr_1.s
mmu_mt_htba_prediction mmu_mt_htba.s -vcs_run_args=+thread=ff
mmu_mt_htba_prediction mmu_mt_htba.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
mmu_mt_real_0_prediction mmu_mt_real_0.s
// mmu_mt_real_1_prediction mmu_mt_real_1.s
mmu_mt_bypass_use_ctx_0_prediction mmu_mt_bypass_use_ctx_0.s
mmu_mt_write_tsb_0_prediction mmu_mt_write_tsb_0.s
mmu_mt_rr_0_prediction mmu_mt_rr_0.s
mmu_mt_demap_page_prediction mmu_mt_demap_page.s
mmu_mt_demap_page_1_prediction mmu_mt_demap_page_1.s
<runargs -sas -vcs_run_args=+thread=07 -midas_args=-DTSB_SEARCH_PREDICTION -vcs_run_args=+err_chkrs_off>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x07 -midas_args=-DTSB_SEARCH_PREDICTION -vcs_run_args=+err_chkrs_off -finish_mask=7 >
mmu_mt_mhit_0_prediction mmu_mt_mhit_0.s -vcs_run_args=+err_sync_on
<runargs -sas -vcs_run_args=+thread=13 -midas_args=-DTSB_SEARCH_PREDICTION>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x13 -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=13 >
mmu_mt_mhit_1_prediction mmu_mt_mhit_1.s -vcs_run_args=+err_sync_on
<runargs -sas -vcs_run_args=+thread=03 -midas_args=-DTSB_SEARCH_PREDICTION>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x03 -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=3 >
mmu_mt_use_ctx0_prediction mmu_mt_use_ctx0.s
mmu_mt_use_ctx1_prediction mmu_mt_use_ctx1.s
mmu_mt_rtrans_0_prediction mmu_mt_rtrans_0.s
<runargs -sas -vcs_run_args=+thread=1f -midas_args=-DTSB_SEARCH_PREDICTION>
<runargs -sas -midas_args=-DCMP_THREAD_START=0x1f -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=1f >
mmu_mt_asi_cp_prediction mmu_mt_asi_cp.s
<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off>
err_sca_diag err_sca_diag.s
err_scau_diag err_scau_diag.s
err_mra_diag err_mra_diag.s
<runargs -sas -vcs_run_args=+thread=all -midas_args=-DTSB_SEARCH_PREDICTION>
<runargs -sas -midas_args=-DCMP_THREAD_START=all -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=all >
mmu_mt_real_1_prediction mmu_mt_real_1.s
<mmu_tlb_sync name=mmu_tlb_sync>
mmu_tag_read_use_bit_test mmu_tag_read_use_bit_test.s
<mmu_cmp_test name=mmu_cmp_test>
<runargs -midas_args=-DMMU247 -vcs_run_args=+thread=all -midas_args=-DENABLE_ITTM_DTTM -midas_args=-DPORTABLE_CORE>
<runargs -midas_args=-DMMU247 -midas_args=-DCMP_THREAD_START=all -midas_args=-DENABLE_ITTM_DTTM -midas_args=-DPORTABLE_CORE -finish_mask=all >
// mmu_cmp_test_0 mmu_cmp_test_0.s
// mmu_cmp_test_1 mmu_cmp_test_1.s
mmu_cmp_test_2 mmu_cmp_test_2.s
mmu_cmp_test_3 mmu_cmp_test_3.s
// mmu_cmp_test_4 mmu_cmp_test_4.s
<runargs -midas_args=-allow_tsb_conflicts>
kaos_01_07_2004_1 kaos_01_07_2004_1.s
kaos_02_03_04_18 kaos_02_03_04_18.s
kaos_02_05_2004_20 kaos_02_05_2004_20.s
kaos_02_05_2004_91 kaos_02_05_2004_91.s
kaos_02_06_2004_11 kaos_02_06_2004_11.s
kaos_02_06_2004_135 kaos_02_06_2004_135.s
kaos_02_06_2004_152 kaos_02_06_2004_152.s
kaos_02_06_2004_71 kaos_02_06_2004_71.s
kaos_27_1_2004_0_11 kaos_27_1_2004_0_11.s
kaos_27_1_2004_0_13 kaos_27_1_2004_0_13.s
kaos_27_1_2004_0_22 kaos_27_1_2004_0_22.s
kaos_27_1_2004_0_42 kaos_27_1_2004_0_42.s
kaos_27_1_2004_0_49 kaos_27_1_2004_0_49.s
v9_kao_02_10_04_19 v9_kao_02_10_04_19.s
v9_kao_02_11_04_31 v9_kao_02_11_04_31.s
v9_kao_02_14_04_101 v9_kao_02_14_04_101.s
v9_kao_02_14_04_103 v9_kao_02_14_04_103.s
v9_kao_02_14_04_112 v9_kao_02_14_04_112.s
ifu_kao_02_18_04_109 ifu_kao_02_18_04_109.s
<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=03 -midas_args=-DNOHWTW>
kaos_01_06_2004_1 kaos_01_06_2004_1.s
//v9_2th_kao_02_20_04_88 v9_2th_kao_02_20_04_88.s
v9_2th_kao_02_20_04_125 v9_2th_kao_02_20_04_125.s
v9_2th_kao_02_20_04_131 v9_2th_kao_02_20_04_131.s
v9_2th_kao_02_20_04_219 v9_2th_kao_02_20_04_219.s
v9_2th_kao_02_20_04_434 v9_2th_kao_02_20_04_434.s
v9_2th_kao_02_20_04_71 v9_2th_kao_02_20_04_71.s
<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=0f -midas_args=-DNOHWTW>
v9_4th_kao_02_25_04_4 v9_4th_kao_02_25_04_4.s
//v9_kao_4th_02_23_04_0 v9_kao_4th_02_23_04_0.s
v9_kao_4th_02_27_04_2 v9_kao_4th_02_27_04_2.s
v9_kao_4th_02_27_04_199 v9_kao_4th_02_27_04_199.s
v9_kao_4th_02_27_04_34 v9_kao_4th_02_27_04_34.s
v9_kao_4th_03_04_04_100 v9_kao_4th_03_04_04_100.s
v9_kao_4th_02_27_04_199 v9_kao_4th_02_27_04_199.s
v9_4th_kaos_03_05_04_500 v9_4th_kaos_03_05_04_500.s
v9_4th_kaos_03_05_04_105 v9_4th_kaos_03_05_04_105.s
v9_4th_kaos_03_05_04_130 v9_4th_kaos_03_05_04_130.s
v9_4th_kaos_03_05_04_101 v9_4th_kaos_03_05_04_101.s
v9_4th_kaos_03_05_04_153 v9_4th_kaos_03_05_04_153.s
v9_4th_kaos_03_05_04_501 v9_4th_kaos_03_05_04_501.s
<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=all>
v9_8th_sp_kaos_03_11_04_0 v9_8th_sp_kaos_03_11_04_0.s
v9_8th_sp_kaos_03_11_04_15 v9_8th_sp_kaos_03_11_04_15.s
v9_8th_kaos_03_16_04_0 v9_8th_kaos_03_16_04_0.s
ifu_8th_sp_kaos_03_10_04_1 ifu_8th_sp_kaos_03_10_04_1.s
v9_8th_kaos_02_08_04_20 v9_8th_kaos_02_08_04_20.s
v9_8th_sp_kaos_03_11_04_17 v9_8th_sp_kaos_03_11_04_17.s
v9_8th_kaos_03_17_04_133 v9_8th_kaos_03_17_04_133.s
v9_8th_kaos_03_17_04_0 v9_8th_kaos_03_17_04_0.s
v9_8th_kaos_03_23_04_14 v9_8th_kaos_03_23_04_14.s
v9_8th_kaos_03_17_04_10 v9_8th_kaos_03_17_04_10.s
v9_8th_kaos_02_08_04_20 v9_8th_kaos_02_08_04_20.s
v9_8th_kaos_03_14_04_396 v9_8th_kaos_03_14_04_396.s
isa_8th_kaos_03_30_04_101 isa_8th_kaos_03_30_04_101.s
v9_8th_kaos_03_01_04_102 v9_8th_kaos_03_01_04_102.s
v9_8th_kao_03_01_04_0 v9_8th_kao_03_01_04_0.s
v9_8th_kaos_02_08_04_0 v9_8th_kaos_02_08_04_0.s
<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=all>
// These diags require TLB Sync
// Add these back into kaos_8t once CMP has TLB Sync
v9_8th_kaos_03_01_04_102 v9_8th_kaos_03_01_04_102.s
v9_8th_kao_03_01_04_0 v9_8th_kao_03_01_04_0.s
v9_8th_kaos_02_08_04_0 v9_8th_kaos_02_08_04_0.s
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
isa2_raw_fc_2 isa2_raw_fc_2.s
isa2_all_fail_fc_3 isa2_all_fail_fc_3.s
spc_isa2mt_fail_fc_9 spc_isa2mt_fail_fc_9.s
spc_isa2mt_fail_fc_7 spc_isa2mt_fail_fc_7.s
spc_isa2mt_fail_fc_11 spc_isa2mt_fail_fc_11.s
isa2_basic_fc0 isa2_basic_fc0.s
isa2_basic_fc1 isa2_basic_fc1.s
isa2_basic_fc2 isa2_basic_fc2.s
isa2_basic_fc3 isa2_basic_fc3.s
isa2_basic_fc4 isa2_basic_fc4.s
isa2_basic_fc5 isa2_basic_fc5.s
isa2_basic_fc6 isa2_basic_fc6.s
isa2_basic_fc7 isa2_basic_fc7.s
isa2_basic_fc8 isa2_basic_fc8.s
isa2_basic_fc9 isa2_basic_fc9.s
isa2_basic_fc10 isa2_basic_fc10.s
isa2_basic_fc11 isa2_basic_fc11.s
isa2_basic_fc12 isa2_basic_fc12.s
isa2_basic_fc13 isa2_basic_fc13.s
isa2_basic_fc14 isa2_basic_fc14.s
isa2_basic_fc15 isa2_basic_fc15.s
isa2_basic_fc16 isa2_basic_fc16.s
isa2_basic_fc17 isa2_basic_fc17.s
isa2_basic_fc18 isa2_basic_fc18.s
isa2_basic_fc19 isa2_basic_fc19.s
isa2_basic_fc20 isa2_basic_fc20.s
isa2_basic_fc21 isa2_basic_fc21.s
isa2_basic_fc22 isa2_basic_fc22.s
isa2_basic_fc23 isa2_basic_fc23.s
isa2_basic_fc24 isa2_basic_fc24.s
isa2_basic_fc25 isa2_basic_fc25.s
isa2_basic_fc26 isa2_basic_fc26.s
isa2_basic_fc27 isa2_basic_fc27.s
isa2_basic_fc28 isa2_basic_fc28.s
isa2_basic_fc29 isa2_basic_fc29.s
<isa3_saverestore name=isa3_saverestore>
isa3_saverestore_fc0 isa3_saverestore_fc0.s
isa3_saverestore_fc1 isa3_saverestore_fc1.s
isa3_saverestore_fc2 isa3_saverestore_fc2.s
isa3_saverestore_fc3 isa3_saverestore_fc3.s
isa3_saverestore_fc4 isa3_saverestore_fc4.s
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
isa3_basic3_f0 isa3_basic3_f0.s
isa3_basic3_f1 isa3_basic3_f1.s
isa3_basic3_f2 isa3_basic3_f2.s
isa3_basic3_f3 isa3_basic3_f3.s
isa3_basic3_f5 isa3_basic3_f5.s
isa3_basic3_f6 isa3_basic3_f6.s
isa3_basic3_f7 isa3_basic3_f7.s
isa3_basic3_f8 isa3_basic3_f8.s
isa3_basic3_f10 isa3_basic3_f10.s
isa3_basic3_f11 isa3_basic3_f11.s
isa3_basic3_f12 isa3_basic3_f12.s
isa3_basic3_f13 isa3_basic3_f13.s
isa3_basic3_f14 isa3_basic3_f14.s
isa3_basic3_f15 isa3_basic3_f15.s
isa3_basic3_f16 isa3_basic3_f16.s
isa3_basic3_f17 isa3_basic3_f17.s
isa3_basic3_f18 isa3_basic3_f18.s
isa3_basic3_f19 isa3_basic3_f19.s
isa3_window3_f0 isa3_window3_f0.s
isa3_window3_f1 isa3_window3_f1.s
isa3_window3_f2 isa3_window3_f2.s
isa3_window3_f3 isa3_window3_f3.s
isa3_window3_f4 isa3_window3_f4.s
isa3_window3_f5 isa3_window3_f5.s
isa3_window3_f6 isa3_window3_f6.s
isa3_window3_f7 isa3_window3_f7.s
isa3_window3_f8 isa3_window3_f8.s
isa3_window3_f9 isa3_window3_f9.s
isa3_window3_f10 isa3_window3_f10.s
isa3_window3_f11 isa3_window3_f11.s
isa3_window3_f12 isa3_window3_f12.s
isa3_window3_f13 isa3_window3_f13.s
isa3_window3_f14 isa3_window3_f14.s
isa3_window3_f15 isa3_window3_f15.s
isa3_window3_f16 isa3_window3_f16.s
isa3_window3_f17 isa3_window3_f17.s
isa3_window3_f18 isa3_window3_f18.s
isa3_window3_f19 isa3_window3_f19.s
isa3_fsr3_f1 isa3_fsr3_f1.s
isa3_fsr3_f2 isa3_fsr3_f2.s
isa3_fsr3_f3 isa3_fsr3_f3.s
isa3_fsr3_f4 isa3_fsr3_f4.s
isa3_fsr3_f5 isa3_fsr3_f5.s
isa3_fsr3_f6 isa3_fsr3_f6.s
isa3_fsr3_f8 isa3_fsr3_f8.s
isa3_fsr3_f9 isa3_fsr3_f9.s
isa3_fsr3_f10 isa3_fsr3_f10.s
isa3_fsr3_f11 isa3_fsr3_f11.s
isa3_fsr3_f12 isa3_fsr3_f12.s
isa3_fsr3_f13 isa3_fsr3_f13.s
isa3_fsr3_f14 isa3_fsr3_f14.s
isa3_fsr3_f15 isa3_fsr3_f15.s
isa3_fsr3_f16 isa3_fsr3_f16.s
isa3_fsr3_f17 isa3_fsr3_f17.s
isa3_fsr3_f18 isa3_fsr3_f18.s
isa3_asr_pr_hpr_f1 isa3_asr_pr_hpr_f1.s
isa3_asr_pr_hpr_f2 isa3_asr_pr_hpr_f2.s
isa3_asr_pr_hpr_f3 isa3_asr_pr_hpr_f3.s
isa3_asr_pr_hpr_f4 isa3_asr_pr_hpr_f4.s
isa3_asr_pr_hpr_f5 isa3_asr_pr_hpr_f5.s
isa3_asr_pr_hpr_f6 isa3_asr_pr_hpr_f6.s
isa3_asr_pr_hpr_f7 isa3_asr_pr_hpr_f7.s
<runargs -vcs_run_args=+thread=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
isa3_basic_idtlb1 isa3_basic_idtlb1.s
isa3_basic_idtlb1_nohw isa3_basic_idtlb1.s -midas_args=-DNOHWTW
isa3_basic_idtlb2 isa3_basic_idtlb2.s
isa3_basic_idtlb3 isa3_basic_idtlb3.s
isa3_basic_idtlb4 isa3_basic_idtlb4.s
isa3_basic_idtlb4_nohw isa3_basic_idtlb4.s -midas_args=-DNOHWTW
isa3_basic_idtlb5 isa3_basic_idtlb5.s
isa3_basic_idtlb6 isa3_basic_idtlb6.s
isa3_basic_dtlb1 isa3_basic_dtlb1.s
isa3_basic_idtlb6_nohw isa3_basic_idtlb6.s -midas_args=-DNOHWTW
isa3_basic_dtlb1_nohw isa3_basic_dtlb1.s -midas_args=-DNOHWTW
isa3_mmu_f1 isa3_mmu_f1.s
isa3_mmu_f2 isa3_mmu_f2.s
isa3_scratchpad_f1 isa3_scratchpad_f1.s
isa3_scratchpad_f2 isa3_scratchpad_f2.s
isa3_mmu_21_52_f1 isa3_mmu_21_52_f1.s
isa3_mmu_htw_4v_phy isa3_mmu_htw_0.s -vcs_run_args=+thread=all
isa3_mmu_htw_4v_real isa3_mmu_htw_3.s -vcs_run_args=+thread=all
isa3_flushw_fc0 isa3_flushw_fc0.s
isa3_basic0_f0 isa3_basic0_f0.s
isa3_fsr0_f0 isa3_fsr0_f0.s
isa3_window0_f0 isa3_window0_f0.s
spc2_hboot_test spc2_hboot_test.s
spc_shutdown spc_shutdown.s
isa3_basic3_f0 isa3_basic3_f0.s
isa3_basic3_f1 isa3_basic3_f1.s
isa3_basic3_f2 isa3_basic3_f2.s
isa3_basic3_f3 isa3_basic3_f3.s
isa3_basic3_f5 isa3_basic3_f5.s
isa3_basic3_f6 isa3_basic3_f6.s
isa3_basic3_f7 isa3_basic3_f7.s
isa3_basic3_f8 isa3_basic3_f8.s
isa3_basic3_f10 isa3_basic3_f10.s
isa3_basic3_f11 isa3_basic3_f11.s
isa3_basic3_f12 isa3_basic3_f12.s
isa3_basic3_f13 isa3_basic3_f13.s
isa3_basic3_f14 isa3_basic3_f14.s
isa3_basic3_f15 isa3_basic3_f15.s
isa3_basic3_f16 isa3_basic3_f16.s
isa3_basic3_f17 isa3_basic3_f17.s
isa3_basic3_f18 isa3_basic3_f18.s
isa3_basic3_f19 isa3_basic3_f19.s
isa3_window3_f0 isa3_window3_f0.s
isa3_window3_f1 isa3_window3_f1.s
isa3_window3_f2 isa3_window3_f2.s
isa3_window3_f3 isa3_window3_f3.s
isa3_window3_f4 isa3_window3_f4.s
isa3_window3_f5 isa3_window3_f5.s
isa3_window3_f6 isa3_window3_f6.s
isa3_window3_f7 isa3_window3_f7.s
isa3_window3_f8 isa3_window3_f8.s
isa3_window3_f9 isa3_window3_f9.s
isa3_window3_f10 isa3_window3_f10.s
isa3_window3_f11 isa3_window3_f11.s
isa3_window3_f12 isa3_window3_f12.s
isa3_window3_f13 isa3_window3_f13.s
isa3_window3_f14 isa3_window3_f14.s
isa3_window3_f15 isa3_window3_f15.s
isa3_window3_f16 isa3_window3_f16.s
isa3_window3_f17 isa3_window3_f17.s
isa3_window3_f18 isa3_window3_f18.s
isa3_window3_f19 isa3_window3_f19.s
isa3_fsr3_f1 isa3_fsr3_f1.s
isa3_fsr3_f2 isa3_fsr3_f2.s
isa3_fsr3_f3 isa3_fsr3_f3.s
isa3_fsr3_f4 isa3_fsr3_f4.s
isa3_fsr3_f5 isa3_fsr3_f5.s
isa3_fsr3_f6 isa3_fsr3_f6.s
isa3_fsr3_f8 isa3_fsr3_f8.s
isa3_fsr3_f9 isa3_fsr3_f9.s
isa3_fsr3_f10 isa3_fsr3_f10.s
isa3_fsr3_f11 isa3_fsr3_f11.s
isa3_fsr3_f12 isa3_fsr3_f12.s
isa3_fsr3_f13 isa3_fsr3_f13.s
isa3_fsr3_f14 isa3_fsr3_f14.s
isa3_fsr3_f15 isa3_fsr3_f15.s
isa3_fsr3_f16 isa3_fsr3_f16.s
isa3_fsr3_f17 isa3_fsr3_f17.s
isa3_fsr3_f18 isa3_fsr3_f18.s
isa3_asr_pr_hpr_f1 isa3_asr_pr_hpr_f1.s
isa3_asr_pr_hpr_f2 isa3_asr_pr_hpr_f2.s
isa3_asr_pr_hpr_f3 isa3_asr_pr_hpr_f3.s
isa3_asr_pr_hpr_f4 isa3_asr_pr_hpr_f4.s
isa3_asr_pr_hpr_f5 isa3_asr_pr_hpr_f5.s
isa3_asr_pr_hpr_f6 isa3_asr_pr_hpr_f6.s
isa3_asr_pr_hpr_f7 isa3_asr_pr_hpr_f7.s
<runargs -vcs_run_args=+thread=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
isa3_basic_idtlb1 isa3_basic_idtlb1.s
isa3_basic_idtlb1_nohw isa3_basic_idtlb1.s -midas_args=-DNOHWTW
isa3_basic_idtlb2 isa3_basic_idtlb2.s
isa3_basic_idtlb3 isa3_basic_idtlb3.s
isa3_basic_idtlb4 isa3_basic_idtlb4.s
isa3_basic_idtlb4_nohw isa3_basic_idtlb4.s -midas_args=-DNOHWTW
isa3_basic_idtlb5 isa3_basic_idtlb5.s
isa3_basic_idtlb6 isa3_basic_idtlb6.s
isa3_basic_dtlb1 isa3_basic_dtlb1.s
isa3_basic_idtlb6_nohw isa3_basic_idtlb6.s -midas_args=-DNOHWTW
isa3_basic_dtlb1_nohw isa3_basic_dtlb1.s -midas_args=-DNOHWTW
isa3_mmu_f1 isa3_mmu_f1.s
isa3_mmu_f2 isa3_mmu_f2.s
isa3_scratchpad_f1 isa3_scratchpad_f1.s
isa3_scratchpad_f2 isa3_scratchpad_f2.s
isa3_mmu_21_52_f1 isa3_mmu_21_52_f1.s
isa3_mmu_htw_4v_phy isa3_mmu_htw_0.s -vcs_run_args=+thread=all
isa3_mmu_htw_4v_real isa3_mmu_htw_3.s -vcs_run_args=+thread=all
isa3_flushw_fc0 isa3_flushw_fc0.s
isa3_basic0_f0 isa3_basic0_f0.s
isa3_fsr0_f0 isa3_fsr0_f0.s
isa3_window0_f0 isa3_window0_f0.s
isa3_va_watchpoint isa3_va_watchpoint.s
isa3_pa_watchpoint isa3_pa_watchpoint.s
isa3_1215htraps1 isa3_1215htraps1.s
isa3_privileged_action isa3_privileged_action.s
isa3_fdacc_protection isa3_fdacc_protection.s
spc_trans_test0 spc_trans_test0.s
isa3_align_trap isa3_align_trap.s
isa3_core_id isa3_core_id.s -nosas
isa3_fp_disable_1215_0x20 isa3_fp_disable_1215_0x20.s -sas
isa3_fp_excIeee_1215_0x21 isa3_fp_excIeee_1215_0x21.s -sas
isa3_fp_excOther_1215_0x22 isa3_fp_excOther_1215_0x22.s -sas
isa3_int_div0_1215_0x28 isa3_int_div0_1215_0x28.s -sas
// isa3_mod_arith_int_1215_0x3d isa3_mod_arith_int_1215_0x3d.s -nosas
isa3_1215hsysmatrap isa3_1215hsysmatrap.s
traps_34_35_36 traps_34_35_36.s
traps_save_restore traps_save_restore.s
isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -vcs_run_args=+thread=1
isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -vcs_run_args=+thread=ff
isa3_1215ivtrap isa3_1215ivtrap.s -vcs_run_args=+thread=ff
isa3_trap_0x30 isa3_trap_0x30.s
isa3_trap_0x3e isa3_trap_0x3e.s
isa3_trap_0x3f isa3_trap_0x3f.s
isa3_trap_0x8 isa3_trap_0x8.s
isa3_mt_hwtw1 isa3_mt_hwtw1.s -vcs_run_args=+thread=all
isa3_xir_121503 isa3_xir_121503.s -vcs_run_args=+thread=all -vcs_run_args=+intr_en=all -vcs_run_args=+intr_vect=3 -vcs_run_args=+intr_type=1 -vcs_run_args=+intr_wait=3000 -vcs_run_args=+intr_delay=100 -vcs_run_args=+lsu_mon_off
isa3_intlevel_121503 isa3_intlevel_121503.s -vcs_run_args=+thread=all
isa3_mondo_121503 isa3_mondo_121503.s -vcs_run_args=+thread=all
tsotool_1t_75971 tsotool_1t_75971.s -midas_args=-allow_tsb_conflicts
<runargs -nosas -midas_args=-DNOPMUENABLE>
isa3_pmu_e2_t1 isa3_pmu_e2_t1.s
isa3_pmu_imiss_idle isa3_pmu_imiss_idle.s
isa3_pmu_int15 isa3_pmu_int15.s
isa3_pmu_cpu_ldst isa3_pmu_cpu_ldst.s
isa3_pmu_dmiss_idle isa3_pmu_dmiss_idle.s
isa3_pmu_other isa3_pmu_other.s
<runargs -vcs_run_args=+TIMEOUT=500000 -vcs_run_args=+skt_timeout=500000 -max_cycle=+5000000 -rtl_timeout=5000000>
pmu_ccx_sel5_0x04_thAll pmu_ccx_sel5_0x04_thAll.s -vcs_run_args=+thread=ff
pmu_ccx_sel5_0x10_thAll pmu_ccx_sel5_0x10_thAll.s -vcs_run_args=+thread=ff
itlbMiss0 itlbSl3.pal -vcs_run_args=+thread=01
itlbMiss1 itlbSl3.pal -vcs_run_args=+thread=02
itlbMiss2 itlbSl3.pal -vcs_run_args=+thread=04
itlbMiss3 itlbSl3.pal -vcs_run_args=+thread=08
itlbMiss4 itlbSl3.pal -vcs_run_args=+thread=10
itlbMiss5 itlbSl3.pal -vcs_run_args=+thread=20
itlbMiss6 itlbSl3.pal -vcs_run_args=+thread=40
itlbMiss7 itlbSl3.pal -vcs_run_args=+thread=80
dtlbMiss0 dtlbSl3.pal -vcs_run_args=+thread=01
dtlbMiss1 dtlbSl3.pal -vcs_run_args=+thread=02
dtlbMiss2 dtlbSl3.pal -vcs_run_args=+thread=04
dtlbMiss3 dtlbSl3.pal -vcs_run_args=+thread=08
dtlbMiss4 dtlbSl3.pal -vcs_run_args=+thread=10
dtlbMiss5 dtlbSl3.pal -vcs_run_args=+thread=20
dtlbMiss6 dtlbSl3.pal -vcs_run_args=+thread=40
dtlbMiss7 dtlbSl3.pal -vcs_run_args=+thread=80
itlbMissLoOv0 itlbSl3OvL.pal -vcs_run_args=+thread=01
itlbMissLoOv1 itlbSl3OvL.pal -vcs_run_args=+thread=02
itlbMissLoOv2 itlbSl3OvL.pal -vcs_run_args=+thread=04
itlbMissLoOv3 itlbSl3OvL.pal -vcs_run_args=+thread=08
itlbMissLoOv4 itlbSl3OvL.pal -vcs_run_args=+thread=10
itlbMissLoOv5 itlbSl3OvL.pal -vcs_run_args=+thread=20
itlbMissLoOv6 itlbSl3OvL.pal -vcs_run_args=+thread=40
itlbMissLoOv7 itlbSl3OvL.pal -vcs_run_args=+thread=80
itlbMissHiOv0 itlbSl3OvH.pal -vcs_run_args=+thread=01
itlbMissHiOv1 itlbSl3OvH.pal -vcs_run_args=+thread=02
itlbMissHiOv2 itlbSl3OvH.pal -vcs_run_args=+thread=04
itlbMissHiOv3 itlbSl3OvH.pal -vcs_run_args=+thread=08
itlbMissHiOv4 itlbSl3OvH.pal -vcs_run_args=+thread=10
itlbMissHiOv5 itlbSl3OvH.pal -vcs_run_args=+thread=20
itlbMissHiOv6 itlbSl3OvH.pal -vcs_run_args=+thread=40
itlbMissHiOv7 itlbSl3OvH.pal -vcs_run_args=+thread=80
dtlbMissLoOv0 dtlbSl3OvL.pal -vcs_run_args=+thread=01
dtlbMissLoOv1 dtlbSl3OvL.pal -vcs_run_args=+thread=02
dtlbMissLoOv2 dtlbSl3OvL.pal -vcs_run_args=+thread=04
dtlbMissLoOv3 dtlbSl3OvL.pal -vcs_run_args=+thread=08
dtlbMissLoOv4 dtlbSl3OvL.pal -vcs_run_args=+thread=10
dtlbMissLoOv5 dtlbSl3OvL.pal -vcs_run_args=+thread=20
dtlbMissLoOv6 dtlbSl3OvL.pal -vcs_run_args=+thread=40
dtlbMissLoOv7 dtlbSl3OvL.pal -vcs_run_args=+thread=80
dtlbMissHiOv0 dtlbSl3OvH.pal -vcs_run_args=+thread=01
dtlbMissHiOv1 dtlbSl3OvH.pal -vcs_run_args=+thread=02
dtlbMissHiOv2 dtlbSl3OvH.pal -vcs_run_args=+thread=04
dtlbMissHiOv3 dtlbSl3OvH.pal -vcs_run_args=+thread=08
dtlbMissHiOv4 dtlbSl3OvH.pal -vcs_run_args=+thread=10
dtlbMissHiOv5 dtlbSl3OvH.pal -vcs_run_args=+thread=20
dtlbMissHiOv6 dtlbSl3OvH.pal -vcs_run_args=+thread=40
dtlbMissHiOv7 dtlbSl3OvH.pal -vcs_run_args=+thread=80
icacheMiss0 icacheMissSl3.s -vcs_run_args=+thread=01
icacheMiss1 icacheMissSl3.s -vcs_run_args=+thread=02
icacheMiss2 icacheMissSl3.s -vcs_run_args=+thread=04
icacheMiss3 icacheMissSl3.s -vcs_run_args=+thread=08
icacheMiss4 icacheMissSl3.s -vcs_run_args=+thread=10
icacheMiss5 icacheMissSl3.s -vcs_run_args=+thread=20
icacheMiss6 icacheMissSl3.s -vcs_run_args=+thread=40
// icacheMiss7 icacheMissSl3.s -vcs_run_args=+thread=80
dcacheMiss0 dcacheMissSl3.s -vcs_run_args=+thread=01
dcacheMiss1 dcacheMissSl3.s -vcs_run_args=+thread=02
dcacheMiss2 dcacheMissSl3.s -vcs_run_args=+thread=04
dcacheMiss3 dcacheMissSl3.s -vcs_run_args=+thread=08
dcacheMiss4 dcacheMissSl3.s -vcs_run_args=+thread=10
dcacheMiss5 dcacheMissSl3.s -vcs_run_args=+thread=20
dcacheMiss6 dcacheMissSl3.s -vcs_run_args=+thread=40
dcacheMiss7 dcacheMissSl3.s -vcs_run_args=+thread=80
dcacheOvH0 dcacheOvH.s -vcs_run_args=+thread=01
dcacheOvH1 dcacheOvH.s -vcs_run_args=+thread=02
dcacheOvH2 dcacheOvH.s -vcs_run_args=+thread=04
dcacheOvH3 dcacheOvH.s -vcs_run_args=+thread=08
dcacheOvH4 dcacheOvH.s -vcs_run_args=+thread=10
dcacheOvH5 dcacheOvH.s -vcs_run_args=+thread=20
dcacheOvH6 dcacheOvH.s -vcs_run_args=+thread=40
dcacheOvH7 dcacheOvH.s -vcs_run_args=+thread=80
dcacheOvL0 dcacheOvL.s -vcs_run_args=+thread=01
dcacheOvL1 dcacheOvL.s -vcs_run_args=+thread=02
dcacheOvL2 dcacheOvL.s -vcs_run_args=+thread=04
dcacheOvL3 dcacheOvL.s -vcs_run_args=+thread=08
dcacheOvL4 dcacheOvL.s -vcs_run_args=+thread=10
dcacheOvL5 dcacheOvL.s -vcs_run_args=+thread=20
dcacheOvL6 dcacheOvL.s -vcs_run_args=+thread=40
dcacheOvL7 dcacheOvL.s -vcs_run_args=+thread=80
dcacheMissL20 dcacheL2MissSl3.s -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1 -nosas
dcacheMissL21 dcacheL2MissSl3.s -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
dcacheMissL22 dcacheL2MissSl3.s -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
dcacheMissL23 dcacheL2MissSl3.s -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
dcacheMissL24 dcacheL2MissSl3.s -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
dcacheMissL25 dcacheL2MissSl3.s -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
dcacheMissL26 dcacheL2MissSl3.s -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
dcacheMissL27 dcacheL2MissSl3.s -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1
icMiss0 icMissL2Miss.pal -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1
icMiss1 icMissL2Miss.pal -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
icMiss2 icMissL2Miss.pal -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
icMiss3 icMissL2Miss.pal -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
icMiss4 icMissL2Miss.pal -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
icMiss5 icMissL2Miss.pal -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
icMiss6 icMissL2Miss.pal -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
icMiss7 icMissL2Miss.pal -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1
pmuAtomic pmuAtomic.s -vcs_run_args=+thread=all
pmuOverflowBit ovBitTest.pal -vcs_run_args=+thread=all
serviceLevel4 pmu_sl4_mask_n2.pal -vcs_run_args=+l2miss_type=1 -nosas
<fgu_traps name=fgu_traps>
fgu_ieee_traps_01 fgu_ieee_traps_01.s
fgu_ieee_traps_02 fgu_ieee_traps_02.s
fgu_ieee_traps_03 fgu_ieee_traps_03.s
fgu_ieee_traps_04 fgu_ieee_traps_04.s
fgu_ieee_traps_05 fgu_ieee_traps_05.s
fgu_ieee_traps_06 fgu_ieee_traps_06.s
fgu_ieee_traps_07 fgu_ieee_traps_07.s
fgu_ieee_traps_08 fgu_ieee_traps_08.s
fgu_ieee_traps_09 fgu_ieee_traps_09.s
fgu_ieee_traps_10 fgu_ieee_traps_10.s
fgu_idiv_traps_01 fgu_idiv_traps_01.s
fgu_idiv_traps_02 fgu_idiv_traps_02.s
fgu_idiv_traps_03 fgu_idiv_traps_03.s
fgu_idiv_traps_04 fgu_idiv_traps_04.s
fgu_idiv_traps_05 fgu_idiv_traps_05.s
fgu_idiv_traps_06 fgu_idiv_traps_06.s
fgu_idiv_traps_07 fgu_idiv_traps_07.s
fgu_idiv_traps_08 fgu_idiv_traps_08.s
fgu_idiv_traps_09 fgu_idiv_traps_09.s
fgu_idiv_traps_10 fgu_idiv_traps_10.s
fgu_siam_traps_21 fgu_siam_traps_21.s
fgu_stfsr_traps_22 fgu_stfsr_traps_22.s
fgu_stxfsr_traps_23 fgu_stxfsr_traps_23.s
fgu_ieee_traps_24 fgu_ieee_traps_24.s
fgu_ieee_traps_25 fgu_ieee_traps_25.s
fgu_ieee_traps_26 fgu_ieee_traps_26.s
fgu_ieee_traps_27 fgu_ieee_traps_27.s
fgu_ieee_traps_28 fgu_ieee_traps_28.s
fgu_ieee_traps_29 fgu_ieee_traps_29.s
fgu_ieee_traps_30 fgu_ieee_traps_30.s
<runargs -vcs_run_args=+thread=01>
<exu_ported name=exu_ported>
exu_irf_global_n2 exu_irf_global_n2.s
exu_irf_local_n2 exu_irf_local_n2.s
exu_logical_n2 exu_logical_n2.s
exu_move_n2 exu_move_n2.s
exu_muldiv_n2 exu_muldiv_n2.s
exu_shift_n2 exu_shift_n2.s
exu_win_traps_n2 exu_win_traps_n2.s
fp_addsub0_n2 fp_addsub0_n2.s
fp_fadd_norm_sv_n2 fp_fadd_norm_sv_n2.s
fp_fdiv_man_sv_n2 fp_fdiv_man_sv_n2.s
fp_fprs0_n2 fp_fprs0_n2.s
fp_ieee_flags_n2 fp_ieee_flags_n2.s
fp_movixcc0_n2 fp_movixcc0_n2.s
fp_movixcc1_n2 fp_movixcc1_n2.s
fp_movixcc2_n2 fp_movixcc2_n2.s
fp_muldiv0_a_n2 fp_muldiv0_a_n2.s
fp_muldiv0_n2 fp_muldiv0_n2.s
fp_sticky_bits_n2 fp_sticky_bits_n2.s
ffu_blkst_stall_n2 ffu_blkst_stall_n2.s
ffu_faligndata_n2 ffu_faligndata_n2.s
ffu_fpaddsub_n2 ffu_fpaddsub_n2.s
ffu_fplogic_n2 ffu_fplogic_n2.s
ffu_fpreg_rw_n2 ffu_fpreg_rw_n2.s
ffu_fsr_gsr_n2 ffu_fsr_gsr_n2.s
ffu_fsr_tem_n2 ffu_fsr_tem_n2.s
ffu_siam_n2 ffu_siam_n2.s
isa1_noldst_fc_0513 isa1_noldst_fc_0513.s
lsu_align_raw lsu_align_raw.s
lsu_storeraw_fc_0 lsu_storeraw_fc_0.s
spc_basic_isa2_fc_0 spc_basic_isa2_fc_0.s
spc_mul_ldst spc_mul_ldst.s
ldst_atomic ldst_atomic.s
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
ifu_basic_bicc ifu_basic_bicc.s
ifu_basic_br1 ifu_basic_br1.s
ifu_basic_br2 ifu_basic_br2.s
ifu_basic_br ifu_basic_br.s
ifu_basic_ex1 ifu_basic_ex1.s
ifu_basic_ex_raw ifu_basic_ex_raw.s
ifu_basic_mov ifu_basic_mov.s
ifu_basic_branch ifu_basic_branch.s
lsu_cpqfill lsu_cpqfill.s
spc_pmu_asr spc_pmu_asr.s
spc_tlu_rml_asr spc_tlu_rml_asr.s
<isa1_nospec name=isa1_nospec>
<runargs -midas_args=-DNOSPEC_EN>
ifu_basic_x ifu_basic_x.s
ifu_basic_branch ifu_basic_branch.s
isa1_noldst_fc_0513 isa1_noldst_fc_0513.s
spc_basic_isa2_fc_0 spc_basic_isa2_fc_0.s
////////////////////////////////////////////////////////////////////////////////////////////////////
projects / OpenSPARC-T2-DV / blob