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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / fc / Fc_MT.diaglist
CommitLineData
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: Fc_MT.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<Fc_MT name=Fc_MT>
36
37
38// ****************************************************************************
39// 10G -> MAC0 -> NIU Tx + Rx.
40// ****************************************************************************
41<fc_ldst_dma>
42
43<runargs -sas >
44<runargs -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 >
45<runargs -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+ORIG_META >
46<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+TX_TEST >
47<runargs -vcs_run_args=+RX_TEST -vcs_run_args=+no_verilog_finish >
48<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
49<runargs -midas_args=-DRX_TEST -midas_args=-DTX_TEST >
50<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
51
52<runargs -midas_args=-DTHREAD_COUNT=2 >
53<runargs -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3 >
54<runargs -midas_args=-DTHREAD_0_DIAG=niu/NIU_Tx/FcNiuBasicTx.s >
55<runargs -midas_args=-DTHREAD_1_DIAG=niu/NIU_Rx/FcNiuBasicRx_sweep1.s >
56<runargs -midas_args=-DMAIN_PAGE_HV_ALSO >
57
58Fc_MT_NIUTx_NIURx mt_template.s
59
60</runargs>
61</runargs>
62</runargs>
63</runargs>
64</runargs>
65</runargs>
66</runargs>
67</runargs>
68</runargs>
69</runargs>
70</runargs>
71</runargs>
72</runargs>
73
74</fc_ldst_dma>
75// ****************************************************************************
76// 10G -> MAC0 -> NIU Tx + PEU PCIeDMAWr
77// ****************************************************************************
78
79<runargs -sas >
80<runargs -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 >
81<runargs -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+ORIG_META >
82<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+TX_TEST >
83<runargs -vcs_run_args=+PEU_TEST >
84<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
85<runargs -midas_args=-DTX_TEST >
86<runargs -midas_args=-DENABLE_PCIE_LINK_TRAINING -midas_args=-DDMA_DATA_ADDR=0x0000000123456700 >
87<runargs -midas_args=-DDMA_DATA_BYP_ADDR1=0xfffc000123456700 -midas_args=-DDMA_DATA_BYP_ADDR2=0xfffc000123456780 >
88<runargs -midas_args=-DDMA_DATA_BYP_ADDR3=0xfffc000123456800 >
89
90<runargs -midas_args=-DTHREAD_COUNT=2 >
91<runargs -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3 >
92<runargs -midas_args=-DTHREAD_0_DIAG=niu/NIU_Tx/FcNiuBasicTx.s >
93<runargs -midas_args=-DTHREAD_1_DIAG=peu/PCIeDMAWr.s >
94<runargs -midas_args=-DMAIN_PAGE_HV_ALSO >
95
96Fc_MT_NIUTx_PEUDMAWr mt_template.s
97
98</runargs>
99</runargs>
100</runargs>
101</runargs>
102</runargs>
103</runargs>
104</runargs>
105</runargs>
106</runargs>
107</runargs>
108</runargs>
109</runargs>
110</runargs>
111</runargs>
112</runargs>
113
114// ****************************************************************************
115// 10G -> MAC0 -> NIU Tx + NIU Rx + Memory.
116// ****************************************************************************
117
118// <runargs -sas >
119// <runargs -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 >
120// <runargs -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+ORIG_META >
121// <runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+TX_TEST >
122// <runargs -vcs_run_args=+RX_TEST -vcs_run_args=+no_verilog_finish >
123// <runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
124// <runargs -midas_args=-DRX_TEST -midas_args=-DTX_TEST >
125// <runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
126//
127// <runargs -midas_args=-DTHREAD_COUNT=3 >
128// <runargs -midas_args=-DCMP_THREAD_START=0x7 -finish_mask=7 >
129// <runargs -midas_args=-DTHREAD_0_DIAG=niu/NIU_Tx/FcNiuBasicTx.s >
130// <runargs -midas_args=-DTHREAD_1_DIAG=niu/NIU_Rx/FcNiuBasicRx_sweep1.s >
131// <runargs -midas_args=-DTHREAD_2_DIAG=arch/prm/memory/memop_word_byte_mask.s >
132// <runargs -midas_args=-DMAIN_PAGE_HV_ALSO >
133//
134// Fc_MT_NIUTx_NIURx_Mem mt_template.s
135//
136// </runargs>
137// </runargs>
138// </runargs>
139// </runargs>
140// </runargs>
141// </runargs>
142// </runargs>
143// </runargs>
144// </runargs>
145// </runargs>
146// </runargs>
147// </runargs>
148// </runargs>
149// </runargs>
150// ****************************************************************************
151// 10G -> MAC0 -> NIU Tx + Rx.
152// ****************************************************************************
153<runargs -sas >
154<runargs -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 >
155<runargs -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+ORIG_META >
156<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+TX_TEST >
157<runargs -vcs_run_args=+RX_TEST -vcs_run_args=+no_verilog_finish >
158<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
159<runargs -midas_args=-DRX_TEST -midas_args=-DTX_TEST >
160<runargs -vcs_run_args=+USE_RANDOM_ADDRESS>
161<runargs -vcs_run_args=+RXWRITE_TIMEOUT=20000>
162<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
163
164<runargs -midas_args=-DTHREAD_COUNT=2 >
165<runargs -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3 >
166
167//#ifndef NIU_SYSTEMC_T2
168Fc_MT_NIUTx_NIURx_rand txrxrand_1.s -midas_args=-DRXMAC_PKTCNT=0x60 -vcs_run_args=+RXMAC_PKTCNT=96
169Fc_MT_NIU_wrm txrxrand_wrm.s -midas_args=-DRXMAC_PKTCNT=0x30 -vcs_run_args=+RXMAC_PKTCNT=48
170Fc_MT_NIU_wrm_macp txrxrand_wrm_macp.s -midas_args=-DRXMAC_PKTCNT=0x30 -vcs_run_args=+RXMAC_PKTCNT=48
171//#endif
172
173</runargs>
174</runargs>
175</runargs>
176</runargs>
177</runargs>
178</runargs>
179</runargs>
180</runargs>
181</runargs>
182</runargs>
183</runargs>
184</runargs>
185
186</Fc_MT>
Full OpenSPARC design & verification tarball including full HDL.