projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / fc / fc_dbp.diaglist
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_dbp.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<sys(tcu_no_tck) name=sys(tcu_no_tck)>
36<runargs -midas_args=-DINC_SOC_ERR_TRAPS -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off >
37 tcu_csr_regs_rw tcu_csr_regs_rw.s -nosas
38 tcu_regs_asi tcu_regs_asi.s
39 tcu_regs_l2 tcu_regs_l2.s
40 tcu_regs_peu tcu_regs_peu.s
41 tcu_regs_soc tcu_regs_soc.s
42 tcu_regs_bist tcu_regs_bist.s -nosas
43</runargs>
44
45<runargs -midas_args=-DINC_SOC_ERR_TRAPS -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+MCU_REG_DEFAULT_VAL -vcs_run_args=+NO_MCU_CSR_SLAM>
46 tcu_regs_dram tcu_regs_dram.s -nofast_boot
47 tcu_regs_dram_2 tcu_regs_dram_2.s -nofast_boot
48 tcu_regs_dram_piu tcu_regs_dram_piu.s -nofast_boot
49</runargs>
50
51</sys(tcu_no_tck)>
52
53
54///////////////////////////////////////////////////////////////////////////////
55///////////////////////////////////////////////////////////////////////////////
56
57<sys(dbg) name=sys(dbg)>
58<runargs -vcs_run_args=-DL2_7 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+50000 -nosas -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+DISABLE_L2_CHECKER -vcs_run_args=+BOOT_CODE_FINISH=13000000 -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+PEU_TEST>
59Debug_Event_Mcu_Ctl2 Debug_Event_Mcu2.s
60</runargs>
61
62<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off>
63Debug_Event_L2_PABank0 Debug_Event_L2PaBank.s -midas_args=-DMCU0
64Debug_Event_L2_PABank2 Debug_Event_L2PaBank.s -midas_args=-DMCU1
65Debug_Event_L2_PABank4 Debug_Event_L2PaBank.s -midas_args=-DMCU2
66Debug_Event_L2_PABank6 Debug_Event_L2PaBank.s -midas_args=-DMCU3
67Debug_Event_L2_PABank1 Debug_Event_L2PaBankOdd.s -midas_args=-DMCU0
68Debug_Event_L2_PABank3 Debug_Event_L2PaBankOdd.s -midas_args=-DMCU1
69Debug_Event_L2_PABank5 Debug_Event_L2PaBankOdd.s -midas_args=-DMCU2
70Debug_Event_L2_PABank7 Debug_Event_L2PaBankOdd.s -midas_args=-DMCU3
71</runargs>
72
73
74
75
76<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_L2_CHECKER>
77Debug_Event_Mcu_Ctl0 Debug_Event_Mcu.s -midas_args=-DMCU0
78Debug_Event_Mcu_Ctl1 Debug_Event_Mcu.s -midas_args=-DMCU1
79Debug_Event_Mcu_Ctl2 Debug_Event_Mcu.s -midas_args=-DMCU2
80Debug_Event_Mcu_Ctl3 Debug_Event_Mcu.s -midas_args=-DMCU3
81</runargs>
82
83<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_L2_CHECKER>
84Debug_Event_L2Bank0 Debug_Event_L2.s -midas_args=-DL2_0 -midas_args=-DMCU0
85Debug_Event_L2Bank2 Debug_Event_L2.s -midas_args=-DL2_2 -midas_args=-DMCU1
86Debug_Event_L2Bank4 Debug_Event_L2.s -midas_args=-DL2_4 -midas_args=-DMCU2
87Debug_Event_L2Bank6 Debug_Event_L2.s -midas_args=-DL2_6 -midas_args=-DMCU3
88</runargs>
89
90
91<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_L2_CHECKER>
92Debug_Event_L2Bank1 Debug_Event_L2Odd.s -midas_args=-DMCU0
93Debug_Event_L2Bank3 Debug_Event_L2Odd.s -midas_args=-DMCU1
94Debug_Event_L2Bank5 Debug_Event_L2Odd.s -midas_args=-DMCU2
95Debug_Event_L2Bank7 Debug_Event_L2Odd.s -midas_args=-DMCU3
96</runargs>
97
98
99
100
101<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+DISABLE_L2_CHECKER -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+l2cpx_errmon_off -max_cycle=+50000 -nosas -vcs_run_args=+l2esr_mon_off -midas_args=-DL2_0 -vcs_run_args=+ios_0in_ras_chk_off>
102Debug_CoreSoc_Soc Debug_CoreSoc_Soc.s
103Debug_Tester_Soc Debug_Tester_Soc.s
104Debug_Event_L2pa Debug_Event_L2_Pa.s
105</runargs>
106
107<runargs -vcs_run_args=+PEU_TEST -midas_args=-DERR_FIELD=NcuCtagUe -vcs_run_args=+ios_0in_ras_chk_off -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=2>
108Debug_Event_Soc Debug_Event_Soc.s
109</runargs>
110
111<runargs -vcs_run_args=+0in_no_statistics -fast_boot -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -nosas -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+DISABLE_L2_CHECKER -drm_type=rgrs -tg_seed=1 -sas -vcs_run_args=+PEU_TEST>
112Debug_Pciex_Obs Debug_Pciex_Mode.s
113</runargs>
114
115#ifndef FC_NO_NIU_T2
116<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -midas_args=-DMCU1 -vcs_run_args=+ios_0in_ras_chk_off>
117//Debug_Niu_Obs Debug_Niu_Mode.s
118</runargs>
119#endif
120
121<runargs -midas_args=-DERR_FIELD=SiiNiuCtagCe -vcs_run_args=+ios_0in_ras_chk_off -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING -nosas>
122Debug_Quiscen_Mode Debug_Quiscen_Mode.s
123</runargs>
124
125<runargs -midas_args=-DERR_FIELD=SiiNiuCtagCe -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING -vcs_run_args=+ios_0in_ras_chk_off -nosas>
126Debug_Repeatable_Mode Debug_Niu_Repeatable.s
127</runargs>
128
129<runargs -nouse_cdms_iver -vcs_run_args=+0in_no_statistics -fast_boot -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -nosas -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+DISABLE_L2_CHECKER -tg_seed=1 -sas -vcs_run_args=+PEU_TEST>
130Debug_Dmu_Quiscen Debug_Dmu_Quiscen.s
131</runargs>
132
133<runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING -midas_args=-DERR_FIELD=SiiDmuDParity -vcs_run_args=+DISABLE_L2_CHECKER -vcs_run_args=+ios_0in_ras_chk_off>
134Debug_Event_Dmu Debug_Event_Dmu.s
135</runargs>
136
137</sys(dbg)>
Full OpenSPARC design & verification tarball including full HDL.