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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cmp_top.if.vrh | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC_CMP_IF_VRH | |
36 | #define INC_CMP_IF_VRH | |
37 | ||
38 | ||
39 | ||
40 | #include <vera_defines.vrh> | |
41 | #include <defines.vri> | |
42 | ||
43 | #define OUTPUT_SKEW #0 | |
44 | #define INPUT_SKEW #-0 | |
45 | #define OUTPUT_EDGE NHOLD | |
46 | #define INPUT_EDGE NSAMPLE | |
47 | #define BOTH_DIR NSAMPLE NHOLD | |
48 | ||
49 | ||
50 | // interface names MUST be unique to ALL var names in ALL vera code | |
51 | // for NTB. These interface names are global names. Adding '_if' | |
52 | // is a good idea! | |
53 | ||
54 | // This line must be present -- it drives the entire Vera environment. | |
55 | // Ends up in the vshell as vera's SystemClock. Should be the FASTEST clock. | |
56 | // Is used when you do @(posedge CLOCK); | |
57 | // Each interface should still have it's own clock! | |
58 | hdl_node CLOCK "tb_top.SystemClock"; | |
59 | ||
60 | ||
61 | // misc probes | |
62 | interface probe_if { | |
63 | input [7:0] sim_status INPUT_EDGE INPUT_SKEW hdl_node "tb_top.sim_status"; | |
64 | input rst_l INPUT_EDGE INPUT_SKEW hdl_node "tb_top.reset"; | |
65 | //input [7:0] raw_set INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.spc0.lsu.lmc.ld_rawp_disabled_set"; | |
66 | input [63:0] th_check_enable INPUT_EDGE INPUT_SKEW hdl_node "tb_top.verif_args.th_check_enable"; | |
67 | input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0"; | |
68 | ||
69 | input pm INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_pm"; | |
70 | input ba01 INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba01"; | |
71 | input ba23 INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba23"; | |
72 | input ba45 INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba45"; | |
73 | input ba67 INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba67"; | |
74 | ||
75 | output [63:0] gOutOfBoot PHOLD OUTPUT_SKEW hdl_node "tb_top.gOutOfBoot"; | |
76 | ||
77 | // #ifdef CCXDEVBASEBFM_DEBUG | |
78 | // output [1:0] count0 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count0"; | |
79 | // output [1:0] count1 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count1"; | |
80 | // output [1:0] count2 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count2"; | |
81 | // output [1:0] count3 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count3"; | |
82 | // output [1:0] count4 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count4"; | |
83 | // output [1:0] count5 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count5"; | |
84 | // output [1:0] count6 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count6"; | |
85 | // output [1:0] count7 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count7"; | |
86 | // #endif | |
87 | } | |
88 | ||
89 | ||
90 | interface ncu_if { | |
91 | // NCU probes for LDST_sync | |
92 | input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0"; | |
93 | output [39:0] b8_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_pa"; | |
94 | output [145:0] b8_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_pkt"; | |
95 | output [2:0] b8_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_cid"; | |
96 | output b8_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_ctrue"; | |
97 | output b8_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_swap"; | |
98 | } | |
99 | ||
100 | port ldStSync_port { | |
101 | pa; | |
102 | pkt; | |
103 | cid; | |
104 | ctrue; | |
105 | swap; | |
106 | clk; | |
107 | } | |
108 | ||
109 | #ifdef NOL2RTL | |
110 | interface l2_if { | |
111 | // L2 probes for LDST_sync | |
112 | input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0"; | |
113 | ||
114 | #ifndef RTL_NO_BNK01 | |
115 | output [39:0] b0_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_pa"; | |
116 | output [145:0] b0_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_pkt"; | |
117 | output [39:0] b1_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_pa"; | |
118 | output [145:0] b1_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_pkt"; | |
119 | output [2:0] b0_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_cid"; | |
120 | output b0_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_ctrue"; | |
121 | output b0_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_swap"; | |
122 | output [2:0] b1_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_cid"; | |
123 | output b1_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_ctrue"; | |
124 | output b1_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_swap"; | |
125 | #endif | |
126 | ||
127 | #ifndef RTL_NO_BNK23 | |
128 | output [39:0] b2_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_pa"; | |
129 | output [145:0] b2_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_pkt"; | |
130 | output [39:0] b3_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_pa"; | |
131 | output [145:0] b3_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_pkt"; | |
132 | output [2:0] b2_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_cid"; | |
133 | output b2_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_ctrue"; | |
134 | output b2_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_swap"; | |
135 | output [2:0] b3_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_cid"; | |
136 | output b3_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_ctrue"; | |
137 | output b3_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_swap"; | |
138 | #endif | |
139 | ||
140 | #ifndef RTL_NO_BNK45 | |
141 | output [39:0] b4_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_pa"; | |
142 | output [145:0] b4_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_pkt"; | |
143 | output [39:0] b5_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_pa"; | |
144 | output [145:0] b5_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_pkt"; | |
145 | output [2:0] b4_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_cid"; | |
146 | output b4_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_ctrue"; | |
147 | output b4_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_swap"; | |
148 | output [2:0] b5_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_cid"; | |
149 | output b5_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_ctrue"; | |
150 | output b5_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_swap"; | |
151 | #endif | |
152 | ||
153 | #ifndef RTL_NO_BNK67 | |
154 | output [39:0] b6_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_pa"; | |
155 | output [145:0] b6_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_pkt"; | |
156 | output [39:0] b7_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_pa"; | |
157 | output [145:0] b7_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_pkt"; | |
158 | output [2:0] b6_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_cid"; | |
159 | output b6_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_ctrue"; | |
160 | output b6_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_swap"; | |
161 | output [2:0] b7_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_cid"; | |
162 | output b7_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_ctrue"; | |
163 | output b7_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_swap"; | |
164 | #endif | |
165 | ||
166 | } | |
167 | ||
168 | #ifndef RTL_NO_BNK01 | |
169 | bind ldStSync_port ldStSync_bind_b0 { | |
170 | pa l2_if.b0_cpx_pa; | |
171 | pkt l2_if.b0_cpx_pkt; | |
172 | cid l2_if.b0_cpx_cid; | |
173 | ctrue l2_if.b0_cpx_ctrue; | |
174 | swap l2_if.b0_cpx_swap; | |
175 | clk l2_if.clk; | |
176 | } | |
177 | bind ldStSync_port ldStSync_bind_b1 { | |
178 | pa l2_if.b1_cpx_pa; | |
179 | pkt l2_if.b1_cpx_pkt; | |
180 | cid l2_if.b1_cpx_cid; | |
181 | ctrue l2_if.b1_cpx_ctrue; | |
182 | swap l2_if.b1_cpx_swap; | |
183 | clk l2_if.clk; | |
184 | } | |
185 | #endif | |
186 | ||
187 | #ifndef RTL_NO_BNK23 | |
188 | bind ldStSync_port ldStSync_bind_b2 { | |
189 | pa l2_if.b2_cpx_pa; | |
190 | pkt l2_if.b2_cpx_pkt; | |
191 | cid l2_if.b2_cpx_cid; | |
192 | ctrue l2_if.b2_cpx_ctrue; | |
193 | swap l2_if.b2_cpx_swap; | |
194 | clk l2_if.clk; | |
195 | } | |
196 | bind ldStSync_port ldStSync_bind_b3 { | |
197 | pa l2_if.b3_cpx_pa; | |
198 | pkt l2_if.b3_cpx_pkt; | |
199 | cid l2_if.b3_cpx_cid; | |
200 | ctrue l2_if.b3_cpx_ctrue; | |
201 | swap l2_if.b3_cpx_swap; | |
202 | clk l2_if.clk; | |
203 | } | |
204 | #endif | |
205 | ||
206 | #ifndef RTL_NO_BNK45 | |
207 | bind ldStSync_port ldStSync_bind_b4 { | |
208 | pa l2_if.b4_cpx_pa; | |
209 | pkt l2_if.b4_cpx_pkt; | |
210 | cid l2_if.b4_cpx_cid; | |
211 | ctrue l2_if.b4_cpx_ctrue; | |
212 | swap l2_if.b4_cpx_swap; | |
213 | clk l2_if.clk; | |
214 | } | |
215 | bind ldStSync_port ldStSync_bind_b5 { | |
216 | pa l2_if.b5_cpx_pa; | |
217 | pkt l2_if.b5_cpx_pkt; | |
218 | cid l2_if.b5_cpx_cid; | |
219 | ctrue l2_if.b5_cpx_ctrue; | |
220 | swap l2_if.b5_cpx_swap; | |
221 | clk l2_if.clk; | |
222 | } | |
223 | #endif | |
224 | ||
225 | #ifndef RTL_NO_BNK67 | |
226 | bind ldStSync_port ldStSync_bind_b6 { | |
227 | pa l2_if.b6_cpx_pa; | |
228 | pkt l2_if.b6_cpx_pkt; | |
229 | cid l2_if.b6_cpx_cid; | |
230 | ctrue l2_if.b6_cpx_ctrue; | |
231 | swap l2_if.b6_cpx_swap; | |
232 | clk l2_if.clk; | |
233 | } | |
234 | bind ldStSync_port ldStSync_bind_b7 { | |
235 | pa l2_if.b7_cpx_pa; | |
236 | pkt l2_if.b7_cpx_pkt; | |
237 | cid l2_if.b7_cpx_cid; | |
238 | ctrue l2_if.b7_cpx_ctrue; | |
239 | swap l2_if.b7_cpx_swap; | |
240 | clk l2_if.clk; | |
241 | } | |
242 | #endif | |
243 | ||
244 | ||
245 | #endif | |
246 | ||
247 | ||
248 | bind ldStSync_port ldStSync_bind_b8 { | |
249 | pa ncu_if.b8_cpx_pa; | |
250 | pkt ncu_if.b8_cpx_pkt; | |
251 | cid ncu_if.b8_cpx_cid; | |
252 | ctrue ncu_if.b8_cpx_ctrue; | |
253 | swap ncu_if.b8_cpx_swap; | |
254 | clk ncu_if.clk; | |
255 | } | |
256 | ||
257 | port probesPort { | |
258 | th_check_enable; | |
259 | rst_l; | |
260 | pm; | |
261 | ba01; | |
262 | ba23; | |
263 | ba45; | |
264 | ba67; | |
265 | } | |
266 | ||
267 | bind probesPort probesBind { | |
268 | th_check_enable probe_if.th_check_enable; | |
269 | rst_l probe_if.rst_l; | |
270 | pm probe_if.pm; | |
271 | ba01 probe_if.ba01; | |
272 | ba23 probe_if.ba23; | |
273 | ba45 probe_if.ba45; | |
274 | ba67 probe_if.ba67; | |
275 | } | |
276 | ||
277 | ||
278 | ||
279 | #endif |