// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: cmp_top.if.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
#include <vera_defines.vrh>
#define OUTPUT_EDGE NHOLD
#define INPUT_EDGE NSAMPLE
#define BOTH_DIR NSAMPLE NHOLD
// interface names MUST be unique to ALL var names in ALL vera code
// for NTB. These interface names are global names. Adding '_if'
// This line must be present -- it drives the entire Vera environment.
// Ends up in the vshell as vera's SystemClock. Should be the FASTEST clock.
// Is used when you do @(posedge CLOCK);
// Each interface should still have it's own clock!
hdl_node CLOCK "tb_top.SystemClock";
input [7:0] sim_status INPUT_EDGE INPUT_SKEW hdl_node "tb_top.sim_status";
input rst_l INPUT_EDGE INPUT_SKEW hdl_node "tb_top.reset";
//input [7:0] raw_set INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.spc0.lsu.lmc.ld_rawp_disabled_set";
input [63:0] th_check_enable INPUT_EDGE INPUT_SKEW hdl_node "tb_top.verif_args.th_check_enable";
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
input pm INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_pm";
input ba01 INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba01";
input ba23 INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba23";
input ba45 INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba45";
input ba67 INPUT_EDGE INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba67";
output [63:0] gOutOfBoot PHOLD OUTPUT_SKEW hdl_node "tb_top.gOutOfBoot";
// #ifdef CCXDEVBASEBFM_DEBUG
// output [1:0] count0 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count0";
// output [1:0] count1 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count1";
// output [1:0] count2 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count2";
// output [1:0] count3 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count3";
// output [1:0] count4 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count4";
// output [1:0] count5 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count5";
// output [1:0] count6 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count6";
// output [1:0] count7 OUTPUT_EDGE OUTPUT_SKEW hdl_node "tb_top.count7";
// NCU probes for LDST_sync
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
output [39:0] b8_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_pa";
output [145:0] b8_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_pkt";
output [2:0] b8_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_cid";
output b8_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_ctrue";
output b8_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b8_cpx_swap";
// L2 probes for LDST_sync
input clk CLOCK hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
output [39:0] b0_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_pa";
output [145:0] b0_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_pkt";
output [39:0] b1_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_pa";
output [145:0] b1_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_pkt";
output [2:0] b0_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_cid";
output b0_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_ctrue";
output b0_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b0_cpx_swap";
output [2:0] b1_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_cid";
output b1_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_ctrue";
output b1_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b1_cpx_swap";
output [39:0] b2_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_pa";
output [145:0] b2_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_pkt";
output [39:0] b3_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_pa";
output [145:0] b3_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_pkt";
output [2:0] b2_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_cid";
output b2_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_ctrue";
output b2_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b2_cpx_swap";
output [2:0] b3_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_cid";
output b3_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_ctrue";
output b3_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b3_cpx_swap";
output [39:0] b4_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_pa";
output [145:0] b4_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_pkt";
output [39:0] b5_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_pa";
output [145:0] b5_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_pkt";
output [2:0] b4_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_cid";
output b4_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_ctrue";
output b4_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b4_cpx_swap";
output [2:0] b5_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_cid";
output b5_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_ctrue";
output b5_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b5_cpx_swap";
output [39:0] b6_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_pa";
output [145:0] b6_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_pkt";
output [39:0] b7_cpx_pa NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_pa";
output [145:0] b7_cpx_pkt NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_pkt";
output [2:0] b6_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_cid";
output b6_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_ctrue";
output b6_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b6_cpx_swap";
output [2:0] b7_cpx_cid NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_cid";
output b7_cpx_ctrue NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_ctrue";
output b7_cpx_swap NR0 OUTPUT_SKEW hdl_node "tb_top.b7_cpx_swap";
bind ldStSync_port ldStSync_bind_b0 {
ctrue l2_if.b0_cpx_ctrue;
bind ldStSync_port ldStSync_bind_b1 {
ctrue l2_if.b1_cpx_ctrue;
bind ldStSync_port ldStSync_bind_b2 {
ctrue l2_if.b2_cpx_ctrue;
bind ldStSync_port ldStSync_bind_b3 {
ctrue l2_if.b3_cpx_ctrue;
bind ldStSync_port ldStSync_bind_b4 {
ctrue l2_if.b4_cpx_ctrue;
bind ldStSync_port ldStSync_bind_b5 {
ctrue l2_if.b5_cpx_ctrue;
bind ldStSync_port ldStSync_bind_b6 {
ctrue l2_if.b6_cpx_ctrue;
bind ldStSync_port ldStSync_bind_b7 {
ctrue l2_if.b7_cpx_ctrue;
bind ldStSync_port ldStSync_bind_b8 {
ctrue ncu_if.b8_cpx_ctrue;
bind probesPort probesBind {
th_check_enable probe_if.th_check_enable;