[OpenSPARC-T2-DV] / verif / env / common / coverage / ilu_peu / peu_register_coverage_sample.vrhpal

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: peu_register_coverage_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
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// ========== Copyright Header End ============================================
#inc "ilu_peu_cov_inc.pal"


   bit [63:0] peu_trn_off_reg_var = 64'b0; 

  coverage_group peu_trn_off_reg_coverage_group 
  { 
  sample_event = wait_var(peu_trn_off_reg_var);  


	  sample peu_registers_coverage_ifc.peu_trn_off_reg_pto 
          {
             state peu_trn_off_reg_pto (1) ;
          }

  } 

  bit [63:0] peu_ici_reg_var = 64'b0; 

  coverage_group peu_ici_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ici_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ici_reg_nhc[7:0]  {
. &toggle( 8 );
          cov_weight = 1;
          }

	  sample peu_registers_coverage_ifc.peu_ici_reg_phc[7:0]  {
. &toggle( 8 );
          cov_weight = 1;
          }
	  sample peu_registers_coverage_ifc.peu_ici_reg_pdc[7:0]  {
. &toggle( 8 );
          cov_weight = 1;
          }


  } 

  bit [63:0] peu_prfc_reg_var = 64'b0; 

  coverage_group peu_prfc_reg_coverage_group 
  { 
  sample_event = wait_var(peu_prfc_reg_var);  

          sample peu_registers_coverage_ifc.peu_prfc_reg_sel0[7:0] { 
. &toggle( 8 );
            cov_weight = 1;
          }

           sample peu_registers_coverage_ifc.peu_prfc_reg_sel1[7:0]  {
. &toggle( 8 );
            cov_weight = 1;
          }

	  sample peu_registers_coverage_ifc.peu_prfc_reg_sel2[1:0]  {
. &toggle( 2 );
            cov_weight = 1;
          }


  } 

  bit [63:0] peu_device_control_reg_var = 64'b0; 

  coverage_group peu_device_control_reg_coverage_group 
  { 
  sample_event = wait_var(peu_device_control_reg_var);  

          sample peu_registers_coverage_ifc.peu_device_control_reg_mps[2:0] { 
. &toggle( 3 );
            cov_weight = 1;
          }

  } 

  bit [63:0] peu_diagnostic_reg_var = 64'b0; 

  coverage_group peu_diagnostic_reg_coverage_group 
  { 
  sample_event = wait_var(peu_diagnostic_reg_var);  

          sample peu_registers_coverage_ifc.ilu_diagnos_rate_scale_hw_read[1:0] { 
. &toggle( 2 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_ehi_trig_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_edi_trig_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_ehi_par_hw_read[3:0] { 
. &toggle( 4 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_edi_par_hw_read[3:0] { 
. &toggle( 4 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enrx0_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enrx1_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enrx2_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enrx3_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enrx4_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enrx5_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enrx6_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enrx7_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_entx0_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_entx1_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_entx2_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_entx3_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_entx4_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_entx5_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_entx6_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_entx7_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enpll0_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.ilu_diagnos_enpll1_hw_read { 
. &toggle( 1 );
            cov_weight = 1;
          }

  } 

  bit [63:0] peu_link_control_reg_var = 64'b0; 

  coverage_group peu_link_control_reg_coverage_group 
  { 
  sample_event = wait_var(peu_link_control_reg_var);  

	  sample peu_registers_coverage_ifc.peu_link_control_reg_extended_sync 
          {
             state peu_link_control_reg_extended_sync (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_link_control_reg_common_clock 
          {
             state peu_link_control_reg_common_clock (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_link_control_reg_retrain 
          {
             state peu_link_control_reg_retrain (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_link_control_reg_disable 
          {
             state peu_link_control_reg_disable (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_link_control_reg_rcb 
          {
             state peu_link_control_reg_rcb (1) ;
          }
          sample peu_registers_coverage_ifc.peu_link_control_reg_aspm[1:0] {
. &toggle( 2 );
            cov_weight = 1;
          }


  } 

  bit [63:0] peu_link_status_reg_var = 64'b0; 

  coverage_group peu_link_status_reg_coverage_group 
  { 
  sample_event = wait_var(peu_link_status_reg_var);  

	  sample peu_registers_coverage_ifc.peu_link_status_reg_slot_clock 
          {
             state peu_link_status_reg_slot_clock (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_link_status_reg_train 
          {
             state peu_link_status_reg_train (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_link_status_reg_error 
          {
             state peu_link_status_reg_error (1) ;
          }
          sample peu_registers_coverage_ifc.peu_link_status_reg_width[5:0] { 
. &toggle( 6 );
            cov_weight = 1;
          }
          sample peu_registers_coverage_ifc.peu_link_status_reg_speed[3:0]  {
. &toggle( 4 );
            cov_weight = 1;
          }

  } 

  bit [9:0] peu_slot_cap_register_var = 10'b0; 

  coverage_group peu_slot_cap_register_coverage_group 
  { 
  sample_event = wait_var(peu_slot_cap_register_var);  

          sample peu_registers_coverage_ifc.peu_slot_cap_register_spls[1:0] {
. &toggle( 2 );
            cov_weight = 1;
          }

          sample peu_registers_coverage_ifc.peu_slot_cap_register_splv[7:0] { 
. &toggle( 8 );
            cov_weight = 1;
          }

  } 

  bit [63:0] peu_dlpl_dll_control_reg_var = 64'b0; 

  coverage_group peu_dlpl_dll_control_reg_coverage_group 
  { 
  sample_event = wait_var(peu_dlpl_dll_control_reg_var);  


          sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_ack_freq[7:0] {
. &toggle( 8 );
            cov_weight = 1;
          }

	  sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_flow_disable 
          {
             state peu_dlpl_dll_control_reg_flow_disable (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_other_message_req 
          {
             state peu_dlpl_dll_control_reg_other_message_req (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_ack_nak_disable 
          {
             state peu_dlpl_dll_control_reg_ack_nak_disable (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_data_link_en 
          {
             state peu_dlpl_dll_control_reg_data_link_en (1) ;
          }


  } 

  bit [63:0] peu_dlpl_macl_control_reg_var = 64'b0; 

  coverage_group peu_dlpl_macl_control_reg_coverage_group 
  { 
  sample_event = wait_var(peu_dlpl_macl_control_reg_var);  

          sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_link_num[7:0] { 
. &toggle( 8 );
            cov_weight = 1;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_nfts[7:0] { 
. &toggle( 8 );
            cov_weight = 1;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_link_capable[3:0] {
. &toggle( 4 );
            cov_weight = 1;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_fast_link_mode 
          {
             state peu_dlpl_macl_control_reg_fast_link_mode (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_elastic_buffer_disable 
          {
             state peu_dlpl_macl_control_reg_elastic_buffer_disable (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_scramble_disable 
          {
             state peu_dlpl_macl_control_reg_scramble_disable (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_reset_assert 
          {
             state peu_dlpl_macl_control_reg_reset_assert (1) ;
          }

  } 

  bit [63:0] peu_dlpl_lane_skew_reg_var = 64'b0; 

  coverage_group peu_dlpl_lane_skew_reg_coverage_group 
  { 
  sample_event = wait_var(peu_dlpl_lane_skew_reg_var);  

	  sample peu_registers_coverage_ifc.peu_dlpl_lane_skew_reg_deskew_disable 
          {
             state peu_dlpl_lane_skew_reg_deskew_disable (1) ;
          }

  } 

  bit [63:0] peu_dlpl_sym_num_reg_var = 64'b0; 

  coverage_group peu_dlpl_sym_num_reg_coverage_group 
  { 
  sample_event = wait_var(peu_dlpl_sym_num_reg_var);  

	  sample peu_registers_coverage_ifc.peu_dlpl_sym_num_reg_skip[2:0] { 
. &toggle( 3 );
           cov_weight = 1;
          }
	  sample peu_registers_coverage_ifc.peu_dlpl_sym_num_reg_ts1[3:0] { 
. &toggle( 4 );
           cov_weight = 1;
          }

  } 

  bit [63:0] peu_dlpl_sym_timer_reg_var = 64'b0; 

  coverage_group peu_dlpl_sym_timer_reg_coverage_group 
  { 
  sample_event = wait_var(peu_dlpl_sym_timer_reg_var);  

	  sample peu_registers_coverage_ifc.peu_dlpl_sym_timer_reg_skip_interval[10:0] { 
. &toggle( 11 );
           cov_weight = 1;
          }

  } 


  bit [63:0] peu_link_bit_error_counter_I_reg_var = 64'b0; 

  coverage_group peu_link_bit_error_counter_I_reg_coverage_group 
  { 
  sample_event = wait_var(peu_link_bit_error_counter_I_reg_var);  

	  sample peu_registers_coverage_ifc.peu_link_bit_error_counter_I_reg_ber_en 
          {
             state peu_link_bit_error_counter_I_reg_ber_en (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_link_bit_error_counter_I_reg_ber_clr 
          {
             state peu_link_bit_error_counter_I_reg_ber_clr (1) ;
          }

  } 


  bit [63:0] serdes_pll_csrbus_read_data_var = 64'b0; 

  coverage_group serdes_pll_csrbus_read_data_coverage_group 
  { 
  sample_event = wait_var(serdes_pll_csrbus_read_data_var);  

          sample peu_registers_coverage_ifc.serdes_pll_lb_hw_read[1:0] { 
. &toggle( 2 );
            cov_weight = 1;
          }

	  sample peu_registers_coverage_ifc.serdes_pll_mpy_hw_read[3:0] 
          { 
             state serdes_pll_mpy_250_clock       (4'b0001) ;
             state serdes_pll_mpy_125_clock       (4'b0101) ;
             state serdes_pll_mpy_100_clock       (4'b0111) ;
          }
  } 

  bit [63:0] peu_ser_receiver_lane_ctl0_reg_var = 64'b0; 

  coverage_group peu_ser_receiver_lane_ctl0_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_lane_ctl0_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg_entest 
          {
             state peu_ser_receiver_lane_ctl0_reg_entest (1) ;
          }
  } 

  bit [63:0] peu_ser_receiver_lane_ctl1_reg_var = 64'b0; 

  coverage_group peu_ser_receiver_lane_ctl1_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_lane_ctl1_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl1_reg_entest 
          {
             state peu_ser_receiver_lane_ctl1_reg_entest (1) ;
          }
  } 

  bit [63:0] peu_ser_receiver_lane_ctl2_reg_var = 64'b0; 

  coverage_group peu_ser_receiver_lane_ctl2_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_lane_ctl2_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl2_reg_entest 
          {
             state peu_ser_receiver_lane_ctl2_reg_entest (1) ;
          }
  } 

  bit [63:0] peu_ser_receiver_lane_ctl3_reg_var = 64'b0; 

  coverage_group peu_ser_receiver_lane_ctl3_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_lane_ctl3_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl3_reg_entest 
          {
             state peu_ser_receiver_lane_ctl3_reg_entest (1) ;
          }
  } 


  bit [63:0] peu_ser_receiver_lane_ctl4_reg_var = 64'b0; 

  coverage_group peu_ser_receiver_lane_ctl4_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_lane_ctl4_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl4_reg_entest 
          {
             state peu_ser_receiver_lane_ctl4_reg_entest (1) ;
          }
  } 

  bit [63:0] peu_ser_receiver_lane_ctl5_reg_var = 64'b0; 

  coverage_group peu_ser_receiver_lane_ctl5_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_lane_ctl5_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl5_reg_entest 
          {
             state peu_ser_receiver_lane_ctl5_reg_entest (1) ;
          }
  } 


  bit [63:0] peu_ser_receiver_lane_ctl6_reg_var = 64'b0; 

  coverage_group peu_ser_receiver_lane_ctl6_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_lane_ctl6_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl6_reg_entest 
          {
             state peu_ser_receiver_lane_ctl6_reg_entest (1) ;
          }
  } 

  bit [63:0] peu_ser_receiver_lane_ctl7_reg_var = 64'b0; 

  coverage_group peu_ser_receiver_lane_ctl7_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_lane_ctl7_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl7_reg_entest 
          {
             state peu_ser_receiver_lane_ctl7_reg_entest (1) ;
          }
  } 


  bit [63:0] peu_ser_xmitter_ctl_lane0_reg_var = 64'b0; 

  coverage_group peu_ser_xmitter_ctl_lane0_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_ctl_lane0_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane0_reg_invert_polarity 
          {
             state peu_ser_xmitter_ctl_lane0_reg_invert_polarity (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane0_reg_entest 
          {
             state peu_ser_xmitter_ctl_lane0_reg_entest (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_ctl_lane1_reg_var = 64'b0; 

  coverage_group peu_ser_xmitter_ctl_lane1_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_ctl_lane1_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane1_reg_invert_polarity 
          {
             state peu_ser_xmitter_ctl_lane1_reg_invert_polarity (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane1_reg_entest 
          {
             state peu_ser_xmitter_ctl_lane1_reg_entest (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_ctl_lane2_reg_var = 64'b0; 

  coverage_group peu_ser_xmitter_ctl_lane2_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_ctl_lane2_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane2_reg_invert_polarity 
          {
             state peu_ser_xmitter_ctl_lane2_reg_invert_polarity (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane2_reg_entest 
          {
             state peu_ser_xmitter_ctl_lane2_reg_entest (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_ctl_lane3_reg_var = 64'b0; 

  coverage_group peu_ser_xmitter_ctl_lane3_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_ctl_lane3_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane3_reg_invert_polarity 
          {
             state peu_ser_xmitter_ctl_lane3_reg_invert_polarity (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane3_reg_entest 
          {
             state peu_ser_xmitter_ctl_lane3_reg_entest (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_ctl_lane4_reg_var = 64'b0; 

  coverage_group peu_ser_xmitter_ctl_lane4_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_ctl_lane4_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane4_reg_invert_polarity 
          {
             state peu_ser_xmitter_ctl_lane4_reg_invert_polarity (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane4_reg_entest 
          {
             state peu_ser_xmitter_ctl_lane4_reg_entest (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_ctl_lane5_reg_var = 64'b0; 

  coverage_group peu_ser_xmitter_ctl_lane5_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_ctl_lane5_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane5_reg_invert_polarity 
          {
             state peu_ser_xmitter_ctl_lane5_reg_invert_polarity (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane5_reg_entest 
          {
             state peu_ser_xmitter_ctl_lane5_reg_entest (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_ctl_lane6_reg_var = 64'b0; 

  coverage_group peu_ser_xmitter_ctl_lane6_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_ctl_lane6_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane6_reg_invert_polarity 
          {
             state peu_ser_xmitter_ctl_lane6_reg_invert_polarity (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane6_reg_entest 
          {
             state peu_ser_xmitter_ctl_lane6_reg_entest (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_ctl_lane7_reg_var = 64'b0; 

  coverage_group peu_ser_xmitter_ctl_lane7_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_ctl_lane7_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane7_reg_invert_polarity 
          {
             state peu_ser_xmitter_ctl_lane7_reg_invert_polarity (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane7_reg_entest 
          {
             state peu_ser_xmitter_ctl_lane7_reg_entest (1) ;
          }

  } 

  
  bit [63:0] peu_ser_receiver_status_lane0_reg_var = 64'b0; 
  coverage_group peu_ser_receiver_status_lane0_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_status_lane0_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane0_reg[0] 
          {
             state peu_ser_receiver_status_lane0_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane0_reg[1] 
          {
             state peu_ser_receiver_status_lane0_reg_1 (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane0_reg[2] 
          {
             state peu_ser_receiver_status_lane0_reg_2 (2) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane0_reg[3] 
          {
             state peu_ser_receiver_status_lane0_reg_3 (3) ;
          }

  } 

  bit [63:0] peu_ser_receiver_status_lane1_reg_var = 64'b0; 
  coverage_group peu_ser_receiver_status_lane1_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_status_lane1_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane1_reg[0] 
          {
             state peu_ser_receiver_status_lane1_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane1_reg[1] 
          {
             state peu_ser_receiver_status_lane1_reg_1 (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane1_reg[2] 
          {
             state peu_ser_receiver_status_lane1_reg_2 (2) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane1_reg[3] 
          {
             state peu_ser_receiver_status_lane1_reg_3 (3) ;
          }

  } 
  bit [63:0] peu_ser_receiver_status_lane2_reg_var = 64'b0; 
  coverage_group peu_ser_receiver_status_lane2_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_status_lane2_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane2_reg[0] 
          {
             state peu_ser_receiver_status_lane2_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane2_reg[1] 
          {
             state peu_ser_receiver_status_lane2_reg_1 (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane2_reg[2] 
          {
             state peu_ser_receiver_status_lane2_reg_2 (2) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane2_reg[3] 
          {
             state peu_ser_receiver_status_lane2_reg_3 (3) ;
          }

  } 
  bit [63:0] peu_ser_receiver_status_lane3_reg_var = 64'b0; 
  coverage_group peu_ser_receiver_status_lane3_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_status_lane3_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane3_reg[0] 
          {
             state peu_ser_receiver_status_lane3_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane3_reg[1] 
          {
             state peu_ser_receiver_status_lane3_reg_1 (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane3_reg[2] 
          {
             state peu_ser_receiver_status_lane3_reg_2 (2) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane3_reg[3] 
          {
             state peu_ser_receiver_status_lane3_reg_3 (3) ;
          }

  } 
  bit [63:0] peu_ser_receiver_status_lane4_reg_var = 64'b0; 
  coverage_group peu_ser_receiver_status_lane4_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_status_lane4_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane4_reg[0] 
          {
             state peu_ser_receiver_status_lane4_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane4_reg[1] 
          {
             state peu_ser_receiver_status_lane4_reg_1 (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane4_reg[2] 
          {
             state peu_ser_receiver_status_lane4_reg_2 (2) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane4_reg[3] 
          {
             state peu_ser_receiver_status_lane4_reg_3 (3) ;
          }

  } 
  bit [63:0] peu_ser_receiver_status_lane5_reg_var = 64'b0; 
  coverage_group peu_ser_receiver_status_lane5_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_status_lane5_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane5_reg[0] 
          {
             state peu_ser_receiver_status_lane5_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane5_reg[1] 
          {
             state peu_ser_receiver_status_lane5_reg_1 (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane5_reg[2] 
          {
             state peu_ser_receiver_status_lane5_reg_2 (2) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane5_reg[3] 
          {
             state peu_ser_receiver_status_lane5_reg_3 (3) ;
          }

  } 
  bit [63:0] peu_ser_receiver_status_lane6_reg_var = 64'b0; 
  coverage_group peu_ser_receiver_status_lane6_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_status_lane6_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane6_reg[0] 
          {
             state peu_ser_receiver_status_lane6_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane6_reg[1] 
          {
             state peu_ser_receiver_status_lane6_reg_1 (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane6_reg[2] 
          {
             state peu_ser_receiver_status_lane6_reg_2 (2) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane6_reg[3] 
          {
             state peu_ser_receiver_status_lane6_reg_3 (3) ;
          }

  } 
  bit [63:0] peu_ser_receiver_status_lane7_reg_var = 64'b0; 
  coverage_group peu_ser_receiver_status_lane7_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_receiver_status_lane7_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane7_reg[0] 
          {
             state peu_ser_receiver_status_lane7_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane7_reg[1] 
          {
             state peu_ser_receiver_status_lane7_reg_1 (1) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane7_reg[2] 
          {
             state peu_ser_receiver_status_lane7_reg_2 (2) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane7_reg[3] 
          {
             state peu_ser_receiver_status_lane7_reg_3 (3) ;
          }

  } 


  // ser xmitter status lane 0 - 7 

  bit [63:0] peu_ser_xmitter_status_lane0_reg_var = 64'b0; 
  coverage_group peu_ser_xmitter_status_lane0_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_status_lane0_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane0_reg[0] 
          {
             state peu_ser_xmitter_status_lane0_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane0_reg[1] 
          {
             state peu_ser_xmitter_status_lane0_reg_1 (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_status_lane1_reg_var = 64'b0; 
  coverage_group peu_ser_xmitter_status_lane1_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_status_lane1_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane1_reg[0] 
          {
             state peu_ser_xmitter_status_lane1_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane1_reg[1] 
          {
             state peu_ser_xmitter_status_lane1_reg_1 (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_status_lane2_reg_var = 64'b0; 
  coverage_group peu_ser_xmitter_status_lane2_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_status_lane2_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane2_reg[0] 
          {
             state peu_ser_xmitter_status_lane2_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane2_reg[1] 
          {
             state peu_ser_xmitter_status_lane2_reg_1 (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_status_lane3_reg_var = 64'b0; 
  coverage_group peu_ser_xmitter_status_lane3_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_status_lane3_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane3_reg[0] 
          {
             state peu_ser_xmitter_status_lane3_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane3_reg[1] 
          {
             state peu_ser_xmitter_status_lane3_reg_1 (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_status_lane4_reg_var = 64'b0; 
  coverage_group peu_ser_xmitter_status_lane4_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_status_lane4_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane4_reg[0] 
          {
             state peu_ser_xmitter_status_lane4_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane4_reg[1] 
          {
             state peu_ser_xmitter_status_lane4_reg_1 (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_status_lane5_reg_var = 64'b0; 
  coverage_group peu_ser_xmitter_status_lane5_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_status_lane5_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane5_reg[0] 
          {
             state peu_ser_xmitter_status_lane5_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane5_reg[1] 
          {
             state peu_ser_xmitter_status_lane5_reg_1 (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_status_lane6_reg_var = 64'b0; 
  coverage_group peu_ser_xmitter_status_lane6_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_status_lane6_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane6_reg[0] 
          {
             state peu_ser_xmitter_status_lane6_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane6_reg[1] 
          {
             state peu_ser_xmitter_status_lane6_reg_1 (1) ;
          }

  } 

  bit [63:0] peu_ser_xmitter_status_lane7_reg_var = 64'b0; 
  coverage_group peu_ser_xmitter_status_lane7_reg_coverage_group 
  { 
  sample_event = wait_var(peu_ser_xmitter_status_lane7_reg_var);  

	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane7_reg[0] 
          {
             state peu_ser_xmitter_status_lane7_reg_0 (0) ;
          }
	  sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane7_reg[1] 
          {
             state peu_ser_xmitter_status_lane7_reg_1 (1) ;
          }

  }