Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / ccx_pcx_req_sample.vrhpal

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccx_pcx_req_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
    state allcores_bank0(128'h01010101_01010101_00000000_00000000);
    state allcores_bank1(128'h02020202_02020202_00000000_00000000);
    state allcores_bank2(128'h04040404_04040404_00000000_00000000);
    state allcores_bank3(128'h08080808_08080808_00000000_00000000);
    state allcores_bank4(128'h10101010_10101010_00000000_00000000);
    state allcores_bank5(128'h20202020_20202020_00000000_00000000);
    state allcores_bank6(128'h40404040_40404040_00000000_00000000);
    state allcores_bank7(128'h80808080_80808080_00000000_00000000);

    // 2-packet requests

    state allcores_bank0_atom(128'h01010101_01010101_01010101_01010101);
    state allcores_bank1_atom(128'h02020202_02020202_02020202_02020202);
    state allcores_bank2_atom(128'h04040404_04040404_04040404_04040404);
    state allcores_bank3_atom(128'h08080808_08080808_08080808_08080808);
    state allcores_bank4_atom(128'h10101010_10101010_10101010_10101010);
    state allcores_bank5_atom(128'h20202020_20202020_20202020_20202020);
    state allcores_bank6_atom(128'h40404040_40404040_40404040_40404040);
    state allcores_bank7_atom(128'h80808080_80808080_80808080_80808080);
    
/*    
    wildcard state core0_bank0({32'hXXXXXXX1, 8'bxxxxxxx0});
    wildcard state core0_bank1({32'hXXXXXXX2, 8'bxxxxxxx0});
    wildcard state core0_bank2({32'hXXXXXXX4, 8'bxxxxxxx0});
    wildcard state core0_bank3({32'hXXXXXXX8, 8'bxxxxxxx0});

    wildcard state core1_bank0({32'hXXXXXX1X, 8'bxxxxxx0x});
    wildcard state core1_bank1({32'hXXXXXX2X, 8'bxxxxxx0x});
    wildcard state core1_bank2({32'hXXXXXX4X, 8'bxxxxxx0x});
    wildcard state core1_bank3({32'hXXXXXX8X, 8'bxxxxxx0x});

    wildcard state core2_bank0({32'hXXXXX1XX, 8'bxxxxx0xx});
    wildcard state core2_bank1({32'hXXXXX2XX, 8'bxxxxx0xx});
    wildcard state core2_bank2({32'hXXXXX4XX, 8'bxxxxx0xx});
    wildcard state core2_bank3({32'hXXXXX8XX, 8'bxxxxx0xx});

    wildcard state core3_bank0({32'hXXXX1XXX, 8'bxxxx0xxx});
    wildcard state core3_bank1({32'hXXXX2XXX, 8'bxxxx0xxx});
    wildcard state core3_bank2({32'hXXXX4XXX, 8'bxxxx0xxx});
    wildcard state core3_bank3({32'hXXXX8XXX, 8'bxxxx0xxx});

    wildcard state core4_bank0({32'hXXX1XXXX, 8'bxxx0xxxx});
    wildcard state core4_bank1({32'hXXX2XXXX, 8'bxxx0xxxx});
    wildcard state core4_bank2({32'hXXX4XXXX, 8'bxxx0xxxx});
    wildcard state core4_bank3({32'hXXX8XXXX, 8'bxxx0xxxx});

    wildcard state core5_bank0({32'hXX1XXXXX, 8'bxx0xxxxx});
    wildcard state core5_bank1({32'hXX2XXXXX, 8'bxx0xxxxx});
    wildcard state core5_bank2({32'hXX4XXXXX, 8'bxx0xxxxx});
    wildcard state core5_bank3({32'hXX8XXXXX, 8'bxx0xxxxx});

    wildcard state core6_bank0({32'hX1XXXXXX, 8'bx0xxxxxx});
    wildcard state core6_bank1({32'hX2XXXXXX, 8'bx0xxxxxx});
    wildcard state core6_bank2({32'hX4XXXXXX, 8'bx0xxxxxx});
    wildcard state core6_bank3({32'hX8XXXXXX, 8'bx0xxxxxx});

    wildcard state core7_bank0({32'h1XXXXXXX, 8'b0xxxxxxx});
    wildcard state core7_bank1({32'h2XXXXXXX, 8'b0xxxxxxx});
    wildcard state core7_bank2({32'h4XXXXXXX, 8'b0xxxxxxx});
    wildcard state core7_bank3({32'h8XXXXXXX, 8'b0xxxxxxx});
*/
/*    
    wildcard state core0_bank0_atom({32'hXXXXXXX1, 8'bxxxxxxx1});
    wildcard state core0_bank1_atom({32'hXXXXXXX2, 8'bxxxxxxx1});
    wildcard state core0_bank2_atom({32'hXXXXXXX4, 8'bxxxxxxx1});
    wildcard state core0_bank3_atom({32'hXXXXXXX8, 8'bxxxxxxx1});

    wildcard state core1_bank0_atom({32'hXXXXXX1X, 8'bxxxxxx1x});
    wildcard state core1_bank1_atom({32'hXXXXXX2X, 8'bxxxxxx1x});
    wildcard state core1_bank2_atom({32'hXXXXXX4X, 8'bxxxxxx1x});
    wildcard state core1_bank3_atom({32'hXXXXXX8X, 8'bxxxxxx1x});

    wildcard state core2_bank0_atom({32'hXXXXX1XX, 8'bxxxxx1xx});
    wildcard state core2_bank1_atom({32'hXXXXX2XX, 8'bxxxxx1xx});
    wildcard state core2_bank2_atom({32'hXXXXX4XX, 8'bxxxxx1xx});
    wildcard state core2_bank3_atom({32'hXXXXX8XX, 8'bxxxxx1xx});

    wildcard state core3_bank0_atom({32'hXXXX1XXX, 8'bxxxx1xxx});
    wildcard state core3_bank1_atom({32'hXXXX2XXX, 8'bxxxx1xxx});
    wildcard state core3_bank2_atom({32'hXXXX4XXX, 8'bxxxx1xxx});
    wildcard state core3_bank3_atom({32'hXXXX8XXX, 8'bxxxx1xxx});

    wildcard state core4_bank0_atom({32'hXXX1XXXX, 8'bxxx1xxxx});
    wildcard state core4_bank1_atom({32'hXXX2XXXX, 8'bxxx1xxxx});
    wildcard state core4_bank2_atom({32'hXXX4XXXX, 8'bxxx1xxxx});
    wildcard state core4_bank3_atom({32'hXXX8XXXX, 8'bxxx1xxxx});

    wildcard state core5_bank0_atom({32'hXX1XXXXX, 8'bxx1xxxxx});
    wildcard state core5_bank1_atom({32'hXX2XXXXX, 8'bxx1xxxxx});
    wildcard state core5_bank2_atom({32'hXX4XXXXX, 8'bxx1xxxxx});
    wildcard state core5_bank3_atom({32'hXX8XXXXX, 8'bxx1xxxxx});

    wildcard state core6_bank0_atom({32'hX1XXXXXX, 8'bx1xxxxxx});
    wildcard state core6_bank1_atom({32'hX2XXXXXX, 8'bx1xxxxxx});
    wildcard state core6_bank2_atom({32'hX4XXXXXX, 8'bx1xxxxxx});
    wildcard state core6_bank3_atom({32'hX8XXXXXX, 8'bx1xxxxxx});

    wildcard state core7_bank0_atom({32'h1XXXXXXX, 8'b1xxxxxxx});
    wildcard state core7_bank1_atom({32'h2XXXXXXX, 8'b1xxxxxxx});
    wildcard state core7_bank2_atom({32'h4XXXXXXX, 8'b1xxxxxxx});
    wildcard state core7_bank3_atom({32'h8XXXXXXX, 8'b1xxxxxxx});
*/
// }