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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2_dir_write_sample.vrhpal
CommitLineData
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2_dir_write_sample.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35 wildcard state idir_panel_00( {1'b1, 4'h0, 4'bx, 10'bx} );
36 wildcard state idir_panel_01( {1'b1, 4'h1, 4'bx, 10'bx} );
37 wildcard state idir_panel_02( {1'b1, 4'h2, 4'bx, 10'bx} );
38 wildcard state idir_panel_03( {1'b1, 4'h3, 4'bx, 10'bx} );
39 wildcard state idir_panel_04( {1'b1, 4'h4, 4'bx, 10'bx} );
40 wildcard state idir_panel_05( {1'b1, 4'h5, 4'bx, 10'bx} );
41 wildcard state idir_panel_06( {1'b1, 4'h6, 4'bx, 10'bx} );
42 wildcard state idir_panel_07( {1'b1, 4'h7, 4'bx, 10'bx} );
43 wildcard state idir_panel_08( {1'b1, 4'h8, 4'bx, 10'bx} );
44 wildcard state idir_panel_09( {1'b1, 4'h9, 4'bx, 10'bx} );
45 wildcard state idir_panel_10( {1'b1, 4'ha, 4'bx, 10'bx} );
46 wildcard state idir_panel_11( {1'b1, 4'hb, 4'bx, 10'bx} );
47 wildcard state idir_panel_12( {1'b1, 4'hc, 4'bx, 10'bx} );
48 wildcard state idir_panel_13( {1'b1, 4'hd, 4'bx, 10'bx} );
49 wildcard state idir_panel_14( {1'b1, 4'he, 4'bx, 10'bx} );
50 wildcard state idir_panel_15( {1'b1, 4'hf, 4'bx, 10'bx} );
51
52 wildcard state idir_entry_00( {1'b1, 4'bx, 5'h00, 10'bx} );
53 wildcard state idir_entry_01( {1'b1, 4'bx, 5'h01, 10'bx} );
54 wildcard state idir_entry_02( {1'b1, 4'bx, 5'h02, 10'bx} );
55 wildcard state idir_entry_03( {1'b1, 4'bx, 5'h03, 10'bx} );
56 wildcard state idir_entry_04( {1'b1, 4'bx, 5'h04, 10'bx} );
57 wildcard state idir_entry_05( {1'b1, 4'bx, 5'h05, 10'bx} );
58 wildcard state idir_entry_06( {1'b1, 4'bx, 5'h06, 10'bx} );
59 wildcard state idir_entry_07( {1'b1, 4'bx, 5'h07, 10'bx} );
60 wildcard state idir_entry_08( {1'b1, 4'bx, 5'h08, 10'bx} );
61 wildcard state idir_entry_09( {1'b1, 4'bx, 5'h09, 10'bx} );
62 wildcard state idir_entry_10( {1'b1, 4'bx, 5'h0a, 10'bx} );
63 wildcard state idir_entry_11( {1'b1, 4'bx, 5'h0b, 10'bx} );
64 wildcard state idir_entry_12( {1'b1, 4'bx, 5'h0c, 10'bx} );
65 wildcard state idir_entry_13( {1'b1, 4'bx, 5'h0d, 10'bx} );
66 wildcard state idir_entry_14( {1'b1, 4'bx, 5'h0e, 10'bx} );
67 wildcard state idir_entry_15( {1'b1, 4'bx, 5'h0f, 10'bx} );
68 wildcard state idir_entry_16( {1'b1, 4'bx, 5'h10, 10'bx} );
69 wildcard state idir_entry_17( {1'b1, 4'bx, 5'h11, 10'bx} );
70 wildcard state idir_entry_18( {1'b1, 4'bx, 5'h12, 10'bx} );
71 wildcard state idir_entry_19( {1'b1, 4'bx, 5'h13, 10'bx} );
72 wildcard state idir_entry_20( {1'b1, 4'bx, 5'h14, 10'bx} );
73 wildcard state idir_entry_21( {1'b1, 4'bx, 5'h15, 10'bx} );
74 wildcard state idir_entry_22( {1'b1, 4'bx, 5'h16, 10'bx} );
75 wildcard state idir_entry_23( {1'b1, 4'bx, 5'h17, 10'bx} );
76 wildcard state idir_entry_24( {1'b1, 4'bx, 5'h18, 10'bx} );
77 wildcard state idir_entry_25( {1'b1, 4'bx, 5'h19, 10'bx} );
78 wildcard state idir_entry_26( {1'b1, 4'bx, 5'h1a, 10'bx} );
79 wildcard state idir_entry_27( {1'b1, 4'bx, 5'h1b, 10'bx} );
80 wildcard state idir_entry_28( {1'b1, 4'bx, 5'h1c, 10'bx} );
81 wildcard state idir_entry_29( {1'b1, 4'bx, 5'h1d, 10'bx} );
82 wildcard state idir_entry_30( {1'b1, 4'bx, 5'h1e, 10'bx} );
83 wildcard state idir_entry_31( {1'b1, 4'bx, 5'h1f, 10'bx} );
84
85 wildcard state ddir_panel_00( {10'bx, 1'b1, 4'h0, 4'bx} );
86 wildcard state ddir_panel_01( {10'bx, 1'b1, 4'h1, 4'bx} );
87 wildcard state ddir_panel_02( {10'bx, 1'b1, 4'h2, 4'bx} );
88 wildcard state ddir_panel_03( {10'bx, 1'b1, 4'h3, 4'bx} );
89 wildcard state ddir_panel_04( {10'bx, 1'b1, 4'h4, 4'bx} );
90 wildcard state ddir_panel_05( {10'bx, 1'b1, 4'h5, 4'bx} );
91 wildcard state ddir_panel_06( {10'bx, 1'b1, 4'h6, 4'bx} );
92 wildcard state ddir_panel_07( {10'bx, 1'b1, 4'h7, 4'bx} );
93 wildcard state ddir_panel_08( {10'bx, 1'b1, 4'h8, 4'bx} );
94 wildcard state ddir_panel_09( {10'bx, 1'b1, 4'h9, 4'bx} );
95 wildcard state ddir_panel_10( {10'bx, 1'b1, 4'ha, 4'bx} );
96 wildcard state ddir_panel_11( {10'bx, 1'b1, 4'hb, 4'bx} );
97 wildcard state ddir_panel_12( {10'bx, 1'b1, 4'hc, 4'bx} );
98 wildcard state ddir_panel_13( {10'bx, 1'b1, 4'hd, 4'bx} );
99 wildcard state ddir_panel_14( {10'bx, 1'b1, 4'he, 4'bx} );
100 wildcard state ddir_panel_15( {10'bx, 1'b1, 4'hf, 4'bx} );
101
102 wildcard state ddir_entry_00( {10'bx, 1'b1, 4'bx, 5'h00} );
103 wildcard state ddir_entry_01( {10'bx, 1'b1, 4'bx, 5'h01} );
104 wildcard state ddir_entry_02( {10'bx, 1'b1, 4'bx, 5'h02} );
105 wildcard state ddir_entry_03( {10'bx, 1'b1, 4'bx, 5'h03} );
106 wildcard state ddir_entry_04( {10'bx, 1'b1, 4'bx, 5'h04} );
107 wildcard state ddir_entry_05( {10'bx, 1'b1, 4'bx, 5'h05} );
108 wildcard state ddir_entry_06( {10'bx, 1'b1, 4'bx, 5'h06} );
109 wildcard state ddir_entry_07( {10'bx, 1'b1, 4'bx, 5'h07} );
110 wildcard state ddir_entry_08( {10'bx, 1'b1, 4'bx, 5'h08} );
111 wildcard state ddir_entry_09( {10'bx, 1'b1, 4'bx, 5'h09} );
112 wildcard state ddir_entry_10( {10'bx, 1'b1, 4'bx, 5'h0a} );
113 wildcard state ddir_entry_11( {10'bx, 1'b1, 4'bx, 5'h0b} );
114 wildcard state ddir_entry_12( {10'bx, 1'b1, 4'bx, 5'h0c} );
115 wildcard state ddir_entry_13( {10'bx, 1'b1, 4'bx, 5'h0d} );
116 wildcard state ddir_entry_14( {10'bx, 1'b1, 4'bx, 5'h0e} );
117 wildcard state ddir_entry_15( {10'bx, 1'b1, 4'bx, 5'h0f} );
118 wildcard state ddir_entry_16( {10'bx, 1'b1, 4'bx, 5'h10} );
119 wildcard state ddir_entry_17( {10'bx, 1'b1, 4'bx, 5'h11} );
120 wildcard state ddir_entry_18( {10'bx, 1'b1, 4'bx, 5'h12} );
121 wildcard state ddir_entry_19( {10'bx, 1'b1, 4'bx, 5'h13} );
122 wildcard state ddir_entry_20( {10'bx, 1'b1, 4'bx, 5'h14} );
123 wildcard state ddir_entry_21( {10'bx, 1'b1, 4'bx, 5'h15} );
124 wildcard state ddir_entry_22( {10'bx, 1'b1, 4'bx, 5'h16} );
125 wildcard state ddir_entry_23( {10'bx, 1'b1, 4'bx, 5'h17} );
126 wildcard state ddir_entry_24( {10'bx, 1'b1, 4'bx, 5'h18} );
127 wildcard state ddir_entry_25( {10'bx, 1'b1, 4'bx, 5'h19} );
128 wildcard state ddir_entry_26( {10'bx, 1'b1, 4'bx, 5'h1a} );
129 wildcard state ddir_entry_27( {10'bx, 1'b1, 4'bx, 5'h1b} );
130 wildcard state ddir_entry_28( {10'bx, 1'b1, 4'bx, 5'h1c} );
131 wildcard state ddir_entry_29( {10'bx, 1'b1, 4'bx, 5'h1d} );
132 wildcard state ddir_entry_30( {10'bx, 1'b1, 4'bx, 5'h1e} );
133 wildcard state ddir_entry_31( {10'bx, 1'b1, 4'bx, 5'h1f} );
134
Full OpenSPARC design & verification tarball including full HDL.