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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2_inst_flow_sample.vrhpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2_inst_flow_sample.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
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24// the General Public License version 2 (GPLv2) at this time for any
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35wildcard state LOAD_hit ( {HIT, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
36wildcard state LOAD_miss ( {MISS, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
37wildcard state LOAD_dep ( {DEP, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
38wildcard state LOAD_dephit ( {DEPHIT, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
39wildcard state LOAD_depmiss( {DEPMISS, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
40
41// PREFETCH vld diag reqtype nc jbi cputh inv pf bis
42wildcard state PREFETCH_hit ( {HIT, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
43wildcard state PREFETCH_miss ( {MISS, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
44wildcard state PREFETCH_dep ( {DEP, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
45wildcard state PREFETCH_dephit ( {DEPHIT, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
46wildcard state PREFETCH_depmiss( {DEPMISS, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
47
48// IMISS vld diag reqtype nc jbi cputh inv pf bis
49wildcard state IMISS_hit ( {HIT, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
50wildcard state IMISS_miss ( {MISS, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
51wildcard state IMISS_dep ( {DEP, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
52wildcard state IMISS_dephit ( {DEPHIT, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
53wildcard state IMISS_depmiss( {DEPMISS, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
54
55// STORE vld diag reqtype nc jbi cputh inv pf bis
56wildcard state STORE_hit ( {HIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
57wildcard state STORE_miss ( {MISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
58wildcard state STORE_dep ( {DEP, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
59wildcard state STORE_dephit ( {DEPHIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
60wildcard state STORE_depmiss( {DEPMISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
61
62// BLKSTORE vld diag reqtype nc jbi cputh inv pf bis
63wildcard state BLKSTORE_hit ( {HIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
64wildcard state BLKSTORE_miss ( {MISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
65wildcard state BLKSTORE_dep ( {DEP, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
66wildcard state BLKSTORE_dephit ( {DEPHIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
67wildcard state BLKSTORE_depmiss( {DEPMISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
68
69// BLKINITST vld diag reqtype nc jbi cputh inv pf bis
70wildcard state BLKINITST_hit ( {HIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
71wildcard state BLKINITST_miss ( {MISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
72wildcard state BLKINITST_dep ( {DEP, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
73wildcard state BLKINITST_dephit ( {DEPHIT, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
74wildcard state BLKINITST_depmiss( {DEPMISS, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
75
76// CAS1 vld diag reqtype nc jbi cputh inv pf bis
77wildcard state CAS1_hit ( {HIT, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
78wildcard state CAS1_miss ( {MISS, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
79wildcard state CAS1_dep ( {DEP, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
80wildcard state CAS1_dephit ( {DEPHIT, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
81wildcard state CAS1_depmiss( {DEPMISS, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
82
83// CAS2 vld diag reqtype nc jbi cputh inv pf bis
84// CAS2 never has HIT (true hit: see top) combination
85//wildcard state CAS2_hit ( {HIT, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
86wildcard state CAS2_miss ( {MISS, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
87wildcard state CAS2_dep ( {DEP, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
88wildcard state CAS2_dephit ( {DEPHIT, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
89wildcard state CAS2_depmiss( {DEPMISS, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
90
91// SWAP vld diag reqtype nc jbi cputh inv pf bis
92wildcard state SWAP_hit ( {HIT, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
93wildcard state SWAP_miss ( {MISS, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
94wildcard state SWAP_dep ( {DEP, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
95wildcard state SWAP_dephit ( {DEPHIT, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
96wildcard state SWAP_depmiss( {DEPMISS, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
97
98// STRLOAD vld diag reqtype nc jbi cputh inv pf bis
99wildcard state STRLOAD_hit ( {HIT, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
100wildcard state STRLOAD_miss ( {MISS, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
101wildcard state STRLOAD_dep ( {DEP, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
102wildcard state STRLOAD_dephit ( {DEPHIT, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
103wildcard state STRLOAD_depmiss( {DEPMISS, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
104
105// STRST vld diag reqtype nc jbi cputh inv pf bis
106wildcard state STRST_hit ( {HIT, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
107wildcard state STRST_miss ( {MISS, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
108wildcard state STRST_dep ( {DEP, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
109wildcard state STRST_dephit ( {DEPHIT, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
110wildcard state STRST_depmiss( {DEPMISS, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
111/*
112// FWDRQ_LOAD vld diag reqtype nc jbi cputh inv pf bis
113wildcard state FWDRQ_LOAD_hit ( {HIT, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
114wildcard state FWDRQ_LOAD_miss ( {MISS, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
115wildcard state FWDRQ_LOAD_dep ( {DEP, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
116wildcard state FWDRQ_LOAD_dephit ( {DEPHIT, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
117wildcard state FWDRQ_LOAD_depmiss( {DEPMISS, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
118
119// FWDRQ_STORE vld diag reqtype nc jbi cputh inv pf bis
120wildcard state FWDRQ_STORE_hit ( {HIT, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
121wildcard state FWDRQ_STORE_miss ( {MISS, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
122wildcard state FWDRQ_STORE_dep ( {DEP, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
123wildcard state FWDRQ_STORE_dephit ( {DEPHIT, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
124wildcard state FWDRQ_STORE_depmiss( {DEPMISS, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
125*/
126
127// RDD vld diag reqtype nc jbi
128wildcard state RDD_hit ( {HIT, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
129wildcard state RDD_miss ( {MISS, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
130wildcard state RDD_dep ( {DEP, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
131wildcard state RDD_dephit ( {DEPHIT, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
132wildcard state RDD_depmiss( {DEPMISS, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
133
134// WR8 vld diag reqtype nc jbi
135wildcard state WR8_hit ( {HIT, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
136wildcard state WR8_miss ( {MISS, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
137wildcard state WR8_dep ( {DEP, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
138wildcard state WR8_dephit ( {DEPHIT, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
139wildcard state WR8_depmiss( {DEPMISS, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
140
141// WRI vld diag reqtype nc jbi
142wildcard state WRI_hit ( {HIT, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
143wildcard state WRI_miss ( {MISS, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
144wildcard state WRI_dep ( {DEP, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
145wildcard state WRI_dephit ( {DEPHIT, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
146wildcard state WRI_depmiss( {DEPMISS, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
Full OpenSPARC design & verification tarball including full HDL.