Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2_two_simultaneous_errors_sample.vrhpal

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// 
// OpenSPARC T2 Processor File: l2_two_simultaneous_errors_sample.vrhpal
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wildcard state LDAC_and_LDWC ({1'b1, 1'bx, 1'b1, 17'bx});
wildcard state LDAC_and_LDWU ({1'b1, 2'bx, 1'b1, 16'bx});
wildcard state LDAC_and_LTC ({1'b1, 7'bx, 1'b1, 11'bx});
wildcard state LDAC_and_LVC ({1'b1, 16'bx, 1'b1, 2'bx});

wildcard state LDAU_and_LDWC ({1'bx, 1'b1, 1'b1, 17'bx});
wildcard state LDAU_and_LDWU ({1'bx, 1'b1, 1'bx, 1'b1, 16'bx});
wildcard state LDAU_and_LTC ({1'bx, 1'b1, 6'bx, 1'b1, 11'bx});
wildcard state LDAU_and_LVC ({1'bx, 1'b1, 15'bx, 1'b1, 2'bx});

wildcard state LDRC_and_LDWC ({2'bx, 1'b1, 1'bx, 1'b1, 15'bx});
wildcard state LDRC_and_LDWU ({3'bx, 1'b1,       1'b1, 15'bx});
wildcard state LDRC_and_LTC ({4'bx, 1'b1, 3'bx, 1'b1, 11'bx});
wildcard state LDRC_and_LVC ({4'bx, 1'b1, 14'bx, 1'b1});

wildcard state LDRU_and_LDWC ({2'bx, 1'b1, 2'bx, 1'b1, 14'bx});
wildcard state LDRU_and_LDWU ({3'bx, 1'b1, 1'bx, 1'b1, 14'bx});
wildcard state LDRU_and_LTC ({5'bx, 1'b1, 2'bx, 1'b1, 11'bx});
wildcard state LDRU_and_LVC ({5'bx, 1'b1, 11'bx, 1'b1, 2'bx});

wildcard state LDSC_and_LDWC ({2'bx, 1'b1, 3'bx, 1'b1, 13'bx});
wildcard state LDSC_and_LDWU ({3'bx, 1'b1, 2'bx, 1'b1, 13'bx});
wildcard state LDSC_and_LTC ({6'bx, 1'b1, 1'bx, 1'b1, 11'bx});
wildcard state LDSC_and_LVC ({6'bx, 1'b1, 10'bx, 1'b1, 2'bx});

wildcard state LDSU_and_LDWC ({2'bx, 1'b1, 4'bx, 1'b1, 12'bx});
wildcard state LDSU_and_LDWU ({3'bx, 1'b1, 3'bx, 1'b1, 12'bx});
wildcard state LDSU_and_LTC ({7'bx, 1'b1, 1'b1, 11'bx});
wildcard state LDSU_and_LVC ({7'bx, 1'b1, 9'bx, 1'b1, 2'bx});

wildcard state DAC_and_LDWC ({2'bx, 1'b1, 1'bx, 7'bx, 1'b1, 8'bx});
wildcard state DAC_and_LDWU ({3'bx, 1'b1, 7'bx, 1'b1, 8'bx});
wildcard state DAC_and_LTC ({8'bx, 1'b1, 2'bx, 1'b1, 8'bx});
wildcard state DAC_and_LVC ({11'bx, 1'b1, 5'bx, 1'b1, 2'bx});

wildcard state DAU_and_LDWC ({2'bx, 1'b1, 1'bx, 8'bx, 1'b1, 7'bx});
wildcard state DAU_and_LDWU ({3'bx, 1'b1, 8'bx, 1'b1, 7'bx});
wildcard state DAU_and_LTC ({8'bx, 1'b1, 3'bx, 1'b1, 7'bx});
wildcard state DAU_and_LVC ({12'bx, 1'b1, 4'bx, 1'b1, 2'bx});

wildcard state DRC_and_LDWC ({2'bx, 1'b1, 1'bx, 9'bx, 1'b1, 6'bx});
wildcard state DRC_and_LDWU ({3'bx, 1'b1, 9'bx, 1'b1, 6'bx});
wildcard state DRC_and_LTC ({8'bx, 1'b1, 4'bx, 1'b1, 6'bx});
wildcard state DRC_and_LVC ({13'bx, 1'b1, 3'bx, 1'b1, 2'bx});

wildcard state DRU_and_LDWC ({2'bx, 1'b1, 1'bx, 10'bx, 1'b1, 5'bx});
wildcard state DRU_and_LDWU ({3'bx, 1'b1, 10'bx, 1'b1, 5'bx});
wildcard state DRU_and_LTC ({8'bx, 1'b1, 5'bx, 1'b1, 5'bx});
wildcard state DRU_and_LVC ({14'bx, 1'b1, 2'bx, 1'b1, 2'bx});

wildcard state DSC_and_LDWC ({2'bx, 1'b1, 1'bx, 11'bx, 1'b1, 4'bx});
wildcard state DSC_and_LDWU ({3'bx, 1'b1, 11'bx, 1'b1, 4'bx});
wildcard state DSC_and_LTC ({8'bx, 1'b1, 6'bx, 1'b1, 4'bx});
wildcard state DSC_and_LVC ({15'bx, 1'b1, 1'bx, 1'b1, 2'bx});

wildcard state DSU_and_LDWC ({2'bx, 1'b1, 1'bx, 12'bx, 1'b1, 3'bx});
wildcard state DSU_and_LDWU ({3'bx, 1'b1, 12'bx, 1'b1, 3'bx});
wildcard state DSU_and_LTC ({8'bx, 1'b1, 7'bx, 1'b1, 3'bx});
wildcard state DSU_and_LVC ({16'bx, 1'b1, 1'b1, 2'bx});

wildcard state NDSP_and_LDWC ({2'bx, 1'b1, 15'bx, 1'b1, 1'bx});
wildcard state NDSP_and_LDWU ({3'bx, 1'b1, 14'bx, 1'b1, 1'bx});
wildcard state NDSP_and_LTC ({8'bx, 1'b1, 9'bx, 1'b1, 1'bx});
wildcard state NDSP_and_LVC ({17'bx, 1'b1, 1'b1, 1'bx});

wildcard state NDDM_and_LDWC ({2'bx, 1'b1, 15'bx, 1'bx, 1'b1});
wildcard state NDDM_and_LDWU ({3'bx, 1'b1, 14'bx, 1'bx, 1'b1});
wildcard state NDDM_and_LTC ({8'bx, 1'b1, 9'bx, 1'bx, 1'b1});
wildcard state NDDM_and_LVC ({17'bx, 1'b1, 1'bx, 1'b1});

wildcard state LTC_and_LDWC ({2'bx, 1'b1, 1'bx, 4'bx, 1'b1, 11'bx});
wildcard state LTC_and_LDWU ({3'bx, 1'b1, 4'bx, 1'b1, 11'bx});
wildcard state LTC_and_LVC ({8'bx, 1'b1, 8'bx, 1'b1, 2'bx});

wildcard state LVC_and_LDWC ({2'bx, 1'b1, 14'bx, 1'b1, 2'bx});
wildcard state LVC_and_LDWU ({3'bx, 1'b1, 13'bx, 1'b1, 2'bx});