projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: l2sat_defines.vrhpal | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #define CTRUE 37 | |
| 36 | #define REQTYPE 25:21 | |
| 37 | #define NC 20 | |
| 38 | #define JBI_INST 19 | |
| 39 | #define PF 11 | |
| 40 | #define BIS 10 | |
| 41 | ||
| 42 | ||
| 43 | // ccx_cpx_sequence | |
| 44 | #define CPX_NO_REQ 17'b00000000_0_xxxxxxxx | |
| 45 | #define CPX_NO_REQ_G0 17'b00000000_0_xxxxxxx0 | |
| 46 | #define CPX_NO_REQ_G1 17'b00000000_0_xxxxxxx1 | |
| 47 | #define CPX_SINGLE_REQ 17'b00000001_0_xxxxxxxx | |
| 48 | #define CPX_SINGLE_REQ_G0 17'b00000001_0_xxxxxxx0 | |
| 49 | #define CPX_SINGLE_REQ_G1 17'b00000001_0_xxxxxxx1 | |
| 50 | #define CPX_DOUBLE_REQ 17'b00000001_1_xxxxxxxx | |
| 51 | #define CPX_DOUBLE_REQ_G0 17'b00000001_1_xxxxxxx0 | |
| 52 | #define CPX_DOUBLE_REQ_G1 17'b00000001_1_xxxxxxx1 | |
| 53 | ||
| 54 | // ccx_pcx_sequence | |
| 55 | // requests only to L2 bank0, all combos of gnts and atm/non reqs | |
| 56 | #define PCX_NO_REQ 24'b00000000_00000000_xxxxxxxx | |
| 57 | #define PCX_NO_REQ_G0 24'b00000000_00000000_xxxxxxx0 | |
| 58 | #define PCX_NO_REQ_G1 24'b00000000_00000000_xxxxxxx1 | |
| 59 | #define PCX_SINGLE_REQ 24'b00000001_00000000_xxxxxxxx | |
| 60 | #define PCX_SINGLE_REQ_G0 24'b00000001_00000000_xxxxxxx0 | |
| 61 | #define PCX_SINGLE_REQ_G1 24'b00000001_00000000_xxxxxxx1 | |
| 62 | #define PCX_DOUBLE_REQ 24'b00000001_00000001_xxxxxxxx | |
| 63 | #define PCX_DOUBLE_REQ_G0 24'b00000001_00000001_xxxxxxx0 | |
| 64 | #define PCX_DOUBLE_REQ_G1 24'b00000001_00000001_xxxxxxx1 | |
| 65 | ||
| 66 | // PCX reqtypes | |
| 67 | #define LOAD_RQ 5'b00000 | |
| 68 | #define IMISS_RQ 5'b10000 | |
| 69 | #define STORE_RQ 5'b00001 | |
| 70 | #define CAS1_RQ 5'b00010 | |
| 71 | #define CAS2_RQ 5'b00011 | |
| 72 | #define SWAP_RQ 5'b00111 | |
| 73 | #define STRLOAD_RQ 5'b00100 | |
| 74 | #define STRST_RQ 5'b00101 | |
| 75 | #define INT_RQ 5'b01001 | |
| 76 | #define FWD_RQ 5'b01101 | |
| 77 | #define FILL 5'b11111 | |
| 78 | ||
| 79 | // CPX rtntypes | |
| 80 | #define LOAD_RET 4'b0000 | |
| 81 | #define IFILL_RET 4'b0001 | |
| 82 | #define ST_ACK 4'b0100 | |
| 83 | #define STRLOAD_RET 4'b0010 | |
| 84 | #define STRST_ACK 4'b0110 | |
| 85 | #define INT_RET 4'b0111 | |
| 86 | #define FWD_RPY_RET 4'b1011 | |
| 87 | #define EVICT_REQ 4'b0011 | |
| 88 | #define ERR_RET 4'b1100 | |
| 89 | ||
| 90 | // l2_inst_flow | |
| 91 | #define HIT 4'b1000 | |
| 92 | #define MISS 4'b0000 | |
| 93 | #define DEP 4'bx100 | |
| 94 | #define DEPHIT 4'b1010 | |
| 95 | #define DEPMISS 4'b0010 | |
| 96 | ||
| 97 | // l2_error_status_reg_cov | |
| 98 | #define LDAC_0 10'bx, 1'b0, 21'bx | |
| 99 | #define LDAU_0 11'bx, 1'b0, 20'bx | |
| 100 | #define LDWC_0 12'bx, 1'b0, 19'bx | |
| 101 | #define LDWU_0 13'bx, 1'b0, 18'bx | |
| 102 | #define LDRC_0 14'bx, 1'b0, 17'bx | |
| 103 | #define LDRU_0 15'bx, 1'b0, 16'bx | |
| 104 | #define LDSC_0 16'bx, 1'b0, 15'bx | |
| 105 | #define LDSU_0 17'bx, 1'b0, 14'bx | |
| 106 | #define LTC_0 18'bx, 1'b0, 13'bx | |
| 107 | #define LRU_0 19'bx, 1'b0, 12'bx | |
| 108 | #define LVU_0 20'bx, 1'b0, 11'bx | |
| 109 | #define DAC_0 21'bx, 1'b0, 10'bx | |
| 110 | #define DAU_0 22'bx, 1'b0, 9'bx | |
| 111 | #define DRC_0 23'bx, 1'b0, 8'bx | |
| 112 | #define DRU_0 24'bx, 1'b0, 7'bx | |
| 113 | #define DSC_0 25'bx, 1'b0, 6'bx | |
| 114 | #define DSU_0 26'bx, 1'b0, 5'bx | |
| 115 | #define LVC_0 29'bx, 1'b0, 2'bx | |
| 116 | #define LDAC_1 10'bx, 1'b1, 21'bx | |
| 117 | #define LDAU_1 11'bx, 1'b1, 20'bx | |
| 118 | #define LDWC_1 12'bx, 1'b1, 19'bx | |
| 119 | #define LDWU_1 13'bx, 1'b1, 18'bx | |
| 120 | #define LDRC_1 14'bx, 1'b1, 17'bx | |
| 121 | #define LDRU_1 15'bx, 1'b1, 16'bx | |
| 122 | #define LDSC_1 16'bx, 1'b1, 15'bx | |
| 123 | #define LDSU_1 17'bx, 1'b1, 14'bx | |
| 124 | #define LTC_1 18'bx, 1'b1, 13'bx | |
| 125 | #define LRU_1 19'bx, 1'b1, 12'bx | |
| 126 | #define LVU_1 20'bx, 1'b1, 11'bx | |
| 127 | #define DAC_1 21'bx, 1'b1, 10'bx | |
| 128 | #define DAU_1 22'bx, 1'b1, 9'bx | |
| 129 | #define DRC_1 23'bx, 1'b1, 8'bx | |
| 130 | #define DRU_1 24'bx, 1'b1, 7'bx | |
| 131 | #define DSC_1 25'bx, 1'b1, 6'bx | |
| 132 | #define DSU_1 26'bx, 1'b1, 5'bx | |
| 133 | #define LVC_1 29'bx, 1'b1, 2'bx | |
| 134 | ||
| 135 | // l2_notdata_error_reg_cov | |
| 136 | #define NDSP_0 1'b0, 1'bx | |
| 137 | #define NDDM_0 1'bx, 1'b0 | |
| 138 | #define NDSP_1 1'b1, 1'bx | |
| 139 | #define NDDM_1 1'bx, 1'b1 | |
| 140 | ||
| 141 | ||
| 142 | // l2_atomic_store_cov | |
| 143 | #define CAS_STORE 14'b0000000_0000001 | |
| 144 | #define CAS_BLKSTORE 14'b0000000_0000010 | |
| 145 | #define CAS_BLKINITST 14'b0000000_0000100 | |
| 146 | #define CAS_STRST 14'b0000000_0001000 | |
| 147 | #define CAS_FWDRQST 14'b0000000_0010000 | |
| 148 | #define CAS_WR8 14'b0000000_0100000 | |
| 149 | #define CAS_WRI 14'b0000000_1000000 | |
| 150 | #define SWAP_STORE 14'b0000001_0000000 | |
| 151 | #define SWAP_BLKSTORE 14'b0000010_0000000 | |
| 152 | #define SWAP_BLKINITST 14'b0000100_0000000 | |
| 153 | #define SWAP_STRST 14'b0001000_0000000 | |
| 154 | #define SWAP_FWDRQST 14'b0010000_0000000 | |
| 155 | #define SWAP_WR8 14'b0100000_0000000 | |
| 156 | #define SWAP_WRI 14'b1000000_0000000 | |
| 157 | ||
| 158 | // l2_pst1_dataerr_pst2_tagerr_cov | |
| 159 | #define PST12_STORE 3'b001 | |
| 160 | #define PST12_STRST 3'b010 | |
| 161 | #define PST12_WR8 3'b100 | |
| 162 | ||
| 163 | ||
| 164 |