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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / mcusat / mcusat_cov.if.vrhpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcusat_cov.if.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#inc "mcusat_cov_inc.pal";
36#ifndef __DRAM_IF_VRH__
37#define __DRAM_IF_VRH__
38#define INPUT_SKEW #-1
39
40#include <vera_defines.vrh>
41`ifdef IDT_AMB
42interface dram_coverage_ifc_link_clk
43{
44 input sclk CLOCK verilog_node "tb_top.crc_errinject_top.sb_crc_errinj0a_p.link_clk";
45}
46`endif
47
48interface dram_coverage_ifc_dram_clk
49{
50 // Common & Clock Signals
51 input dram_gclk CLOCK ;
52 input dram_rst_l PSAMPLE ;
53 input dram_Ch0_pt_selfrsh PSAMPLE;
54 input dram_Ch1_pt_selfrsh PSAMPLE;
55 input dram_Ch2_pt_selfrsh PSAMPLE;
56 input dram_Ch3_pt_selfrsh PSAMPLE;
57 input dram_Ch0_pt_blk_new_openbank_d1 PSAMPLE;
58 input dram_Ch1_pt_blk_new_openbank_d1 PSAMPLE;
59 input dram_Ch2_pt_blk_new_openbank_d1 PSAMPLE;
60 input dram_Ch3_pt_blk_new_openbank_d1 PSAMPLE;
61`ifdef IDT_AMB
62 input [9:0] ps_in PSAMPLE INPUT_SKEW verilog_node "tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_in";
63 input [9:0] ps_out PSAMPLE INPUT_SKEW verilog_node "tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_out";
64`endif
65// input sclk PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu_fmon.sclk";
66
67. sub coreSignals {
68. my( $core_str ) = @_;
69. my $c = $core_str;
70 input [4:0] dram_Ch${c}_que_pos PSAMPLE;
71
72 input dram_Ch${c}_l2b0_rd_req PSAMPLE;
73 input [7:0] dram_Ch${c}_l2b0_rd_que_wr_ptr PSAMPLE;
74 input [7:0] dram_Ch${c}_l2b0_rd_que_rd_ptr PSAMPLE;
75 input [3:0] dram_Ch${c}_l2b0_rd_q_cnt PSAMPLE;
76 input dram_Ch${c}_l2b0_rd_q_full PSAMPLE;
77 input [3:0] dram_Ch${c}_l2b0_rd_colps_q_cnt PSAMPLE;
78 input dram_Ch${c}_l2b0_rd_colps_q_full PSAMPLE;
79 input dram_Ch${c}_l2b0_rd_q_empty PSAMPLE;
80 input dram_Ch${c}_l2b0_rd_colps_q_empty PSAMPLE;
81
82 input dram_Ch${c}_l2b1_rd_req PSAMPLE;
83 input [7:0] dram_Ch${c}_l2b1_rd_que_wr_ptr PSAMPLE;
84 input [7:0] dram_Ch${c}_l2b1_rd_que_rd_ptr PSAMPLE;
85 input [3:0] dram_Ch${c}_l2b1_rd_q_cnt PSAMPLE;
86 input dram_Ch${c}_l2b1_rd_q_full PSAMPLE;
87 input [3:0] dram_Ch${c}_l2b1_rd_colps_q_cnt PSAMPLE;
88 input dram_Ch${c}_l2b1_rd_colps_q_full PSAMPLE;
89 input dram_Ch${c}_l2b1_rd_q_empty PSAMPLE;
90 input dram_Ch${c}_l2b1_rd_colps_q_empty PSAMPLE;
91
92 input dram_Ch${c}_l2b1_wr_req PSAMPLE;
93 input [7:0] dram_Ch${c}_l2b1_wr_que_wr_ptr PSAMPLE;
94 input [7:0] dram_Ch${c}_l2b1_wr_que_rd_ptr PSAMPLE;
95 input [7:0] dram_Ch${c}_l2b1_wr_que_rd_ptr_arb PSAMPLE;
96 input [3:0] dram_Ch${c}_l2b1_wr_q_cnt PSAMPLE;
97 input dram_Ch${c}_l2b1_wr_q_full PSAMPLE;
98 input [3:0] dram_Ch${c}_l2b1_wr_colps_q_cnt PSAMPLE;
99 input dram_Ch${c}_l2b1_wr_colps_q_full PSAMPLE;
100 input dram_Ch${c}_l2b1_wr_q_empty PSAMPLE;
101 input dram_Ch${c}_l2b1_wr_colps_q_empty PSAMPLE;
102
103 input dram_Ch${c}_l2b0_wr_req PSAMPLE;
104 input [7:0] dram_Ch${c}_l2b0_wr_que_wr_ptr PSAMPLE;
105 input [7:0] dram_Ch${c}_l2b0_wr_que_rd_ptr PSAMPLE;
106 input [7:0] dram_Ch${c}_l2b0_wr_que_rd_ptr_arb PSAMPLE;
107 input [3:0] dram_Ch${c}_l2b0_wr_q_cnt PSAMPLE;
108 input dram_Ch${c}_l2b0_wr_q_full PSAMPLE;
109 input [3:0] dram_Ch${c}_l2b0_wr_colps_q_cnt PSAMPLE;
110 input dram_Ch${c}_l2b0_wr_colps_q_full PSAMPLE;
111 input dram_Ch${c}_l2b0_wr_q_empty PSAMPLE;
112 input dram_Ch${c}_l2b0_wr_colps_q_empty PSAMPLE;
113
114 input [1:0] dram_Ch${c}_refresh_all_clr_mon_state PSAMPLE;
115
116 input [7:0] dram_Ch${c}_que_cas_valid PSAMPLE;
117 input [4:0] dram_Ch${c}_que_mem_addr PSAMPLE;
118
119 input dram_Ch${c}_que_pick_wr_first PSAMPLE;
120
121 input dram_Ch${c}_l2b0_rd_req_2a_addr_vld PSAMPLE;
122 input dram_Ch${c}_l2b0_wr_req_2a_addr_vld PSAMPLE;
123 input dram_Ch${c}_scrb_req_2a_addr_vld PSAMPLE;
124
125 input dram_Ch${c}_l2b1_rd_req_2a_addr_vld PSAMPLE;
126 input dram_Ch${c}_l2b1_wr_req_2a_addr_vld PSAMPLE;
127 input dram_Ch${c}_que_rd_wr_hit PSAMPLE;
128
129 input [3:0] dram_Ch${c}_ras_pend_cnt PSAMPLE;
130 input [7:0] dram_Ch${c}_que_ras_picked PSAMPLE;
131 input [15:0] dram_Ch${c}_ras_picked PSAMPLE;
132 input [3:0] dram_Ch${c}_cas_pend_cnt PSAMPLE;
133 input [7:0] dram_Ch${c}_que_cas_picked PSAMPLE;
134 input [15:0] dram_Ch${c}_que_l2req_valid PSAMPLE;
135 input [15:0] dram_Ch${c}_scrb_indx_val PSAMPLE;
136
137
138 input [8:0] dram_Ch${c}_chip_config_reg PSAMPLE;
139 input [2:0] dram_Ch${c}_mode_reg PSAMPLE;
140 input [3:0] dram_Ch${c}_rrd_reg PSAMPLE;
141 input [4:0] dram_Ch${c}_rc_reg PSAMPLE;
142 input [3:0] dram_Ch${c}_rcd_reg PSAMPLE;
143 input [3:0] dram_Ch${c}_wtr_dly_reg PSAMPLE;
144 input [3:0] dram_Ch${c}_rtw_dly_reg PSAMPLE;
145 input [3:0] dram_Ch${c}_rtp_reg PSAMPLE;
146 input [3:0] dram_Ch${c}_ras_reg PSAMPLE;
147 input [3:0] dram_Ch${c}_rp_reg PSAMPLE;
148 input [3:0] dram_Ch${c}_wr_reg PSAMPLE;
149 input [1:0] dram_Ch${c}_mrd_reg PSAMPLE;
150 input [1:0] dram_Ch${c}_iwtr_reg PSAMPLE;
151 input [14:0]dram_Ch${c}_ext_mode_reg2 PSAMPLE;
152 input [14:0]dram_Ch${c}_ext_mode_reg1 PSAMPLE;
153 input [14:0]dram_Ch${c}_ext_mode_reg3 PSAMPLE;
154 input dram_Ch${c}_que_eight_bank_mode PSAMPLE;
155 input dram_Ch${c}_que_rank1_present PSAMPLE;
156 input dram_Ch${c}_que_channel_disabled PSAMPLE;
157 input dram_Ch${c}_que_addr_bank_low_sel PSAMPLE;
158 input dram_Ch${c}_que_init PSAMPLE;
159 input [3:0] dram_Ch${c}_que_data_del_cnt PSAMPLE;
160 input dram_Ch${c}_dram_io_pad_clk_inv PSAMPLE;
161 input [1:0] dram_Ch${c}_dram_io_ptr_clk_inv PSAMPLE;
162 input dram_Ch${c}_que_wr_mode_reg_done PSAMPLE;
163 input dram_Ch${c}_que_init_status_reg PSAMPLE;
164 input [3:0] dram_Ch${c}_que_dimms_present PSAMPLE;
165 input dram_Ch${c}_que_dbg_trig_en PSAMPLE;
166 input [22:0]dram_Ch${c}_que_err_sts_reg PSAMPLE;
167 input [35:0]dram_Ch${c}_que_err_addr_reg PSAMPLE;
168 input dram_Ch${c}_err_inj_reg PSAMPLE;
169 input dram_Ch${c}_sshot_err_reg PSAMPLE;
170// input [1:0] dram_Ch${c}_que_err_cnt PSAMPLE;
171 input [35:0]dram_Ch${c}_que_err_loc PSAMPLE;
172 input dram_Ch${c}_que_l2if_ack_vld PSAMPLE;
173 input dram_Ch${c}_que_l2if_nack_vld PSAMPLE;
174 input [8:0] dram_Ch${c}_l2b0_rd_adr_info_hi PSAMPLE;
175 input [8:0] dram_Ch${c}_l2b0_wr_adr_info_hi PSAMPLE;
176 input [8:0] dram_Ch${c}_l2b0_rd_adr_info_lo PSAMPLE;
177 input [8:0] dram_Ch${c}_l2b0_wr_adr_info_lo PSAMPLE;
178
179 input [8:0] dram_Ch${c}_l2b1_rd_adr_info_hi PSAMPLE;
180 input [8:0] dram_Ch${c}_l2b1_wr_adr_info_hi PSAMPLE;
181 input [8:0] dram_Ch${c}_l2b1_rd_adr_info_lo PSAMPLE;
182 input [8:0] dram_Ch${c}_l2b1_wr_adr_info_lo PSAMPLE;
183 input [7:0] dram_Ch${c}_perf_cntl PSAMPLE;
184 input dram_Ch${c}_cnt0_sticky_bit PSAMPLE;
185 input dram_Ch${c}_cnt1_sticky_bit PSAMPLE;
186
187
188 input [3:0] dram_Ch${c}_dp_pioson_l2_data PSAMPLE;
189 input [1:0] dram_Ch${c}_dp_pioson_l2_chunk PSAMPLE;
190
191// input [2:0] dram_Ch${c}_que_wl_addr_cnt0 PSAMPLE;
192// input [2:0] dram_Ch${c}_que_wl_addr_cnt1 PSAMPLE;
193// input dram_Ch${c}_que_wl_data_addr0_load_cas2 PSAMPLE;
194// input dram_Ch${c}_que_wl_data_addr0_load PSAMPLE;
195// input dram_Ch${c}_que_wl_data_addr1_load PSAMPLE;
196
197
198. for ( $i = 0; $i < 8; $i++ ) {
199 input [10:0] dram_Ch${c}_l2b0_rd_q_cntr_${i} PSAMPLE;
200 input [10:0] dram_Ch${c}_l2b0_wr_q_cntr_${i} PSAMPLE;
201 input [13:0] dram_Ch${c}_l2b0_rd_req_ack_cntr_${i} PSAMPLE;
202 input [10:0] dram_Ch${c}_l2b1_rd_q_cntr_${i} PSAMPLE;
203 input [10:0] dram_Ch${c}_l2b1_wr_q_cntr_${i} PSAMPLE;
204 input [13:0] dram_Ch${c}_l2b1_rd_req_ack_cntr_${i} PSAMPLE;
205
206.}
207 input [10:0] dram_Ch${c}_l2b0_wr_req_ack_cntr PSAMPLE;
208 input [10:0] dram_Ch${c}_l2b1_wr_req_ack_cntr PSAMPLE;
209. for ( $ch = 0; $ch < 4; $ch++ ) {
210. for ( $i = 0; $i < 8; $i++ ) {
211 input [10:0] dram_Ch${c}_cs${ch}_bank_req_cntr_${i} PSAMPLE;
212.}
213.}
214 input dram_Ch${c}_drif0_raw_hazard PSAMPLE;
215 input dram_Ch${c}_drif1_raw_hazard PSAMPLE;
216
217 input dram_Ch${c}_drif_ref_go PSAMPLE;
218 input [4:0] dram_Ch${c}_drif_refresh_rank PSAMPLE;
219
220 input dram_Ch${c}_drif_single_channel_mode PSAMPLE;
221 input [167:0] dram_Ch${c}_fbd1_data PSAMPLE;
222
223 input dram_Ch${c}_fbdic_fast_reset PSAMPLE;
224 input [2:0] dram_Ch${c}_fbdic_fbd_state PSAMPLE;
225
226 input dram_Ch${c}_fbdic_sync_frame_req PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_sync_frame_req";
227 input dram_Ch${c}_fbdic_scr_frame_req PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_scr_frame_req";
228 input [2:0] dram_Ch${c}_drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_cmd_a";
229 input [23:0] dram_Ch${c}_fbdic_a_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_a_cmd_in";
230 input [23:0] dram_Ch${c}_fbdic_sync_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_sync_cmd_a";
231 input [23:0] dram_Ch${c}_fbdic_scr_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_soft_chnl_reset_cmd";
232 input [23:0] dram_Ch${c}_fbdic_act_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_act_cmd_a";
233 input [23:0] dram_Ch${c}_fbdic_rdwr_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_rd_wr_cmd_a";
234 input dram_Ch${c}_fbdic_config_reg_write PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_config_reg_write";
235 input dram_Ch${c}_fbdic_config_reg_read PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_config_reg_read";
236 input dram_Ch${c}_fbdic_issue_cke_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_issue_cke_cmd";
237 input [2:0] dram_Ch${c}_drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_cmd_b";
238 input [2:0] dram_Ch${c}_drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_addr_b";
239 input [2:0] dram_Ch${c}_drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_cmd_c";
240 input [2:0] dram_Ch${c}_drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_addr_c";
241 input [31:0] dram_Ch${c}_fbdic_cnfgreg_wr PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_cnfgreg_wr_data";
242 input [23:0] dram_Ch${c}_fbdic_upcke_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_upper_cke_cmd";
243 input [35:0] dram_Ch${c}_fbdic_c_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_c_cmd";
244 input [2:0] dram_Ch${c}_drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_dimm_a";
245 input [2:0] dram_Ch${c}_drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_dimm_b";
246 input [2:0] dram_Ch${c}_drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_dimm_c";
247 input [2:0] dram_Ch${c}_drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_bank_a";
248 input [2:0] dram_Ch${c}_drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_bank_b";
249 input [2:0] dram_Ch${c}_drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_bank_c";
250 input dram_Ch${c}_drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_rank_a";
251 input dram_Ch${c}_drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_rank_b";
252 input dram_Ch${c}_drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_rank_c";
253 input dram_Ch${c}_l0s_enable PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_l0s_enable";
254 input dram_Ch${c}_l0s_stall PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_l0s_stall";
255 input [13:0] dram_Ch${c}_ts0_hdr_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_ts0_hdr_match";
256 input [13:0] dram_Ch${c}_ts0_hdr_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_ts0_hdr_match";
257 input [11:0] dram_Ch${c}_sts_par_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_status_parity";
258 input [11:0] dram_Ch${c}_sts_par_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_status_parity";
259 input [13:0] dram_Ch${c}_idle_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_idle_match";
260 input [13:0] dram_Ch${c}_idle_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_idle_match";
261 input [13:0] dram_Ch${c}_alrt_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_alert_match";
262 input [13:0] dram_Ch${c}_alrt_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_alert_match";
263 input [11:0] dram_Ch${c}_alrt_assrt_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_alert_asserted";
264 input [11:0] dram_Ch${c}_alrt_assrt_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_alert_asserted";
265 input [11:0] dram_Ch${c}_nbde_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_nbde";
266 input [11:0] dram_Ch${c}_nbde_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_nbde";
267 input [1:0] dram_Ch${c}_fbdic_f PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_f";
268 input [71:0] dram_Ch${c}_bc_cmd_d0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdiwr.fbdiwr_bc_cmd_data0";
269 input [71:0] dram_Ch${c}_bc_cmd_d1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdiwr.fbdiwr_bc_cmd_data1";
270 input [143:0] dram_Ch${c}_wrdp PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdiwr.wrdp_data";
271 input [34:0] dram_Ch${c}_fail_over_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_fail_over_mask";
272 input dram_Ch${c}_fail_over_mode PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_fail_over_mode";
273 input dram_Ch${c}_fbdic0_sb_failover PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic0_sb_failover";
274 input [8:0] dram_Ch${c}_fbdic0_sb_failover_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic0_sb_failover_mask";
275 input dram_Ch${c}_fbdic0_nb_failover PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic0_nb_failover";
276 input [12:0] dram_Ch${c}_fbdic0_nb_failover_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic0_nb_failover_mask";
277 input dram_Ch${c}_fbdic1_sb_failover PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic1_sb_failover";
278 input [8:0] dram_Ch${c}_fbdic1_sb_failover_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic1_sb_failover_mask";
279 input dram_Ch${c}_fbdic1_nb_failover PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic1_nb_failover";
280 input [12:0] dram_Ch${c}_fbdic1_nb_failover_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic1_nb_failover_mask";
281 input [15:0] dram_Ch${c}_err_inj_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.err_inj_ecc";
282 input [3:0] dram_Ch${c}_wecc0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.wecc0";
283 input [3:0] dram_Ch${c}_wecc1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.wecc1";
284 input [3:0] dram_Ch${c}_wecc2 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.wecc2";
285 input [3:0] dram_Ch${c}_wecc3 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.wecc3";
286 input dram_Ch${c}_l2poison_qw PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.l2poison_qw";
287
288.}
289
290. foreach $drc ( @DRC_STR ) {
291
292// ***********************************************************
293// SIGNALS FOR channel_$drc
294// ***********************************************************
295. &coreSignals( $drc );
296. }
297}
298
299interface dram_coverage_ifc_core_clk
300{
301 // Common & Clock Signals
302 input cmp_clk CLOCK ;
303 input [31:0] l2t0_mcu_addr_38to7 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_addr_39to7";
304 input [31:0] l2t1_mcu_addr_38to7 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t1_mcu_addr_39to7";
305 input [2:0] l2t0_mcu_rd_req_id PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_rd_req_id";
306 input [2:0] l2t1_mcu_rd_req_id PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t1_mcu_rd_req_id";
307 input [2:0] mcu_l2t0_rd_req_id_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_rd_req_id_r0";
308 input [2:0] mcu_l2t1_rd_req_id_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_rd_req_id_r0";
309 input mcu_l2t0_rd_ack PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_rd_ack";
310 input mcu_l2t0_rd_ack1 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_rd_ack";
311 input mcu_l2t1_rd_ack PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_rd_ack";
312 input mcu_l2t0_wr_ack PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_wr_ack";
313 input mcu_l2t0_wr_ack1 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_wr_ack";
314 input mcu_l2t1_wr_ack PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_wr_ack";
315 input l2t0_mcu_rd_req PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_rd_req";
316 input l2t0_mcu_rd_req1 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_rd_req";
317 input l2t1_mcu_rd_req PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t1_mcu_rd_req";
318 input l2t0_mcu_wr_req PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_wr_req";
319 input l2t0_mcu_wr_req1 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_wr_req";
320 input l2t1_mcu_wr_req PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t1_mcu_wr_req";
321 input l2b0_mcu_data_vld_r5 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2b0_mcu_data_vld_r5";
322 input l2b1_mcu_data_vld_r5 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2b1_mcu_data_vld_r5";
323 input mcu0_l2t0_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_data_vld_r0";
324 input mcu0_l2t1_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_data_vld_r0";
325 input mcu1_l2t0_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_data_vld_r0";
326 input mcu1_l2t1_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t1_data_vld_r0";
327 input mcu2_l2t0_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_data_vld_r0";
328 input mcu2_l2t1_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t1_data_vld_r0";
329 input mcu3_l2t0_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_data_vld_r0";
330 input mcu3_l2t1_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t1_data_vld_r0";
331 input mcu0_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_secc_err_r3";
332 input mcu0_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_secc_err_r3";
333 input mcu1_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_secc_err_r3";
334 input mcu1_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t1_secc_err_r3";
335 input mcu2_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_secc_err_r3";
336 input mcu2_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t1_secc_err_r3";
337 input mcu3_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_secc_err_r3";
338 input mcu3_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t1_secc_err_r3";
339 input mcu0_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_mecc_err_r3";
340 input mcu0_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_mecc_err_r3";
341 input mcu1_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_mecc_err_r3";
342 input mcu1_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t1_mecc_err_r3";
343 input mcu2_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_mecc_err_r3";
344 input mcu2_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t1_mecc_err_r3";
345 input mcu3_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_mecc_err_r3";
346 input mcu3_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t1_mecc_err_r3";
347 input mcu0_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_scb_secc_err";
348 input mcu1_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_scb_secc_err";
349 input mcu2_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_scb_secc_err";
350 input mcu3_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_scb_secc_err";
351 input mcu0_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_scb_mecc_err";
352 input mcu1_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_scb_mecc_err";
353 input mcu2_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_scb_mecc_err";
354 input mcu3_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_scb_mecc_err";
355
356
357 input mcu0_l2t0_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t0_data_vld_d1";
358 input mcu0_l2t0_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t0_data_vld_d2";
359 input mcu0_l2t0_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t0_data_vld_d3";
360 input mcu1_l2t0_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t0_data_vld_d1";
361 input mcu1_l2t0_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t0_data_vld_d2";
362 input mcu1_l2t0_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t0_data_vld_d3";
363 input mcu2_l2t0_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t0_data_vld_d1";
364 input mcu2_l2t0_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t0_data_vld_d2";
365 input mcu2_l2t0_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t0_data_vld_d3";
366 input mcu3_l2t0_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t0_data_vld_d1";
367 input mcu3_l2t0_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t0_data_vld_d2";
368 input mcu3_l2t0_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t0_data_vld_d3";
369 input mcu0_l2t1_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t1_data_vld_d1";
370 input mcu0_l2t1_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t1_data_vld_d2";
371 input mcu0_l2t1_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t1_data_vld_d3";
372 input mcu1_l2t1_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t1_data_vld_d1";
373 input mcu1_l2t1_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t1_data_vld_d2";
374 input mcu1_l2t1_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t1_data_vld_d3";
375 input mcu2_l2t1_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t1_data_vld_d1";
376 input mcu2_l2t1_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t1_data_vld_d2";
377 input mcu2_l2t1_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t1_data_vld_d3";
378 input mcu3_l2t1_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t1_data_vld_d1";
379 input mcu3_l2t1_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t1_data_vld_d2";
380 input mcu3_l2t1_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t1_data_vld_d3";
381
382 input mcu0_drif_refresh_req_picked PSAMPLE INPUT_SKEW verilog_node "`MCU0.drif.drif_refresh_req_picked";
383 input mcu1_drif_refresh_req_picked PSAMPLE INPUT_SKEW verilog_node "`MCU1.drif.drif_refresh_req_picked";
384 input mcu2_drif_refresh_req_picked PSAMPLE INPUT_SKEW verilog_node "`MCU2.drif.drif_refresh_req_picked";
385 input mcu3_drif_refresh_req_picked PSAMPLE INPUT_SKEW verilog_node "`MCU3.drif.drif_refresh_req_picked";
386 input dram_Ch0_dbg1_crc21 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_dbg1_crc21";
387 input dram_Ch1_dbg1_crc21 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_dbg1_crc21";
388 input dram_Ch2_dbg1_crc21 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_dbg1_crc21";
389 input dram_Ch3_dbg1_crc21 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_dbg1_crc21";
390 input dram_Ch0_dbg1_err_event PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_dbg1_err_event";
391 input dram_Ch1_dbg1_err_event PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_dbg1_err_event";
392 input dram_Ch2_dbg1_err_event PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_dbg1_err_event";
393 input dram_Ch3_dbg1_err_event PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_dbg1_err_event";
394
395
396// input cmp_diag_done PSAMPLE ;
397 input cmp_grst_l PSAMPLE ;
398. sub coreSignals_l2 {
399. my( $core_str ) = @_;
400. my $c = $core_str;
401
402 input dram_Ch${c}_l2b0_sctag_dram_rd_req PSAMPLE;
403 input dram_Ch${c}_l2b0_sctag_dram_rd_dummy_req PSAMPLE;
404 input dram_Ch${c}_l2b0_dram_sctag_rd_ack PSAMPLE;
405 input dram_Ch${c}_l2b0_sctag_dram_wr_req PSAMPLE;
406 input dram_Ch${c}_l2b0_dram_sctag_wr_ack PSAMPLE;
407 input dram_Ch${c}_l2b0_sctag_dram_data_vld PSAMPLE;
408 input dram_Ch${c}_l2b1_sctag_dram_rd_req PSAMPLE;
409 input dram_Ch${c}_l2b1_sctag_dram_rd_dummy_req PSAMPLE;
410 input dram_Ch${c}_l2b1_dram_sctag_rd_ack PSAMPLE;
411 input dram_Ch${c}_l2b1_sctag_dram_wr_req PSAMPLE;
412 input dram_Ch${c}_l2b1_dram_sctag_wr_ack PSAMPLE;
413 input dram_Ch${c}_l2b1_sctag_dram_data_vld PSAMPLE;
414 input [3:0] dram_Ch${c}_l2if_b0_rd_val PSAMPLE;
415 input [3:0] dram_Ch${c}_l2if_b1_rd_val PSAMPLE;
416 input [3:0] dram_Ch${c}_l2b0_l2if_b0_wr_val PSAMPLE;
417 input [3:0] dram_Ch${c}_l2b1_l2if_b0_wr_val PSAMPLE;
418 input [3:0] dram_Ch${c}_l2b0_l2if_b1_wr_val PSAMPLE;
419 input [3:0] dram_Ch${c}_l2b1_l2if_b1_wr_val PSAMPLE;
420 input [5:0] dram_Ch${c}_l2if_wr_b0_data_addr PSAMPLE;
421
422 input dram_Ch${c}_l2b0_dram_sctag_secc_err PSAMPLE;
423 input dram_Ch${c}_l2b0_dram_sctag_pa_err PSAMPLE;
424 input dram_Ch${c}_l2b0_dram_sctag_mecc_err PSAMPLE;
425 input dram_Ch${c}_l2b0_dram_sctag_scb_secc_err PSAMPLE;
426 input dram_Ch${c}_l2b0_dram_sctag_scb_mecc_err PSAMPLE;
427
428 input dram_Ch${c}_l2b1_dram_sctag_secc_err PSAMPLE;
429 input dram_Ch${c}_l2b1_dram_sctag_pa_err PSAMPLE;
430 input dram_Ch${c}_l2b1_dram_sctag_mecc_err PSAMPLE;
431 input dram_Ch${c}_l2b1_dram_sctag_scb_secc_err PSAMPLE;
432 input dram_Ch${c}_l2b1_dram_sctag_scb_mecc_err PSAMPLE;
433
434
435 input dram_Ch${c}_l2if_scrb_val_d2 PSAMPLE;
436 input dram_Ch${c}_l2b0_l2if_secc_err PSAMPLE;
437 input dram_Ch${c}_l2b0_l2if_mecc_err_partial PSAMPLE;
438 input dram_Ch${c}_l2b0_l2if_pa_err PSAMPLE;
439 input dram_Ch${c}_l2b1_l2if_secc_err PSAMPLE;
440 input dram_Ch${c}_l2b1_l2if_mecc_err_partial PSAMPLE;
441 input dram_Ch${c}_l2b1_l2if_pa_err PSAMPLE;
442 input [6:0] dram_Ch${c}_err_sts_reg PSAMPLE;
443 input dram_Ch${c}_l2if_err_sts_reg_en6 PSAMPLE;
444 input dram_Ch${c}_l2if_err_sts_reg_en5 PSAMPLE;
445 input dram_Ch${c}_l2if_err_sts_reg_en4 PSAMPLE;
446 input dram_Ch${c}_l2if_err_sts_reg_en3 PSAMPLE;
447 input dram_Ch${c}_l2if_err_sts_reg_en2 PSAMPLE;
448 input dram_Ch${c}_l2if_err_sts_reg_en1 PSAMPLE;
449 input dram_Ch${c}_l2if_err_sts_reg_en0 PSAMPLE;
450 input dram_Ch${c}_l2if_err_sts_reg_en PSAMPLE;
451 input dram_Ch${c}_l2if_err_addr_reg_en PSAMPLE;
452 input dram_Ch${c}_l2if_secc_loc_en PSAMPLE;
453
454 input [7:0] dram_Ch${c}_l2if_data_ret_fifo_en PSAMPLE;
455 input [4:0] dram_Ch${c}_l2b0_cpu_wr_addr PSAMPLE;
456 input [1:0] dram_Ch${c}_l2b0_cpu_wr_en PSAMPLE;
457
458 input [4:0] dram_Ch${c}_l2b1_cpu_wr_addr PSAMPLE;
459 input [1:0] dram_Ch${c}_l2b1_cpu_wr_en PSAMPLE;
460
461 input [4:0] dram_Ch${c}_l2b0_wdq_radr PSAMPLE;
462 input dram_Ch${c}_l2b0_wdq_rd_en PSAMPLE;
463
464 input [4:0] dram_Ch${c}_l2b1_wdq_radr PSAMPLE;
465 input dram_Ch${c}_l2b1_wdq_rd_en PSAMPLE;
466
467 input dram_Ch${c}_l2b0_clspine_dram_txrd_sync PSAMPLE;
468 input dram_Ch${c}_l2b0_clspine_dram_txwr_sync PSAMPLE;
469 input dram_Ch${c}_l2b1_clspine_dram_txrd_sync PSAMPLE;
470 input dram_Ch${c}_l2b1_clspine_dram_txwr_sync PSAMPLE;
471 input [1:0] dram_rd_req_q_full_Ch${c}_rd_taken_state PSAMPLE;
472 input [1:0] dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state PSAMPLE;
473 input [1:0] dram_l2b1_wr_req_q_full_Ch${c}_wr_taken_state PSAMPLE;
474
475 input dram_Ch${c}_l2if_ucb_trig PSAMPLE;
476 input dram_Ch${c}_l2b0_mcu_data_mecc PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.l2if0.l2b_mcu_data_mecc";
477 input dram_Ch${c}_l2b1_mcu_data_mecc PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.l2if1.l2b_mcu_data_mecc";
478.}
479
480. foreach $drc ( @DRC_STR ) {
481
482// ***********************************************************
483// SIGNALS FOR channel_$drc
484// ***********************************************************
485. &coreSignals_l2( $drc );
486. }
487
488}
489
490
491
492interface dram_coverage_ifc_jbus_clk
493{
494 // Common & Clock Signals
495 input jbus_gclk CLOCK ;
496 input dram_Ch0_rd_req_vld PSAMPLE;
497 input dram_Ch0_ucb_req_pend PSAMPLE;
498 input dram_Ch0_ucb_dram_ack_busy PSAMPLE;
499 input dram_Ch0_ucb_dram_int_busy PSAMPLE;
500 input dram_Ch1_rd_req_vld PSAMPLE;
501 input dram_Ch1_ucb_req_pend PSAMPLE;
502 input dram_Ch1_ucb_dram_ack_busy PSAMPLE;
503 input dram_Ch1_ucb_dram_int_busy PSAMPLE;
504 input dram_Ch2_rd_req_vld PSAMPLE;
505 input dram_Ch2_ucb_req_pend PSAMPLE;
506 input dram_Ch2_ucb_dram_ack_busy PSAMPLE;
507 input dram_Ch2_ucb_dram_int_busy PSAMPLE;
508 input dram_Ch3_rd_req_vld PSAMPLE;
509 input dram_Ch3_ucb_req_pend PSAMPLE;
510 input dram_Ch3_ucb_dram_ack_busy PSAMPLE;
511 input dram_Ch3_ucb_dram_int_busy PSAMPLE;
512 input dram_Ch0_mcu_ncu_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_ncu_ecc";
513 input dram_Ch1_mcu_ncu_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_ncu_ecc";
514 input dram_Ch2_mcu_ncu_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_ncu_ecc";
515 input dram_Ch3_mcu_ncu_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_ncu_ecc";
516 input dram_Ch0_mcu_ncu_fbr PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_ncu_fbr";
517 input dram_Ch1_mcu_ncu_fbr PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_ncu_fbr";
518 input dram_Ch2_mcu_ncu_fbr PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_ncu_fbr";
519 input dram_Ch3_mcu_ncu_fbr PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_ncu_fbr";
520
521. sub coreSignals_jbus {
522. my( $core_str ) = @_;
523. my $c = $core_str;
524 input [4:0] dram_Ch${c}_dbg1_rdreq_out PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_rd_req_out";
525 input [3:0] dram_Ch${c}_dbg1_rdreq_in_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_rd_req_in_0";
526 input [3:0] dram_Ch${c}_dbg1_rdreq_in_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_rd_req_in_1";
527 input [1:0] dram_Ch${c}_dbg1_wrreq_out PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_wr_req_out";
528 input dram_Ch${c}_dbg1_wrreq_in_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_wr_req_in_0";
529 input dram_Ch${c}_dbg1_wrreq_in_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_wr_req_in_1";
530 input dram_Ch${c}_dbg1_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_mecc_err";
531 input dram_Ch${c}_dbg1_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_secc_err";
532 input dram_Ch${c}_dbg1_fbd_err PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_fbd_err";
533 input dram_Ch${c}_dbg1_err_mode PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_err_mode";
534 input dram_Ch${c}_ucb_serdes_dtm PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.ucb.ucb_serdes_dtm";
535. }
536
537. foreach $drc ( @DRC_STR ) {
538
539// ***********************************************************
540// SIGNALS FOR channel_$drc
541// ***********************************************************
542. &coreSignals_jbus( $drc );
543. }
544}
545
546// ***********************************************************
547// SIGNALS FOR RAS VCOs - MAQ
548// ***********************************************************
549. for($mcu_no=0; $mcu_no<1; $mcu_no++)
550. {
551interface l2_to_mcu${mcu_no}_ras_intf
552{
553input clk CLOCK verilog_node "`MCU${mcu_no}.gclk";
554input l2b0_mcu_data_mecc_r5 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.l2b0_mcu_data_mecc_r5";
555input l2b1_mcu_data_mecc_r5 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.l2b1_mcu_data_mecc_r5";
556}
557
558interface mcu${mcu_no}_to_l2_ras_intf
559{
560input clk CLOCK verilog_node "`MCU${mcu_no}.gclk";
561input mcu_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t0_scb_mecc_err";
562input mcu_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t0_scb_secc_err";
563input mcu_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t0_mecc_err_r3";
564input mcu_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t0_secc_err_r3";
565
566input mcu_l2t1_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t1_scb_mecc_err";
567input mcu_l2t1_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t1_scb_secc_err";
568input mcu_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t1_mecc_err_r3";
569input mcu_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t1_secc_err_r3";
570}
571
572interface mcu${mcu_no}_ESR_intf
573{
574input clk CLOCK verilog_node "`MCU${mcu_no}.gclk";
575input rdpctl_meu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_meu_error";
576input rdpctl_mec_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_mec_error";
577input rdpctl_dac_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dac_error";
578input rdpctl_dau_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dau_error";
579input rdpctl_dsc_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dsc_error";
580input rdpctl_dsu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dsu_error";
581input rdpctl_dbu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dbu_error";
582input rdpctl_meb_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_meb_error";
583input rdpctl_fbu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_fbu_error";
584input rdpctl_fbr_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_fbr_error";
585}
586
587interface mcu${mcu_no}_FBD_Error_Synd_intf
588{
589input clk CLOCK verilog_node "`MCU${mcu_no}.dr_gclk";
590input fbdic_mcu_synd_valid PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[30]";
591input fbdic_mcu_synd_c PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[0]";
592input fbdic_mcu_synd_afe PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[1]";
593input fbdic_mcu_synd_aa PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[2]";
594input fbdic_mcu_synd_sfpe PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[3]";
595input fbu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_fbu_error";
596input fbr_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_fbr_error";
597}
598. }
599
600#endif
601
602
603
Full OpenSPARC design & verification tarball including full HDL.