// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mcusat_cov.if.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
#inc "mcusat_cov_inc.pal";
#include <vera_defines.vrh>
interface dram_coverage_ifc_link_clk
input sclk CLOCK verilog_node "tb_top.crc_errinject_top.sb_crc_errinj0a_p.link_clk";
interface dram_coverage_ifc_dram_clk
// Common & Clock Signals
input dram_rst_l PSAMPLE ;
input dram_Ch0_pt_selfrsh PSAMPLE;
input dram_Ch1_pt_selfrsh PSAMPLE;
input dram_Ch2_pt_selfrsh PSAMPLE;
input dram_Ch3_pt_selfrsh PSAMPLE;
input dram_Ch0_pt_blk_new_openbank_d1 PSAMPLE;
input dram_Ch1_pt_blk_new_openbank_d1 PSAMPLE;
input dram_Ch2_pt_blk_new_openbank_d1 PSAMPLE;
input dram_Ch3_pt_blk_new_openbank_d1 PSAMPLE;
input [9:0] ps_in PSAMPLE INPUT_SKEW verilog_node "tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_in";
input [9:0] ps_out PSAMPLE INPUT_SKEW verilog_node "tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_out";
// input sclk PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu_fmon.sclk";
input [4:0] dram_Ch${c}_que_pos PSAMPLE;
input dram_Ch${c}_l2b0_rd_req PSAMPLE;
input [7:0] dram_Ch${c}_l2b0_rd_que_wr_ptr PSAMPLE;
input [7:0] dram_Ch${c}_l2b0_rd_que_rd_ptr PSAMPLE;
input [3:0] dram_Ch${c}_l2b0_rd_q_cnt PSAMPLE;
input dram_Ch${c}_l2b0_rd_q_full PSAMPLE;
input [3:0] dram_Ch${c}_l2b0_rd_colps_q_cnt PSAMPLE;
input dram_Ch${c}_l2b0_rd_colps_q_full PSAMPLE;
input dram_Ch${c}_l2b0_rd_q_empty PSAMPLE;
input dram_Ch${c}_l2b0_rd_colps_q_empty PSAMPLE;
input dram_Ch${c}_l2b1_rd_req PSAMPLE;
input [7:0] dram_Ch${c}_l2b1_rd_que_wr_ptr PSAMPLE;
input [7:0] dram_Ch${c}_l2b1_rd_que_rd_ptr PSAMPLE;
input [3:0] dram_Ch${c}_l2b1_rd_q_cnt PSAMPLE;
input dram_Ch${c}_l2b1_rd_q_full PSAMPLE;
input [3:0] dram_Ch${c}_l2b1_rd_colps_q_cnt PSAMPLE;
input dram_Ch${c}_l2b1_rd_colps_q_full PSAMPLE;
input dram_Ch${c}_l2b1_rd_q_empty PSAMPLE;
input dram_Ch${c}_l2b1_rd_colps_q_empty PSAMPLE;
input dram_Ch${c}_l2b1_wr_req PSAMPLE;
input [7:0] dram_Ch${c}_l2b1_wr_que_wr_ptr PSAMPLE;
input [7:0] dram_Ch${c}_l2b1_wr_que_rd_ptr PSAMPLE;
input [7:0] dram_Ch${c}_l2b1_wr_que_rd_ptr_arb PSAMPLE;
input [3:0] dram_Ch${c}_l2b1_wr_q_cnt PSAMPLE;
input dram_Ch${c}_l2b1_wr_q_full PSAMPLE;
input [3:0] dram_Ch${c}_l2b1_wr_colps_q_cnt PSAMPLE;
input dram_Ch${c}_l2b1_wr_colps_q_full PSAMPLE;
input dram_Ch${c}_l2b1_wr_q_empty PSAMPLE;
input dram_Ch${c}_l2b1_wr_colps_q_empty PSAMPLE;
input dram_Ch${c}_l2b0_wr_req PSAMPLE;
input [7:0] dram_Ch${c}_l2b0_wr_que_wr_ptr PSAMPLE;
input [7:0] dram_Ch${c}_l2b0_wr_que_rd_ptr PSAMPLE;
input [7:0] dram_Ch${c}_l2b0_wr_que_rd_ptr_arb PSAMPLE;
input [3:0] dram_Ch${c}_l2b0_wr_q_cnt PSAMPLE;
input dram_Ch${c}_l2b0_wr_q_full PSAMPLE;
input [3:0] dram_Ch${c}_l2b0_wr_colps_q_cnt PSAMPLE;
input dram_Ch${c}_l2b0_wr_colps_q_full PSAMPLE;
input dram_Ch${c}_l2b0_wr_q_empty PSAMPLE;
input dram_Ch${c}_l2b0_wr_colps_q_empty PSAMPLE;
input [1:0] dram_Ch${c}_refresh_all_clr_mon_state PSAMPLE;
input [7:0] dram_Ch${c}_que_cas_valid PSAMPLE;
input [4:0] dram_Ch${c}_que_mem_addr PSAMPLE;
input dram_Ch${c}_que_pick_wr_first PSAMPLE;
input dram_Ch${c}_l2b0_rd_req_2a_addr_vld PSAMPLE;
input dram_Ch${c}_l2b0_wr_req_2a_addr_vld PSAMPLE;
input dram_Ch${c}_scrb_req_2a_addr_vld PSAMPLE;
input dram_Ch${c}_l2b1_rd_req_2a_addr_vld PSAMPLE;
input dram_Ch${c}_l2b1_wr_req_2a_addr_vld PSAMPLE;
input dram_Ch${c}_que_rd_wr_hit PSAMPLE;
input [3:0] dram_Ch${c}_ras_pend_cnt PSAMPLE;
input [7:0] dram_Ch${c}_que_ras_picked PSAMPLE;
input [15:0] dram_Ch${c}_ras_picked PSAMPLE;
input [3:0] dram_Ch${c}_cas_pend_cnt PSAMPLE;
input [7:0] dram_Ch${c}_que_cas_picked PSAMPLE;
input [15:0] dram_Ch${c}_que_l2req_valid PSAMPLE;
input [15:0] dram_Ch${c}_scrb_indx_val PSAMPLE;
input [8:0] dram_Ch${c}_chip_config_reg PSAMPLE;
input [2:0] dram_Ch${c}_mode_reg PSAMPLE;
input [3:0] dram_Ch${c}_rrd_reg PSAMPLE;
input [4:0] dram_Ch${c}_rc_reg PSAMPLE;
input [3:0] dram_Ch${c}_rcd_reg PSAMPLE;
input [3:0] dram_Ch${c}_wtr_dly_reg PSAMPLE;
input [3:0] dram_Ch${c}_rtw_dly_reg PSAMPLE;
input [3:0] dram_Ch${c}_rtp_reg PSAMPLE;
input [3:0] dram_Ch${c}_ras_reg PSAMPLE;
input [3:0] dram_Ch${c}_rp_reg PSAMPLE;
input [3:0] dram_Ch${c}_wr_reg PSAMPLE;
input [1:0] dram_Ch${c}_mrd_reg PSAMPLE;
input [1:0] dram_Ch${c}_iwtr_reg PSAMPLE;
input [14:0]dram_Ch${c}_ext_mode_reg2 PSAMPLE;
input [14:0]dram_Ch${c}_ext_mode_reg1 PSAMPLE;
input [14:0]dram_Ch${c}_ext_mode_reg3 PSAMPLE;
input dram_Ch${c}_que_eight_bank_mode PSAMPLE;
input dram_Ch${c}_que_rank1_present PSAMPLE;
input dram_Ch${c}_que_channel_disabled PSAMPLE;
input dram_Ch${c}_que_addr_bank_low_sel PSAMPLE;
input dram_Ch${c}_que_init PSAMPLE;
input [3:0] dram_Ch${c}_que_data_del_cnt PSAMPLE;
input dram_Ch${c}_dram_io_pad_clk_inv PSAMPLE;
input [1:0] dram_Ch${c}_dram_io_ptr_clk_inv PSAMPLE;
input dram_Ch${c}_que_wr_mode_reg_done PSAMPLE;
input dram_Ch${c}_que_init_status_reg PSAMPLE;
input [3:0] dram_Ch${c}_que_dimms_present PSAMPLE;
input dram_Ch${c}_que_dbg_trig_en PSAMPLE;
input [22:0]dram_Ch${c}_que_err_sts_reg PSAMPLE;
input [35:0]dram_Ch${c}_que_err_addr_reg PSAMPLE;
input dram_Ch${c}_err_inj_reg PSAMPLE;
input dram_Ch${c}_sshot_err_reg PSAMPLE;
// input [1:0] dram_Ch${c}_que_err_cnt PSAMPLE;
input [35:0]dram_Ch${c}_que_err_loc PSAMPLE;
input dram_Ch${c}_que_l2if_ack_vld PSAMPLE;
input dram_Ch${c}_que_l2if_nack_vld PSAMPLE;
input [8:0] dram_Ch${c}_l2b0_rd_adr_info_hi PSAMPLE;
input [8:0] dram_Ch${c}_l2b0_wr_adr_info_hi PSAMPLE;
input [8:0] dram_Ch${c}_l2b0_rd_adr_info_lo PSAMPLE;
input [8:0] dram_Ch${c}_l2b0_wr_adr_info_lo PSAMPLE;
input [8:0] dram_Ch${c}_l2b1_rd_adr_info_hi PSAMPLE;
input [8:0] dram_Ch${c}_l2b1_wr_adr_info_hi PSAMPLE;
input [8:0] dram_Ch${c}_l2b1_rd_adr_info_lo PSAMPLE;
input [8:0] dram_Ch${c}_l2b1_wr_adr_info_lo PSAMPLE;
input [7:0] dram_Ch${c}_perf_cntl PSAMPLE;
input dram_Ch${c}_cnt0_sticky_bit PSAMPLE;
input dram_Ch${c}_cnt1_sticky_bit PSAMPLE;
input [3:0] dram_Ch${c}_dp_pioson_l2_data PSAMPLE;
input [1:0] dram_Ch${c}_dp_pioson_l2_chunk PSAMPLE;
// input [2:0] dram_Ch${c}_que_wl_addr_cnt0 PSAMPLE;
// input [2:0] dram_Ch${c}_que_wl_addr_cnt1 PSAMPLE;
// input dram_Ch${c}_que_wl_data_addr0_load_cas2 PSAMPLE;
// input dram_Ch${c}_que_wl_data_addr0_load PSAMPLE;
// input dram_Ch${c}_que_wl_data_addr1_load PSAMPLE;
. for ( $i = 0; $i < 8; $i++ ) {
input [10:0] dram_Ch${c}_l2b0_rd_q_cntr_${i} PSAMPLE;
input [10:0] dram_Ch${c}_l2b0_wr_q_cntr_${i} PSAMPLE;
input [13:0] dram_Ch${c}_l2b0_rd_req_ack_cntr_${i} PSAMPLE;
input [10:0] dram_Ch${c}_l2b1_rd_q_cntr_${i} PSAMPLE;
input [10:0] dram_Ch${c}_l2b1_wr_q_cntr_${i} PSAMPLE;
input [13:0] dram_Ch${c}_l2b1_rd_req_ack_cntr_${i} PSAMPLE;
input [10:0] dram_Ch${c}_l2b0_wr_req_ack_cntr PSAMPLE;
input [10:0] dram_Ch${c}_l2b1_wr_req_ack_cntr PSAMPLE;
. for ( $ch = 0; $ch < 4; $ch++ ) {
. for ( $i = 0; $i < 8; $i++ ) {
input [10:0] dram_Ch${c}_cs${ch}_bank_req_cntr_${i} PSAMPLE;
input dram_Ch${c}_drif0_raw_hazard PSAMPLE;
input dram_Ch${c}_drif1_raw_hazard PSAMPLE;
input dram_Ch${c}_drif_ref_go PSAMPLE;
input [4:0] dram_Ch${c}_drif_refresh_rank PSAMPLE;
input dram_Ch${c}_drif_single_channel_mode PSAMPLE;
input [167:0] dram_Ch${c}_fbd1_data PSAMPLE;
input dram_Ch${c}_fbdic_fast_reset PSAMPLE;
input [2:0] dram_Ch${c}_fbdic_fbd_state PSAMPLE;
input dram_Ch${c}_fbdic_sync_frame_req PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_sync_frame_req";
input dram_Ch${c}_fbdic_scr_frame_req PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_scr_frame_req";
input [2:0] dram_Ch${c}_drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_cmd_a";
input [23:0] dram_Ch${c}_fbdic_a_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_a_cmd_in";
input [23:0] dram_Ch${c}_fbdic_sync_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_sync_cmd_a";
input [23:0] dram_Ch${c}_fbdic_scr_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_soft_chnl_reset_cmd";
input [23:0] dram_Ch${c}_fbdic_act_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_act_cmd_a";
input [23:0] dram_Ch${c}_fbdic_rdwr_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_rd_wr_cmd_a";
input dram_Ch${c}_fbdic_config_reg_write PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_config_reg_write";
input dram_Ch${c}_fbdic_config_reg_read PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_config_reg_read";
input dram_Ch${c}_fbdic_issue_cke_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_issue_cke_cmd";
input [2:0] dram_Ch${c}_drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_cmd_b";
input [2:0] dram_Ch${c}_drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_addr_b";
input [2:0] dram_Ch${c}_drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_cmd_c";
input [2:0] dram_Ch${c}_drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.drif_dram_addr_c";
input [31:0] dram_Ch${c}_fbdic_cnfgreg_wr PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_cnfgreg_wr_data";
input [23:0] dram_Ch${c}_fbdic_upcke_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_upper_cke_cmd";
input [35:0] dram_Ch${c}_fbdic_c_cmd PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_c_cmd";
input [2:0] dram_Ch${c}_drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_dimm_a";
input [2:0] dram_Ch${c}_drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_dimm_b";
input [2:0] dram_Ch${c}_drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_dimm_c";
input [2:0] dram_Ch${c}_drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_bank_a";
input [2:0] dram_Ch${c}_drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_bank_b";
input [2:0] dram_Ch${c}_drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_bank_c";
input dram_Ch${c}_drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_rank_a";
input dram_Ch${c}_drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_rank_b";
input dram_Ch${c}_drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_dram_rank_c";
input dram_Ch${c}_l0s_enable PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_l0s_enable";
input dram_Ch${c}_l0s_stall PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_l0s_stall";
input [13:0] dram_Ch${c}_ts0_hdr_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_ts0_hdr_match";
input [13:0] dram_Ch${c}_ts0_hdr_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_ts0_hdr_match";
input [11:0] dram_Ch${c}_sts_par_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_status_parity";
input [11:0] dram_Ch${c}_sts_par_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_status_parity";
input [13:0] dram_Ch${c}_idle_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_idle_match";
input [13:0] dram_Ch${c}_idle_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_idle_match";
input [13:0] dram_Ch${c}_alrt_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_alert_match";
input [13:0] dram_Ch${c}_alrt_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_alert_match";
input [11:0] dram_Ch${c}_alrt_assrt_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_alert_asserted";
input [11:0] dram_Ch${c}_alrt_assrt_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_alert_asserted";
input [11:0] dram_Ch${c}_nbde_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw0_nbde";
input [11:0] dram_Ch${c}_nbde_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.lndskw1_nbde";
input [1:0] dram_Ch${c}_fbdic_f PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic_f";
input [71:0] dram_Ch${c}_bc_cmd_d0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdiwr.fbdiwr_bc_cmd_data0";
input [71:0] dram_Ch${c}_bc_cmd_d1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdiwr.fbdiwr_bc_cmd_data1";
input [143:0] dram_Ch${c}_wrdp PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdiwr.wrdp_data";
input [34:0] dram_Ch${c}_fail_over_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_fail_over_mask";
input dram_Ch${c}_fail_over_mode PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.drif.drif_fail_over_mode";
input dram_Ch${c}_fbdic0_sb_failover PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic0_sb_failover";
input [8:0] dram_Ch${c}_fbdic0_sb_failover_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic0_sb_failover_mask";
input dram_Ch${c}_fbdic0_nb_failover PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic0_nb_failover";
input [12:0] dram_Ch${c}_fbdic0_nb_failover_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic0_nb_failover_mask";
input dram_Ch${c}_fbdic1_sb_failover PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic1_sb_failover";
input [8:0] dram_Ch${c}_fbdic1_sb_failover_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic1_sb_failover_mask";
input dram_Ch${c}_fbdic1_nb_failover PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic1_nb_failover";
input [12:0] dram_Ch${c}_fbdic1_nb_failover_mask PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.fbdic.fbdic1_nb_failover_mask";
input [15:0] dram_Ch${c}_err_inj_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.err_inj_ecc";
input [3:0] dram_Ch${c}_wecc0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.wecc0";
input [3:0] dram_Ch${c}_wecc1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.wecc1";
input [3:0] dram_Ch${c}_wecc2 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.wecc2";
input [3:0] dram_Ch${c}_wecc3 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.wecc3";
input dram_Ch${c}_l2poison_qw PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.wrdp.l2poison_qw";
. foreach $drc ( @DRC_STR ) {
// ***********************************************************
// SIGNALS FOR channel_$drc
// ***********************************************************
interface dram_coverage_ifc_core_clk
// Common & Clock Signals
input [31:0] l2t0_mcu_addr_38to7 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_addr_39to7";
input [31:0] l2t1_mcu_addr_38to7 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t1_mcu_addr_39to7";
input [2:0] l2t0_mcu_rd_req_id PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_rd_req_id";
input [2:0] l2t1_mcu_rd_req_id PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t1_mcu_rd_req_id";
input [2:0] mcu_l2t0_rd_req_id_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_rd_req_id_r0";
input [2:0] mcu_l2t1_rd_req_id_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_rd_req_id_r0";
input mcu_l2t0_rd_ack PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_rd_ack";
input mcu_l2t0_rd_ack1 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_rd_ack";
input mcu_l2t1_rd_ack PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_rd_ack";
input mcu_l2t0_wr_ack PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_wr_ack";
input mcu_l2t0_wr_ack1 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_wr_ack";
input mcu_l2t1_wr_ack PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_wr_ack";
input l2t0_mcu_rd_req PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_rd_req";
input l2t0_mcu_rd_req1 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_rd_req";
input l2t1_mcu_rd_req PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t1_mcu_rd_req";
input l2t0_mcu_wr_req PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_wr_req";
input l2t0_mcu_wr_req1 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t0_mcu_wr_req";
input l2t1_mcu_wr_req PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2t1_mcu_wr_req";
input l2b0_mcu_data_vld_r5 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2b0_mcu_data_vld_r5";
input l2b1_mcu_data_vld_r5 PSAMPLE INPUT_SKEW verilog_node "`MCU0.l2b1_mcu_data_vld_r5";
input mcu0_l2t0_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_data_vld_r0";
input mcu0_l2t1_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_data_vld_r0";
input mcu1_l2t0_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_data_vld_r0";
input mcu1_l2t1_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t1_data_vld_r0";
input mcu2_l2t0_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_data_vld_r0";
input mcu2_l2t1_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t1_data_vld_r0";
input mcu3_l2t0_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_data_vld_r0";
input mcu3_l2t1_data_vld_r0 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t1_data_vld_r0";
input mcu0_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_secc_err_r3";
input mcu0_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_secc_err_r3";
input mcu1_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_secc_err_r3";
input mcu1_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t1_secc_err_r3";
input mcu2_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_secc_err_r3";
input mcu2_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t1_secc_err_r3";
input mcu3_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_secc_err_r3";
input mcu3_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t1_secc_err_r3";
input mcu0_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_mecc_err_r3";
input mcu0_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t1_mecc_err_r3";
input mcu1_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_mecc_err_r3";
input mcu1_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t1_mecc_err_r3";
input mcu2_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_mecc_err_r3";
input mcu2_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t1_mecc_err_r3";
input mcu3_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_mecc_err_r3";
input mcu3_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t1_mecc_err_r3";
input mcu0_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_scb_secc_err";
input mcu1_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_scb_secc_err";
input mcu2_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_scb_secc_err";
input mcu3_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_scb_secc_err";
input mcu0_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_l2t0_scb_mecc_err";
input mcu1_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_l2t0_scb_mecc_err";
input mcu2_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_l2t0_scb_mecc_err";
input mcu3_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_l2t0_scb_mecc_err";
input mcu0_l2t0_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t0_data_vld_d1";
input mcu0_l2t0_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t0_data_vld_d2";
input mcu0_l2t0_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t0_data_vld_d3";
input mcu1_l2t0_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t0_data_vld_d1";
input mcu1_l2t0_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t0_data_vld_d2";
input mcu1_l2t0_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t0_data_vld_d3";
input mcu2_l2t0_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t0_data_vld_d1";
input mcu2_l2t0_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t0_data_vld_d2";
input mcu2_l2t0_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t0_data_vld_d3";
input mcu3_l2t0_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t0_data_vld_d1";
input mcu3_l2t0_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t0_data_vld_d2";
input mcu3_l2t0_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t0_data_vld_d3";
input mcu0_l2t1_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t1_data_vld_d1";
input mcu0_l2t1_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t1_data_vld_d2";
input mcu0_l2t1_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu0_l2t1_data_vld_d3";
input mcu1_l2t1_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t1_data_vld_d1";
input mcu1_l2t1_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t1_data_vld_d2";
input mcu1_l2t1_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu1_l2t1_data_vld_d3";
input mcu2_l2t1_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t1_data_vld_d1";
input mcu2_l2t1_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t1_data_vld_d2";
input mcu2_l2t1_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu2_l2t1_data_vld_d3";
input mcu3_l2t1_data_vld_d1 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t1_data_vld_d1";
input mcu3_l2t1_data_vld_d2 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t1_data_vld_d2";
input mcu3_l2t1_data_vld_d3 PSAMPLE INPUT_SKEW verilog_node "tb_top.mcu3_l2t1_data_vld_d3";
input mcu0_drif_refresh_req_picked PSAMPLE INPUT_SKEW verilog_node "`MCU0.drif.drif_refresh_req_picked";
input mcu1_drif_refresh_req_picked PSAMPLE INPUT_SKEW verilog_node "`MCU1.drif.drif_refresh_req_picked";
input mcu2_drif_refresh_req_picked PSAMPLE INPUT_SKEW verilog_node "`MCU2.drif.drif_refresh_req_picked";
input mcu3_drif_refresh_req_picked PSAMPLE INPUT_SKEW verilog_node "`MCU3.drif.drif_refresh_req_picked";
input dram_Ch0_dbg1_crc21 PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_dbg1_crc21";
input dram_Ch1_dbg1_crc21 PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_dbg1_crc21";
input dram_Ch2_dbg1_crc21 PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_dbg1_crc21";
input dram_Ch3_dbg1_crc21 PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_dbg1_crc21";
input dram_Ch0_dbg1_err_event PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_dbg1_err_event";
input dram_Ch1_dbg1_err_event PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_dbg1_err_event";
input dram_Ch2_dbg1_err_event PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_dbg1_err_event";
input dram_Ch3_dbg1_err_event PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_dbg1_err_event";
// input cmp_diag_done PSAMPLE ;
input cmp_grst_l PSAMPLE ;
input dram_Ch${c}_l2b0_sctag_dram_rd_req PSAMPLE;
input dram_Ch${c}_l2b0_sctag_dram_rd_dummy_req PSAMPLE;
input dram_Ch${c}_l2b0_dram_sctag_rd_ack PSAMPLE;
input dram_Ch${c}_l2b0_sctag_dram_wr_req PSAMPLE;
input dram_Ch${c}_l2b0_dram_sctag_wr_ack PSAMPLE;
input dram_Ch${c}_l2b0_sctag_dram_data_vld PSAMPLE;
input dram_Ch${c}_l2b1_sctag_dram_rd_req PSAMPLE;
input dram_Ch${c}_l2b1_sctag_dram_rd_dummy_req PSAMPLE;
input dram_Ch${c}_l2b1_dram_sctag_rd_ack PSAMPLE;
input dram_Ch${c}_l2b1_sctag_dram_wr_req PSAMPLE;
input dram_Ch${c}_l2b1_dram_sctag_wr_ack PSAMPLE;
input dram_Ch${c}_l2b1_sctag_dram_data_vld PSAMPLE;
input [3:0] dram_Ch${c}_l2if_b0_rd_val PSAMPLE;
input [3:0] dram_Ch${c}_l2if_b1_rd_val PSAMPLE;
input [3:0] dram_Ch${c}_l2b0_l2if_b0_wr_val PSAMPLE;
input [3:0] dram_Ch${c}_l2b1_l2if_b0_wr_val PSAMPLE;
input [3:0] dram_Ch${c}_l2b0_l2if_b1_wr_val PSAMPLE;
input [3:0] dram_Ch${c}_l2b1_l2if_b1_wr_val PSAMPLE;
input [5:0] dram_Ch${c}_l2if_wr_b0_data_addr PSAMPLE;
input dram_Ch${c}_l2b0_dram_sctag_secc_err PSAMPLE;
input dram_Ch${c}_l2b0_dram_sctag_pa_err PSAMPLE;
input dram_Ch${c}_l2b0_dram_sctag_mecc_err PSAMPLE;
input dram_Ch${c}_l2b0_dram_sctag_scb_secc_err PSAMPLE;
input dram_Ch${c}_l2b0_dram_sctag_scb_mecc_err PSAMPLE;
input dram_Ch${c}_l2b1_dram_sctag_secc_err PSAMPLE;
input dram_Ch${c}_l2b1_dram_sctag_pa_err PSAMPLE;
input dram_Ch${c}_l2b1_dram_sctag_mecc_err PSAMPLE;
input dram_Ch${c}_l2b1_dram_sctag_scb_secc_err PSAMPLE;
input dram_Ch${c}_l2b1_dram_sctag_scb_mecc_err PSAMPLE;
input dram_Ch${c}_l2if_scrb_val_d2 PSAMPLE;
input dram_Ch${c}_l2b0_l2if_secc_err PSAMPLE;
input dram_Ch${c}_l2b0_l2if_mecc_err_partial PSAMPLE;
input dram_Ch${c}_l2b0_l2if_pa_err PSAMPLE;
input dram_Ch${c}_l2b1_l2if_secc_err PSAMPLE;
input dram_Ch${c}_l2b1_l2if_mecc_err_partial PSAMPLE;
input dram_Ch${c}_l2b1_l2if_pa_err PSAMPLE;
input [6:0] dram_Ch${c}_err_sts_reg PSAMPLE;
input dram_Ch${c}_l2if_err_sts_reg_en6 PSAMPLE;
input dram_Ch${c}_l2if_err_sts_reg_en5 PSAMPLE;
input dram_Ch${c}_l2if_err_sts_reg_en4 PSAMPLE;
input dram_Ch${c}_l2if_err_sts_reg_en3 PSAMPLE;
input dram_Ch${c}_l2if_err_sts_reg_en2 PSAMPLE;
input dram_Ch${c}_l2if_err_sts_reg_en1 PSAMPLE;
input dram_Ch${c}_l2if_err_sts_reg_en0 PSAMPLE;
input dram_Ch${c}_l2if_err_sts_reg_en PSAMPLE;
input dram_Ch${c}_l2if_err_addr_reg_en PSAMPLE;
input dram_Ch${c}_l2if_secc_loc_en PSAMPLE;
input [7:0] dram_Ch${c}_l2if_data_ret_fifo_en PSAMPLE;
input [4:0] dram_Ch${c}_l2b0_cpu_wr_addr PSAMPLE;
input [1:0] dram_Ch${c}_l2b0_cpu_wr_en PSAMPLE;
input [4:0] dram_Ch${c}_l2b1_cpu_wr_addr PSAMPLE;
input [1:0] dram_Ch${c}_l2b1_cpu_wr_en PSAMPLE;
input [4:0] dram_Ch${c}_l2b0_wdq_radr PSAMPLE;
input dram_Ch${c}_l2b0_wdq_rd_en PSAMPLE;
input [4:0] dram_Ch${c}_l2b1_wdq_radr PSAMPLE;
input dram_Ch${c}_l2b1_wdq_rd_en PSAMPLE;
input dram_Ch${c}_l2b0_clspine_dram_txrd_sync PSAMPLE;
input dram_Ch${c}_l2b0_clspine_dram_txwr_sync PSAMPLE;
input dram_Ch${c}_l2b1_clspine_dram_txrd_sync PSAMPLE;
input dram_Ch${c}_l2b1_clspine_dram_txwr_sync PSAMPLE;
input [1:0] dram_rd_req_q_full_Ch${c}_rd_taken_state PSAMPLE;
input [1:0] dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state PSAMPLE;
input [1:0] dram_l2b1_wr_req_q_full_Ch${c}_wr_taken_state PSAMPLE;
input dram_Ch${c}_l2if_ucb_trig PSAMPLE;
input dram_Ch${c}_l2b0_mcu_data_mecc PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.l2if0.l2b_mcu_data_mecc";
input dram_Ch${c}_l2b1_mcu_data_mecc PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.l2if1.l2b_mcu_data_mecc";
. foreach $drc ( @DRC_STR ) {
// ***********************************************************
// SIGNALS FOR channel_$drc
// ***********************************************************
. &coreSignals_l2( $drc );
interface dram_coverage_ifc_jbus_clk
// Common & Clock Signals
input dram_Ch0_rd_req_vld PSAMPLE;
input dram_Ch0_ucb_req_pend PSAMPLE;
input dram_Ch0_ucb_dram_ack_busy PSAMPLE;
input dram_Ch0_ucb_dram_int_busy PSAMPLE;
input dram_Ch1_rd_req_vld PSAMPLE;
input dram_Ch1_ucb_req_pend PSAMPLE;
input dram_Ch1_ucb_dram_ack_busy PSAMPLE;
input dram_Ch1_ucb_dram_int_busy PSAMPLE;
input dram_Ch2_rd_req_vld PSAMPLE;
input dram_Ch2_ucb_req_pend PSAMPLE;
input dram_Ch2_ucb_dram_ack_busy PSAMPLE;
input dram_Ch2_ucb_dram_int_busy PSAMPLE;
input dram_Ch3_rd_req_vld PSAMPLE;
input dram_Ch3_ucb_req_pend PSAMPLE;
input dram_Ch3_ucb_dram_ack_busy PSAMPLE;
input dram_Ch3_ucb_dram_int_busy PSAMPLE;
input dram_Ch0_mcu_ncu_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_ncu_ecc";
input dram_Ch1_mcu_ncu_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_ncu_ecc";
input dram_Ch2_mcu_ncu_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_ncu_ecc";
input dram_Ch3_mcu_ncu_ecc PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_ncu_ecc";
input dram_Ch0_mcu_ncu_fbr PSAMPLE INPUT_SKEW verilog_node "`MCU0.mcu_ncu_fbr";
input dram_Ch1_mcu_ncu_fbr PSAMPLE INPUT_SKEW verilog_node "`MCU1.mcu_ncu_fbr";
input dram_Ch2_mcu_ncu_fbr PSAMPLE INPUT_SKEW verilog_node "`MCU2.mcu_ncu_fbr";
input dram_Ch3_mcu_ncu_fbr PSAMPLE INPUT_SKEW verilog_node "`MCU3.mcu_ncu_fbr";
input [4:0] dram_Ch${c}_dbg1_rdreq_out PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_rd_req_out";
input [3:0] dram_Ch${c}_dbg1_rdreq_in_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_rd_req_in_0";
input [3:0] dram_Ch${c}_dbg1_rdreq_in_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_rd_req_in_1";
input [1:0] dram_Ch${c}_dbg1_wrreq_out PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_wr_req_out";
input dram_Ch${c}_dbg1_wrreq_in_0 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_wr_req_in_0";
input dram_Ch${c}_dbg1_wrreq_in_1 PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_wr_req_in_1";
input dram_Ch${c}_dbg1_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_mecc_err";
input dram_Ch${c}_dbg1_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_secc_err";
input dram_Ch${c}_dbg1_fbd_err PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_fbd_err";
input dram_Ch${c}_dbg1_err_mode PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.mcu_dbg1_err_mode";
input dram_Ch${c}_ucb_serdes_dtm PSAMPLE INPUT_SKEW verilog_node "`MCU${c}.ucb.ucb_serdes_dtm";
. foreach $drc ( @DRC_STR ) {
// ***********************************************************
// SIGNALS FOR channel_$drc
// ***********************************************************
. &coreSignals_jbus( $drc );
// ***********************************************************
// SIGNALS FOR RAS VCOs - MAQ
// ***********************************************************
. for($mcu_no=0; $mcu_no<1; $mcu_no++)
interface l2_to_mcu${mcu_no}_ras_intf
input clk CLOCK verilog_node "`MCU${mcu_no}.gclk";
input l2b0_mcu_data_mecc_r5 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.l2b0_mcu_data_mecc_r5";
input l2b1_mcu_data_mecc_r5 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.l2b1_mcu_data_mecc_r5";
interface mcu${mcu_no}_to_l2_ras_intf
input clk CLOCK verilog_node "`MCU${mcu_no}.gclk";
input mcu_l2t0_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t0_scb_mecc_err";
input mcu_l2t0_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t0_scb_secc_err";
input mcu_l2t0_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t0_mecc_err_r3";
input mcu_l2t0_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t0_secc_err_r3";
input mcu_l2t1_scb_mecc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t1_scb_mecc_err";
input mcu_l2t1_scb_secc_err PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t1_scb_secc_err";
input mcu_l2t1_mecc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t1_mecc_err_r3";
input mcu_l2t1_secc_err_r3 PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.mcu_l2t1_secc_err_r3";
interface mcu${mcu_no}_ESR_intf
input clk CLOCK verilog_node "`MCU${mcu_no}.gclk";
input rdpctl_meu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_meu_error";
input rdpctl_mec_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_mec_error";
input rdpctl_dac_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dac_error";
input rdpctl_dau_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dau_error";
input rdpctl_dsc_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dsc_error";
input rdpctl_dsu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dsu_error";
input rdpctl_dbu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_dbu_error";
input rdpctl_meb_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_meb_error";
input rdpctl_fbu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_fbu_error";
input rdpctl_fbr_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_fbr_error";
interface mcu${mcu_no}_FBD_Error_Synd_intf
input clk CLOCK verilog_node "`MCU${mcu_no}.dr_gclk";
input fbdic_mcu_synd_valid PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[30]";
input fbdic_mcu_synd_c PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[0]";
input fbdic_mcu_synd_afe PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[1]";
input fbdic_mcu_synd_aa PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[2]";
input fbdic_mcu_synd_sfpe PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.fbdic.fbdic_mcu_syndrome[3]";
input fbu_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_fbu_error";
input fbr_error PSAMPLE INPUT_SKEW verilog_node "`MCU${mcu_no}.rdpctl.rdpctl_fbr_error";
projects / OpenSPARC-T2-DV / blob