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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / mcusat / mcusat_cov.vconpal
CommitLineData
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcusat_cov.vconpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#inc "mcusat_cov_inc.pal";
36////////////////////////////////////////////////////////////////////////////////
37// dram coverage signals
38////////////////////////////////////////////////////////////////////////////////
39
40// global signals
41//connect input dram_coverage_ifc_dram_clk.dram_gclk = "`TOP_MOD.mcusat_mcu_gclk" iskew -1
42//connect input dram_coverage_ifc_core_clk.cmp_clk = "`TOP_MOD.mcusat_cmp_gclk" iskew -1
43connect input dram_coverage_ifc_dram_clk.dram_gclk = "`TOP_MOD.cpu.mcu0.drl2clk" iskew -1
44connect input dram_coverage_ifc_core_clk.cmp_clk = "`TOP_MOD.cpu.mcu0.l2clk" iskew -1
45connect input dram_coverage_ifc_jbus_clk.jbus_gclk = "`TOP_MOD.cpu.mcu0.iol2clk" iskew -1
46// connect input dram_coverage_ifc_core_clk.cmp_diag_done = "`TOP_MOD.diag_done" iskew -1
47//connect input dram_coverage_ifc_core_clk.cmp_grst_l = "`TOP_MOD.rst_reg_l" iskew -1
48connect input dram_coverage_ifc_dram_clk.dram_rst_l = "${DRAM_MON_PATH}.dram_rst_l" iskew -1
49
50connect input dram_coverage_ifc_dram_clk.dram_Ch0_que_pos = "${DRAM_MON_PATH}.dram_Ch0_que_pos" iskew -1
51connect input dram_coverage_ifc_dram_clk.dram_Ch1_que_pos = "${DRAM_MON_PATH}.dram_Ch1_que_pos" iskew -1
52connect input dram_coverage_ifc_dram_clk.dram_Ch2_que_pos = "${DRAM_MON_PATH}.dram_Ch2_que_pos" iskew -1
53connect input dram_coverage_ifc_dram_clk.dram_Ch3_que_pos = "${DRAM_MON_PATH}.dram_Ch3_que_pos" iskew -1
54connect input dram_coverage_ifc_dram_clk.dram_Ch0_pt_selfrsh = "${DRAM_MON_PATH}.dram_Ch0_que_hw_selfrsh" iskew -1
55connect input dram_coverage_ifc_dram_clk.dram_Ch1_pt_selfrsh = "${DRAM_MON_PATH}.dram_Ch1_que_hw_selfrsh" iskew -1
56connect input dram_coverage_ifc_dram_clk.dram_Ch2_pt_selfrsh = "${DRAM_MON_PATH}.dram_Ch2_que_hw_selfrsh" iskew -1
57connect input dram_coverage_ifc_dram_clk.dram_Ch3_pt_selfrsh = "${DRAM_MON_PATH}.dram_Ch3_que_hw_selfrsh" iskew -1
58connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif0_raw_hazard = "`MCU0_DRIF_CTL.drif0_raw_hazard" iskew -1
59connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif1_raw_hazard = "`MCU0_DRIF_CTL.drif1_raw_hazard" iskew -1
60connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif0_raw_hazard = "`MCU1_DRIF_CTL.drif0_raw_hazard" iskew -1
61connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif1_raw_hazard = "`MCU1_DRIF_CTL.drif1_raw_hazard" iskew -1
62connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif0_raw_hazard = "`MCU2_DRIF_CTL.drif0_raw_hazard" iskew -1
63connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif1_raw_hazard = "`MCU2_DRIF_CTL.drif1_raw_hazard" iskew -1
64connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif0_raw_hazard = "`MCU3_DRIF_CTL.drif0_raw_hazard" iskew -1
65connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif1_raw_hazard = "`MCU3_DRIF_CTL.drif1_raw_hazard" iskew -1
66connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif_ref_go = "`MCU0_DRIF_CTL.drif_ref_go" iskew -1
67connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif_refresh_rank = "`MCU0_DRIF_CTL.drif_refresh_rank" iskew -1
68connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif_ref_go = "`MCU1_DRIF_CTL.drif_ref_go" iskew -1
69connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif_refresh_rank = "`MCU1_DRIF_CTL.drif_refresh_rank" iskew -1
70connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif_ref_go = "`MCU2_DRIF_CTL.drif_ref_go" iskew -1
71connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif_refresh_rank = "`MCU2_DRIF_CTL.drif_refresh_rank" iskew -1
72connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif_ref_go = "`MCU3_DRIF_CTL.drif_ref_go" iskew -1
73connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif_refresh_rank = "`MCU3_DRIF_CTL.drif_refresh_rank" iskew -1
74connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif_single_channel_mode = "`MCU0_DRIF_CTL.drif_single_channel_mode" iskew -1
75connect input dram_coverage_ifc_dram_clk.dram_Ch0_fbd1_data = "`MCU0.fbd1_data" iskew -1
76connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif_single_channel_mode = "`MCU1_DRIF_CTL.drif_single_channel_mode" iskew -1
77connect input dram_coverage_ifc_dram_clk.dram_Ch1_fbd1_data = "`MCU1.fbd1_data" iskew -1
78connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif_single_channel_mode = "`MCU2_DRIF_CTL.drif_single_channel_mode" iskew -1
79connect input dram_coverage_ifc_dram_clk.dram_Ch2_fbd1_data = "`MCU2.fbd1_data" iskew -1
80connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif_single_channel_mode = "`MCU3_DRIF_CTL.drif_single_channel_mode" iskew -1
81connect input dram_coverage_ifc_dram_clk.dram_Ch3_fbd1_data = "`MCU3.fbd1_data" iskew -1
82connect input dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_fast_reset = "`MCU0.fbdic.fbdic_fast_reset" iskew -1
83connect input dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_fbd_state = "`MCU0.fbdic.fbdic_fbd_state[2:0]" iskew -1
84connect input dram_coverage_ifc_dram_clk.dram_Ch1_fbdic_fast_reset = "`MCU1.fbdic.fbdic_fast_reset" iskew -1
85connect input dram_coverage_ifc_dram_clk.dram_Ch1_fbdic_fbd_state = "`MCU1.fbdic.fbdic_fbd_state[2:0]" iskew -1
86connect input dram_coverage_ifc_dram_clk.dram_Ch2_fbdic_fast_reset = "`MCU2.fbdic.fbdic_fast_reset" iskew -1
87connect input dram_coverage_ifc_dram_clk.dram_Ch2_fbdic_fbd_state = "`MCU2.fbdic.fbdic_fbd_state[2:0]" iskew -1
88connect input dram_coverage_ifc_dram_clk.dram_Ch3_fbdic_fast_reset = "`MCU3.fbdic.fbdic_fast_reset" iskew -1
89connect input dram_coverage_ifc_dram_clk.dram_Ch3_fbdic_fbd_state = "`MCU3.fbdic.fbdic_fbd_state[2:0]" iskew -1
90//////////
91
92connect input dram_coverage_ifc_dram_clk.dram_Ch0_pt_blk_new_openbank_d1= "${DRAM_MON_PATH}.dram_Ch0_pt_blk_new_openbank_d1" iskew -1
93connect input dram_coverage_ifc_dram_clk.dram_Ch1_pt_blk_new_openbank_d1= "${DRAM_MON_PATH}.dram_Ch1_pt_blk_new_openbank_d1" iskew -1
94connect input dram_coverage_ifc_dram_clk.dram_Ch2_pt_blk_new_openbank_d1= "${DRAM_MON_PATH}.dram_Ch2_pt_blk_new_openbank_d1" iskew -1
95connect input dram_coverage_ifc_dram_clk.dram_Ch3_pt_blk_new_openbank_d1= "${DRAM_MON_PATH}.dram_Ch3_pt_blk_new_openbank_d1" iskew -1
96
97//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch0_l2if_ucb_trig = "${MCU0_PATH}.ucb.ddr_clk_tr" iskew -1
98//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch1_l2if_ucb_trig = "${MCU1_PATH}.ucb.ddr_clk_tr" iskew -1
99//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch2_l2if_ucb_trig = "${MCU2_PATH}.ucb.ddr_clk_tr" iskew -1
100//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch3_l2if_ucb_trig = "${MCU3_PATH}.ucb.ddr_clk_tr" iskew -1
101/////////////// not done above
102
103
104connect input dram_coverage_ifc_jbus_clk.dram_Ch0_rd_req_vld = "${MCU0_PATH}.ucb.ucb_mcu_rd_req_vld0" iskew -1
105connect input dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_req_pend = "${MCU0_PATH}.ucb.ucb_req_pend" iskew -1
106connect input dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_dram_ack_busy = "${MCU0_PATH}.ucb.ucb_mcu_ack_busy" iskew -1
107connect input dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_dram_int_busy = "${MCU0_PATH}.ucb.ucb_mcu_int_busy" iskew -1
108connect input dram_coverage_ifc_jbus_clk.dram_Ch1_rd_req_vld = "${MCU1_PATH}.ucb.ucb_mcu_rd_req_vld0" iskew -1
109connect input dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_req_pend = "${MCU1_PATH}.ucb.ucb_req_pend" iskew -1
110connect input dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_dram_ack_busy = "${MCU1_PATH}.ucb.ucb_mcu_ack_busy" iskew -1
111connect input dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_dram_int_busy = "${MCU1_PATH}.ucb.ucb_mcu_int_busy" iskew -1
112connect input dram_coverage_ifc_jbus_clk.dram_Ch2_rd_req_vld = "${MCU2_PATH}.ucb.ucb_mcu_rd_req_vld0" iskew -1
113connect input dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_req_pend = "${MCU2_PATH}.ucb.ucb_req_pend" iskew -1
114connect input dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_dram_ack_busy = "${MCU2_PATH}.ucb.ucb_mcu_ack_busy" iskew -1
115connect input dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_dram_int_busy = "${MCU2_PATH}.ucb.ucb_mcu_int_busy" iskew -1
116connect input dram_coverage_ifc_jbus_clk.dram_Ch3_rd_req_vld = "${MCU3_PATH}.ucb.ucb_mcu_rd_req_vld0" iskew -1
117connect input dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_req_pend = "${MCU3_PATH}.ucb.ucb_req_pend" iskew -1
118connect input dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_dram_ack_busy = "${MCU3_PATH}.ucb.ucb_mcu_ack_busy" iskew -1
119connect input dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_dram_int_busy = "${MCU3_PATH}.ucb.ucb_mcu_int_busy" iskew -1
120
121
122. sub connectInstance {
123. my( $core_str ) = @_;
124. my $c = $core_str;
125.
126// read q related
127connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_req" iskew -1
128connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_que_wr_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_que_wr_ptr" iskew -1
129connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_que_rd_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_que_rd_ptr" iskew -1
130connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_cnt" iskew -1
131connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_full" iskew -1
132connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_colps_q_cnt" iskew -1
133connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_full" iskew -1
134connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_empty" iskew -1
135connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_colps_q_empty" iskew -1
136
137connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_req" iskew -1
138connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_que_wr_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_que_wr_ptr" iskew -1
139connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_que_rd_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_que_rd_ptr" iskew -1
140connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_cnt" iskew -1
141connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_full" iskew -1
142connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_colps_q_cnt" iskew -1
143connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_full" iskew -1
144connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_empty" iskew -1
145connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_colps_q_empty" iskew -1
146//connect input dram_coverage_ifc_core_clk.dram_rd_req_q_full_Ch${c}_rd_taken_state = "${DRAM_MON_PATH}.dram_rd_req_q_full_Ch${c}_rd_taken_state" iskew -1
147
148// write q related
149connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_req" iskew -1
150connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_wr_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_que_wr_ptr" iskew -1
151connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_rd_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_que_rd_ptr" iskew -1
152// N2 doesn't support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_rd_ptr_arb = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_que_rd_ptr_arb" iskew -1
153connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_cnt" iskew -1
154connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_full" iskew -1
155// N2 doesn't support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_colps_q_cnt" iskew -1
156// N2 doesn't support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_full" iskew -1
157connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_empty" iskew -1
158connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_colps_q_empty" iskew -1
159connect input dram_coverage_ifc_core_clk.dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state = "${DRAM_MON_PATH}.dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state" iskew -1
160
161connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_req" iskew -1
162connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_wr_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_que_wr_ptr" iskew -1
163connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_rd_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_que_rd_ptr" iskew -1
164// N2 not supporting connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_rd_ptr_arb = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_que_rd_ptr_arb" iskew -1
165connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_cnt" iskew -1
166connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_full" iskew -1
167// N2 not support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_colps_q_cnt" iskew -1
168// N2 doesn't support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_full" iskew -1
169connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_empty" iskew -1
170connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_colps_q_empty" iskew -1
171connect input dram_coverage_ifc_core_clk.dram_l2b1_wr_req_q_full_Ch${c}_wr_taken_state = "${DRAM_MON_PATH}.dram_l2b1_wr_req_q_full_Ch${c}_wr_taken_state" iskew -1
172
173connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_refresh_all_clr_mon_state = "${DRAM_MON_PATH}.dram_Ch${c}_refresh_all_clr_mon_state" iskew -1
174connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_cas_valid = "${DRAM_MON_PATH}.dram_Ch${c}_que_cas_valid" iskew -1
175
176connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_pick_wr_first = "${DRAM_MON_PATH}.dram_Ch${c}_que_pick_wr_first" iskew -1
177connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_req_2a_addr_vld" iskew -1
178connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_req_2a_addr_vld" iskew -1
179connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_scrb_req_2a_addr_vld" iskew -1
180
181connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_req_2a_addr_vld" iskew -1
182connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_req_2a_addr_vld" iskew -1
183
184connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_rd_wr_hit = "${DRAM_MON_PATH}.dram_Ch${c}_que_rd_wr_hit" iskew -1
185
186// not used N2 connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_pend_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_ras_pend_cnt" iskew -1
187connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_ras_picked = "${DRAM_MON_PATH}.dram_Ch${c}_que_ras_picked" iskew -1
188connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_picked = "${DRAM_MON_PATH}.dram_Ch${c}_ras_picked" iskew -1
189// not used N2 connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_cas_pend_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_cas_pend_cnt" iskew -1
190// not used N2 connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_cas_picked = "${DRAM_MON_PATH}.dram_Ch${c}_que_cas_picked" iskew -1
191connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2req_valid = "${DRAM_MON_PATH}.dram_Ch${c}_que_l2req_valid" iskew -1
192connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_indx_val = "${DRAM_MON_PATH}.dram_Ch${c}_scrb_indx_val" iskew -1
193
194connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_chip_config_reg = "${DRAM_MON_PATH}.dram_Ch${c}_chip_config_reg" iskew -1
195connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_mode_reg = "${DRAM_MON_PATH}.dram_Ch${c}_mode_reg" iskew -1
196connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rrd_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rrd_reg" iskew -1
197connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rc_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rc_reg" iskew -1
198connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rcd_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rcd_reg" iskew -1
199connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_wtr_dly_reg = "${DRAM_MON_PATH}.dram_Ch${c}_wtr_dly_reg" iskew -1
200connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rtw_dly_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rtw_dly_reg" iskew -1
201connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rtp_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rtp_reg" iskew -1
202connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_reg = "${DRAM_MON_PATH}.dram_Ch${c}_ras_reg" iskew -1
203connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rp_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rp_reg" iskew -1
204connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_wr_reg = "${DRAM_MON_PATH}.dram_Ch${c}_wr_reg" iskew -1
205connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_mrd_reg = "${DRAM_MON_PATH}.dram_Ch${c}_mrd_reg" iskew -1
206connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_iwtr_reg = "${DRAM_MON_PATH}.dram_Ch${c}_iwtr_reg" iskew -1
207connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg2 = "${DRAM_MON_PATH}.dram_Ch${c}_ext_mode_reg2" iskew -1
208connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg1 = "${DRAM_MON_PATH}.dram_Ch${c}_ext_mode_reg1" iskew -1
209connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg3 = "${DRAM_MON_PATH}.dram_Ch${c}_ext_mode_reg3" iskew -1
210connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_eight_bank_mode = "${DRAM_MON_PATH}.dram_Ch${c}_que_eight_bank_mode" iskew -1
211connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_rank1_present = "${DRAM_MON_PATH}.dram_Ch${c}_que_rank1_present" iskew -1
212connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_channel_disabled = "${DRAM_MON_PATH}.dram_Ch${c}_que_channel_disabled" iskew -1
213connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_addr_bank_low_sel= "${DRAM_MON_PATH}.dram_Ch${c}_que_addr_bank_low_sel" iskew -1
214connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_init = "${DRAM_MON_PATH}.dram_Ch${c}_que_init" iskew -1
215//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_data_del_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_que_data_del_cnt" iskew -1
216//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_io_pad_clk_inv = "${DRAM_MON_PATH}.dram_Ch${c}_dram_io_pad_clk_inv" iskew -1
217//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_io_ptr_clk_inv = "${DRAM_MON_PATH}.dram_Ch${c}_dram_io_ptr_clk_inv" iskew -1
218connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wr_mode_reg_done = "${DRAM_MON_PATH}.dram_Ch${c}_que_wr_mode_reg_done" iskew -1
219connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_init_status_reg = "${DRAM_MON_PATH}.dram_Ch${c}_que_init_status_reg" iskew -1
220connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_dimms_present = "${DRAM_MON_PATH}.dram_Ch${c}_que_dimms_present" iskew -1
221connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_dbg_trig_en = "${DRAM_MON_PATH}.dram_Ch${c}_que_dbg_trig_en" iskew -1
222connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_sts_reg = "${DRAM_MON_PATH}.dram_Ch${c}_que_err_sts_reg" iskew -1
223connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_addr_reg = "${DRAM_MON_PATH}.dram_Ch${c}_que_err_addr_reg" iskew -1
224connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_err_inj_reg = "${DRAM_MON_PATH}.dram_Ch${c}_err_inj_reg" iskew -1
225connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_sshot_err_reg = "${DRAM_MON_PATH}.dram_Ch${c}_sshot_err_reg" iskew -1
226//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_que_err_cnt" iskew -1
227connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_loc = "${DRAM_MON_PATH}.dram_Ch${c}_que_err_loc" iskew -1
228connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2if_ack_vld = "${DRAM_MON_PATH}.dram_Ch${c}_que_l2if_ack_vld" iskew -1
229connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2if_nack_vld = "${DRAM_MON_PATH}.dram_Ch${c}_que_l2if_nack_vld" iskew -1
230//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_adr_info_hi = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_adr_info_hi" iskew -1
231//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_adr_info_hi = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_adr_info_hi" iskew -1
232//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_adr_info_lo = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_adr_info_lo" iskew -1
233//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_adr_info_lo = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_adr_info_lo" iskew -1
234
235//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_adr_info_hi = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_adr_info_hi" iskew -1
236//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_adr_info_hi = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_adr_info_hi" iskew -1
237//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_adr_info_lo = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_adr_info_lo" iskew -1
238//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_adr_info_lo = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_adr_info_lo" iskew -1
239
240// to be done later
241//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_mem_addr = "${DRAM_MON_PATH}.dram_Ch${c}_que_mem_addr" iskew -1
242connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_perf_cntl = "${DRAM_MON_PATH}.dram_Ch${c}_perf_cntl" iskew -1
243connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_cnt0_sticky_bit = "${DRAM_MON_PATH}.dram_Ch${c}_cnt0_sticky_bit" iskew -1
244connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_cnt1_sticky_bit = "${DRAM_MON_PATH}.dram_Ch${c}_cnt1_sticky_bit" iskew -1
245//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_dp_pioson_l2_data = "${DRAM_MON_PATH}.dram_Ch${c}_dp_pioson_l2_data" iskew -1
246//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_dp_pioson_l2_chunk = "${DRAM_MON_PATH}.dram_Ch${c}_dp_pioson_l2_chunk" iskew -1
247
248//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_addr_cnt0 = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_addr_cnt0" iskew -1
249//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_addr_cnt1 = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_addr_cnt1" iskew -1
250//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr0_load_cas2 = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_data_addr0_load_cas2" iskew -1
251//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr0_load = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_data_addr0_load" iskew -1
252//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr1_load = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_data_addr1_load" iskew -1
253
254
255
256. for ( $i = 0; $i < 8; $i++ ) {
257connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_cntr_${i}" iskew -1
258connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_cntr_${i}" iskew -1
259connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_cntr_${i}" iskew -1
260connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_cntr_${i}" iskew -1
261connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req_ack_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_req_ack_cntr_${i}" iskew -1
262connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req_ack_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_req_ack_cntr_${i}" iskew -1
263.}
264connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req_ack_cntr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_req_ack_cntr" iskew -1
265connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req_ack_cntr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_req_ack_cntr" iskew -1
266
267. for ( $ch = 0; $ch < 4; $ch++ ) {
268. for ( $i = 0; $i < 8; $i++ ) {
269connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_cs${ch}_bank_req_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_cs${ch}_bank_req_cntr_${i}" iskew -1
270.}
271.}
272
273connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_sctag_dram_rd_req" iskew -1
274connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_dummy_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_sctag_dram_rd_dummy_req" iskew -1
275connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_rd_ack = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_rd_ack" iskew -1
276connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_wr_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_sctag_dram_wr_req" iskew -1
277connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_wr_ack = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_wr_ack" iskew -1
278connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_data_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_sctag_dram_data_vld" iskew -1
279
280connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_sctag_dram_rd_req" iskew -1
281connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_dummy_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_sctag_dram_rd_dummy_req" iskew -1
282connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_rd_ack = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_rd_ack" iskew -1
283connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_wr_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_sctag_dram_wr_req" iskew -1
284connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_wr_ack = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_wr_ack" iskew -1
285connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_data_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_sctag_dram_data_vld" iskew -1
286
287//N2 not supporting connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b0_rd_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_b0_rd_val" iskew -1
288//N2 not supporting connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b1_rd_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_b1_rd_val" iskew -1
289connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_b0_wr_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_b0_wr_val" iskew -1
290connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_b1_wr_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_b1_wr_val" iskew -1
291connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_b0_wr_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_b0_wr_val" iskew -1
292connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_b1_wr_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_b1_wr_val" iskew -1
293// N2 not supporting connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_wr_b0_data_addr = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_wr_b0_data_addr" iskew -1
294
295connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_secc_err" iskew -1
296connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_pa_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_pa_err" iskew -1
297connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_mecc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_mecc_err" iskew -1
298connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_scb_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_scb_secc_err" iskew -1
299connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_scb_mecc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_scb_mecc_err" iskew -1
300
301connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_secc_err" iskew -1
302connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_pa_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_pa_err" iskew -1
303connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_mecc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_mecc_err" iskew -1
304connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_scb_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_scb_secc_err" iskew -1
305connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_scb_mecc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_scb_mecc_err" iskew -1
306
307connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_scrb_val_d2 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_scrb_val_d2" iskew -1
308connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_secc_err" iskew -1
309connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_mecc_err_partial = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_mecc_err_partial" iskew -1
310connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_pa_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_pa_err" iskew -1
311
312connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_secc_err" iskew -1
313connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_mecc_err_partial = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_mecc_err_partial" iskew -1
314connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_pa_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_pa_err" iskew -1
315
316connect input dram_coverage_ifc_core_clk.dram_Ch${c}_err_sts_reg = "${DRAM_MON_PATH}.dram_Ch${c}_err_sts_reg" iskew -1
317connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en6 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en6" iskew -1
318connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en5 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en5" iskew -1
319connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en4 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en4" iskew -1
320connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en3 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en3" iskew -1
321connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en2 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en2" iskew -1
322connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en1 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en1" iskew -1
323connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en0 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en0" iskew -1
324connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en" iskew -1
325connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_addr_reg_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_addr_reg_en" iskew -1
326connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_secc_loc_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_secc_loc_en" iskew -1
327connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_cpu_wr_addr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_cpu_wr_addr" iskew -1
328connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_cpu_wr_addr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_cpu_wr_addr" iskew -1
329connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_cpu_wr_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_cpu_wr_en" iskew -1
330connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_cpu_wr_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_cpu_wr_en" iskew -1
331connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_wdq_radr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wdq_radr" iskew -1
332connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_wdq_radr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wdq_radr" iskew -1
333connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_wdq_rd_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wdq_rd_en" iskew -1
334connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_wdq_rd_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wdq_rd_en" iskew -1
335//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_data_ret_fifo_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_data_ret_fifo_en" iskew -1
336
337connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_clspine_dram_txrd_sync = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_clspine_dram_txrd_sync" iskew -1
338connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_clspine_dram_txwr_sync = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_clspine_dram_txwr_sync" iskew -1
339connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_clspine_dram_txrd_sync = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_clspine_dram_txrd_sync" iskew -1
340connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_clspine_dram_txwr_sync = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_clspine_dram_txwr_sync" iskew -1
341
342
343
344.
345. } ## connectInstance
346. for ( $dr = 0; $dr < $drc; $dr++ ) {
347// ***********************************************************
348// CONNECTIONS FOR channel_$dr
349// ***********************************************************
350. &connectInstance( $dr );
351. }
352
353
Full OpenSPARC design & verification tarball including full HDL.