// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mcusat_cov.vconpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
#inc "mcusat_cov_inc.pal";
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//connect input dram_coverage_ifc_dram_clk.dram_gclk = "`TOP_MOD.mcusat_mcu_gclk" iskew -1
//connect input dram_coverage_ifc_core_clk.cmp_clk = "`TOP_MOD.mcusat_cmp_gclk" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_gclk = "`TOP_MOD.cpu.mcu0.drl2clk" iskew -1
connect input dram_coverage_ifc_core_clk.cmp_clk = "`TOP_MOD.cpu.mcu0.l2clk" iskew -1
connect input dram_coverage_ifc_jbus_clk.jbus_gclk = "`TOP_MOD.cpu.mcu0.iol2clk" iskew -1
// connect input dram_coverage_ifc_core_clk.cmp_diag_done = "`TOP_MOD.diag_done" iskew -1
//connect input dram_coverage_ifc_core_clk.cmp_grst_l = "`TOP_MOD.rst_reg_l" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_rst_l = "${DRAM_MON_PATH}.dram_rst_l" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_que_pos = "${DRAM_MON_PATH}.dram_Ch0_que_pos" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_que_pos = "${DRAM_MON_PATH}.dram_Ch1_que_pos" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_que_pos = "${DRAM_MON_PATH}.dram_Ch2_que_pos" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_que_pos = "${DRAM_MON_PATH}.dram_Ch3_que_pos" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_pt_selfrsh = "${DRAM_MON_PATH}.dram_Ch0_que_hw_selfrsh" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_pt_selfrsh = "${DRAM_MON_PATH}.dram_Ch1_que_hw_selfrsh" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_pt_selfrsh = "${DRAM_MON_PATH}.dram_Ch2_que_hw_selfrsh" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_pt_selfrsh = "${DRAM_MON_PATH}.dram_Ch3_que_hw_selfrsh" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif0_raw_hazard = "`MCU0_DRIF_CTL.drif0_raw_hazard" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif1_raw_hazard = "`MCU0_DRIF_CTL.drif1_raw_hazard" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif0_raw_hazard = "`MCU1_DRIF_CTL.drif0_raw_hazard" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif1_raw_hazard = "`MCU1_DRIF_CTL.drif1_raw_hazard" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif0_raw_hazard = "`MCU2_DRIF_CTL.drif0_raw_hazard" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif1_raw_hazard = "`MCU2_DRIF_CTL.drif1_raw_hazard" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif0_raw_hazard = "`MCU3_DRIF_CTL.drif0_raw_hazard" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif1_raw_hazard = "`MCU3_DRIF_CTL.drif1_raw_hazard" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif_ref_go = "`MCU0_DRIF_CTL.drif_ref_go" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif_refresh_rank = "`MCU0_DRIF_CTL.drif_refresh_rank" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif_ref_go = "`MCU1_DRIF_CTL.drif_ref_go" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif_refresh_rank = "`MCU1_DRIF_CTL.drif_refresh_rank" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif_ref_go = "`MCU2_DRIF_CTL.drif_ref_go" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif_refresh_rank = "`MCU2_DRIF_CTL.drif_refresh_rank" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif_ref_go = "`MCU3_DRIF_CTL.drif_ref_go" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif_refresh_rank = "`MCU3_DRIF_CTL.drif_refresh_rank" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_drif_single_channel_mode = "`MCU0_DRIF_CTL.drif_single_channel_mode" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_fbd1_data = "`MCU0.fbd1_data" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_drif_single_channel_mode = "`MCU1_DRIF_CTL.drif_single_channel_mode" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_fbd1_data = "`MCU1.fbd1_data" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_drif_single_channel_mode = "`MCU2_DRIF_CTL.drif_single_channel_mode" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_fbd1_data = "`MCU2.fbd1_data" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_drif_single_channel_mode = "`MCU3_DRIF_CTL.drif_single_channel_mode" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_fbd1_data = "`MCU3.fbd1_data" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_fast_reset = "`MCU0.fbdic.fbdic_fast_reset" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_fbd_state = "`MCU0.fbdic.fbdic_fbd_state[2:0]" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_fbdic_fast_reset = "`MCU1.fbdic.fbdic_fast_reset" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_fbdic_fbd_state = "`MCU1.fbdic.fbdic_fbd_state[2:0]" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_fbdic_fast_reset = "`MCU2.fbdic.fbdic_fast_reset" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_fbdic_fbd_state = "`MCU2.fbdic.fbdic_fbd_state[2:0]" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_fbdic_fast_reset = "`MCU3.fbdic.fbdic_fast_reset" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_fbdic_fbd_state = "`MCU3.fbdic.fbdic_fbd_state[2:0]" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch0_pt_blk_new_openbank_d1= "${DRAM_MON_PATH}.dram_Ch0_pt_blk_new_openbank_d1" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch1_pt_blk_new_openbank_d1= "${DRAM_MON_PATH}.dram_Ch1_pt_blk_new_openbank_d1" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch2_pt_blk_new_openbank_d1= "${DRAM_MON_PATH}.dram_Ch2_pt_blk_new_openbank_d1" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch3_pt_blk_new_openbank_d1= "${DRAM_MON_PATH}.dram_Ch3_pt_blk_new_openbank_d1" iskew -1
//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch0_l2if_ucb_trig = "${MCU0_PATH}.ucb.ddr_clk_tr" iskew -1
//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch1_l2if_ucb_trig = "${MCU1_PATH}.ucb.ddr_clk_tr" iskew -1
//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch2_l2if_ucb_trig = "${MCU2_PATH}.ucb.ddr_clk_tr" iskew -1
//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch3_l2if_ucb_trig = "${MCU3_PATH}.ucb.ddr_clk_tr" iskew -1
/////////////// not done above
connect input dram_coverage_ifc_jbus_clk.dram_Ch0_rd_req_vld = "${MCU0_PATH}.ucb.ucb_mcu_rd_req_vld0" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_req_pend = "${MCU0_PATH}.ucb.ucb_req_pend" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_dram_ack_busy = "${MCU0_PATH}.ucb.ucb_mcu_ack_busy" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_dram_int_busy = "${MCU0_PATH}.ucb.ucb_mcu_int_busy" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch1_rd_req_vld = "${MCU1_PATH}.ucb.ucb_mcu_rd_req_vld0" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_req_pend = "${MCU1_PATH}.ucb.ucb_req_pend" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_dram_ack_busy = "${MCU1_PATH}.ucb.ucb_mcu_ack_busy" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_dram_int_busy = "${MCU1_PATH}.ucb.ucb_mcu_int_busy" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch2_rd_req_vld = "${MCU2_PATH}.ucb.ucb_mcu_rd_req_vld0" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_req_pend = "${MCU2_PATH}.ucb.ucb_req_pend" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_dram_ack_busy = "${MCU2_PATH}.ucb.ucb_mcu_ack_busy" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_dram_int_busy = "${MCU2_PATH}.ucb.ucb_mcu_int_busy" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch3_rd_req_vld = "${MCU3_PATH}.ucb.ucb_mcu_rd_req_vld0" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_req_pend = "${MCU3_PATH}.ucb.ucb_req_pend" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_dram_ack_busy = "${MCU3_PATH}.ucb.ucb_mcu_ack_busy" iskew -1
connect input dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_dram_int_busy = "${MCU3_PATH}.ucb.ucb_mcu_int_busy" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_req" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_que_wr_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_que_wr_ptr" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_que_rd_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_que_rd_ptr" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_cnt" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_full" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_colps_q_cnt" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_full" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_empty" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_colps_q_empty" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_req" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_que_wr_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_que_wr_ptr" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_que_rd_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_que_rd_ptr" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_cnt" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_full" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_colps_q_cnt" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_full" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_empty" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_colps_q_empty" iskew -1
//connect input dram_coverage_ifc_core_clk.dram_rd_req_q_full_Ch${c}_rd_taken_state = "${DRAM_MON_PATH}.dram_rd_req_q_full_Ch${c}_rd_taken_state" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_req" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_wr_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_que_wr_ptr" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_rd_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_que_rd_ptr" iskew -1
// N2 doesn't support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_rd_ptr_arb = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_que_rd_ptr_arb" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_cnt" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_full" iskew -1
// N2 doesn't support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_colps_q_cnt" iskew -1
// N2 doesn't support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_full" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_empty" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_colps_q_empty" iskew -1
connect input dram_coverage_ifc_core_clk.dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state = "${DRAM_MON_PATH}.dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_req" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_wr_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_que_wr_ptr" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_rd_ptr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_que_rd_ptr" iskew -1
// N2 not supporting connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_rd_ptr_arb = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_que_rd_ptr_arb" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_cnt" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_full" iskew -1
// N2 not support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_colps_q_cnt" iskew -1
// N2 doesn't support connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_full = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_full" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_empty" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_empty = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_colps_q_empty" iskew -1
connect input dram_coverage_ifc_core_clk.dram_l2b1_wr_req_q_full_Ch${c}_wr_taken_state = "${DRAM_MON_PATH}.dram_l2b1_wr_req_q_full_Ch${c}_wr_taken_state" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_refresh_all_clr_mon_state = "${DRAM_MON_PATH}.dram_Ch${c}_refresh_all_clr_mon_state" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_cas_valid = "${DRAM_MON_PATH}.dram_Ch${c}_que_cas_valid" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_pick_wr_first = "${DRAM_MON_PATH}.dram_Ch${c}_que_pick_wr_first" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_req_2a_addr_vld" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_req_2a_addr_vld" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_scrb_req_2a_addr_vld" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_req_2a_addr_vld" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req_2a_addr_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_req_2a_addr_vld" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_rd_wr_hit = "${DRAM_MON_PATH}.dram_Ch${c}_que_rd_wr_hit" iskew -1
// not used N2 connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_pend_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_ras_pend_cnt" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_ras_picked = "${DRAM_MON_PATH}.dram_Ch${c}_que_ras_picked" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_picked = "${DRAM_MON_PATH}.dram_Ch${c}_ras_picked" iskew -1
// not used N2 connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_cas_pend_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_cas_pend_cnt" iskew -1
// not used N2 connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_cas_picked = "${DRAM_MON_PATH}.dram_Ch${c}_que_cas_picked" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2req_valid = "${DRAM_MON_PATH}.dram_Ch${c}_que_l2req_valid" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_indx_val = "${DRAM_MON_PATH}.dram_Ch${c}_scrb_indx_val" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_chip_config_reg = "${DRAM_MON_PATH}.dram_Ch${c}_chip_config_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_mode_reg = "${DRAM_MON_PATH}.dram_Ch${c}_mode_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rrd_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rrd_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rc_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rc_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rcd_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rcd_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_wtr_dly_reg = "${DRAM_MON_PATH}.dram_Ch${c}_wtr_dly_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rtw_dly_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rtw_dly_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rtp_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rtp_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_reg = "${DRAM_MON_PATH}.dram_Ch${c}_ras_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_rp_reg = "${DRAM_MON_PATH}.dram_Ch${c}_rp_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_wr_reg = "${DRAM_MON_PATH}.dram_Ch${c}_wr_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_mrd_reg = "${DRAM_MON_PATH}.dram_Ch${c}_mrd_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_iwtr_reg = "${DRAM_MON_PATH}.dram_Ch${c}_iwtr_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg2 = "${DRAM_MON_PATH}.dram_Ch${c}_ext_mode_reg2" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg1 = "${DRAM_MON_PATH}.dram_Ch${c}_ext_mode_reg1" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg3 = "${DRAM_MON_PATH}.dram_Ch${c}_ext_mode_reg3" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_eight_bank_mode = "${DRAM_MON_PATH}.dram_Ch${c}_que_eight_bank_mode" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_rank1_present = "${DRAM_MON_PATH}.dram_Ch${c}_que_rank1_present" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_channel_disabled = "${DRAM_MON_PATH}.dram_Ch${c}_que_channel_disabled" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_addr_bank_low_sel= "${DRAM_MON_PATH}.dram_Ch${c}_que_addr_bank_low_sel" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_init = "${DRAM_MON_PATH}.dram_Ch${c}_que_init" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_data_del_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_que_data_del_cnt" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_io_pad_clk_inv = "${DRAM_MON_PATH}.dram_Ch${c}_dram_io_pad_clk_inv" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_io_ptr_clk_inv = "${DRAM_MON_PATH}.dram_Ch${c}_dram_io_ptr_clk_inv" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wr_mode_reg_done = "${DRAM_MON_PATH}.dram_Ch${c}_que_wr_mode_reg_done" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_init_status_reg = "${DRAM_MON_PATH}.dram_Ch${c}_que_init_status_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_dimms_present = "${DRAM_MON_PATH}.dram_Ch${c}_que_dimms_present" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_dbg_trig_en = "${DRAM_MON_PATH}.dram_Ch${c}_que_dbg_trig_en" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_sts_reg = "${DRAM_MON_PATH}.dram_Ch${c}_que_err_sts_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_addr_reg = "${DRAM_MON_PATH}.dram_Ch${c}_que_err_addr_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_err_inj_reg = "${DRAM_MON_PATH}.dram_Ch${c}_err_inj_reg" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_sshot_err_reg = "${DRAM_MON_PATH}.dram_Ch${c}_sshot_err_reg" iskew -1
//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_cnt = "${DRAM_MON_PATH}.dram_Ch${c}_que_err_cnt" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_loc = "${DRAM_MON_PATH}.dram_Ch${c}_que_err_loc" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2if_ack_vld = "${DRAM_MON_PATH}.dram_Ch${c}_que_l2if_ack_vld" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2if_nack_vld = "${DRAM_MON_PATH}.dram_Ch${c}_que_l2if_nack_vld" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_adr_info_hi = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_adr_info_hi" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_adr_info_hi = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_adr_info_hi" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_adr_info_lo = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_adr_info_lo" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_adr_info_lo = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_adr_info_lo" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_adr_info_hi = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_adr_info_hi" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_adr_info_hi = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_adr_info_hi" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_adr_info_lo = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_adr_info_lo" iskew -1
//somePersonconnect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_adr_info_lo = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_adr_info_lo" iskew -1
//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_mem_addr = "${DRAM_MON_PATH}.dram_Ch${c}_que_mem_addr" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_perf_cntl = "${DRAM_MON_PATH}.dram_Ch${c}_perf_cntl" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_cnt0_sticky_bit = "${DRAM_MON_PATH}.dram_Ch${c}_cnt0_sticky_bit" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_cnt1_sticky_bit = "${DRAM_MON_PATH}.dram_Ch${c}_cnt1_sticky_bit" iskew -1
//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_dp_pioson_l2_data = "${DRAM_MON_PATH}.dram_Ch${c}_dp_pioson_l2_data" iskew -1
//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_dp_pioson_l2_chunk = "${DRAM_MON_PATH}.dram_Ch${c}_dp_pioson_l2_chunk" iskew -1
//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_addr_cnt0 = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_addr_cnt0" iskew -1
//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_addr_cnt1 = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_addr_cnt1" iskew -1
//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr0_load_cas2 = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_data_addr0_load_cas2" iskew -1
//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr0_load = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_data_addr0_load" iskew -1
//connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr1_load = "${DRAM_MON_PATH}.dram_Ch${c}_que_wl_data_addr1_load" iskew -1
. for ( $i = 0; $i < 8; $i++ ) {
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_q_cntr_${i}" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_q_cntr_${i}" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_q_cntr_${i}" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_q_cntr_${i}" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req_ack_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_rd_req_ack_cntr_${i}" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req_ack_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_rd_req_ack_cntr_${i}" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req_ack_cntr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wr_req_ack_cntr" iskew -1
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req_ack_cntr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wr_req_ack_cntr" iskew -1
. for ( $ch = 0; $ch < 4; $ch++ ) {
. for ( $i = 0; $i < 8; $i++ ) {
connect input dram_coverage_ifc_dram_clk.dram_Ch${c}_cs${ch}_bank_req_cntr_${i} = "${DRAM_MON_PATH}.dram_Ch${c}_cs${ch}_bank_req_cntr_${i}" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_sctag_dram_rd_req" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_dummy_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_sctag_dram_rd_dummy_req" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_rd_ack = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_rd_ack" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_wr_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_sctag_dram_wr_req" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_wr_ack = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_wr_ack" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_data_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_sctag_dram_data_vld" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_sctag_dram_rd_req" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_dummy_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_sctag_dram_rd_dummy_req" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_rd_ack = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_rd_ack" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_wr_req = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_sctag_dram_wr_req" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_wr_ack = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_wr_ack" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_data_vld = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_sctag_dram_data_vld" iskew -1
//N2 not supporting connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b0_rd_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_b0_rd_val" iskew -1
//N2 not supporting connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b1_rd_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_b1_rd_val" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_b0_wr_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_b0_wr_val" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_b1_wr_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_b1_wr_val" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_b0_wr_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_b0_wr_val" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_b1_wr_val = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_b1_wr_val" iskew -1
// N2 not supporting connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_wr_b0_data_addr = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_wr_b0_data_addr" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_secc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_pa_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_pa_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_mecc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_mecc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_scb_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_scb_secc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_scb_mecc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_dram_sctag_scb_mecc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_secc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_pa_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_pa_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_mecc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_mecc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_scb_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_scb_secc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_scb_mecc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_dram_sctag_scb_mecc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_scrb_val_d2 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_scrb_val_d2" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_secc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_mecc_err_partial = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_mecc_err_partial" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_pa_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_l2if_pa_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_secc_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_secc_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_mecc_err_partial = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_mecc_err_partial" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_pa_err = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_l2if_pa_err" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_err_sts_reg = "${DRAM_MON_PATH}.dram_Ch${c}_err_sts_reg" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en6 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en6" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en5 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en5" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en4 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en4" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en3 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en3" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en2 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en2" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en1 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en1" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en0 = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en0" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_sts_reg_en" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_addr_reg_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_err_addr_reg_en" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_secc_loc_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_secc_loc_en" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_cpu_wr_addr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_cpu_wr_addr" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_cpu_wr_addr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_cpu_wr_addr" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_cpu_wr_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_cpu_wr_en" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_cpu_wr_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_cpu_wr_en" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_wdq_radr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wdq_radr" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_wdq_radr = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wdq_radr" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_wdq_rd_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_wdq_rd_en" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_wdq_rd_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_wdq_rd_en" iskew -1
//somePersonconnect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_data_ret_fifo_en = "${DRAM_MON_PATH}.dram_Ch${c}_l2if_data_ret_fifo_en" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_clspine_dram_txrd_sync = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_clspine_dram_txrd_sync" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_clspine_dram_txwr_sync = "${DRAM_MON_PATH}.dram_Ch${c}_l2b0_clspine_dram_txwr_sync" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_clspine_dram_txrd_sync = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_clspine_dram_txrd_sync" iskew -1
connect input dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_clspine_dram_txwr_sync = "${DRAM_MON_PATH}.dram_Ch${c}_l2b1_clspine_dram_txwr_sync" iskew -1
. for ( $dr = 0; $dr < $drc; $dr++ ) {
// ***********************************************************
// CONNECTIONS FOR channel_$dr
// ***********************************************************
. &connectInstance( $dr );
projects / OpenSPARC-T2-DV / blob