projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: mcusat_cov_ports_binds.vrhpal | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #inc "mcusat_cov_inc.pal"; | |
| 36 | #ifndef __DRAM_PORTS_VRH__ | |
| 37 | #define __DRAM_PORTS_VRH__ | |
| 38 | ||
| 39 | #include <vera_defines.vrh> | |
| 40 | ||
| 41 | //--------------------------------------------------------------- | |
| 42 | // The clock port | |
| 43 | //--------------------------------------------------------------- | |
| 44 | ||
| 45 | //port dram_clk_port { | |
| 46 | // dram_gclk; | |
| 47 | //} | |
| 48 | ||
| 49 | //port core_clk_port { | |
| 50 | // cmp_clk; | |
| 51 | // cmp_diag_done; | |
| 52 | // cmp_grst_l; | |
| 53 | //} | |
| 54 | ||
| 55 | //--------------------------------------------------------------- | |
| 56 | // dram_que.v , controller state machine | |
| 57 | //--------------------------------------------------------------- | |
| 58 | port dram_que_fsm { | |
| 59 | que_pos; | |
| 60 | } | |
| 61 | ||
| 62 | //--------------------------------------------------------------- | |
| 63 | // rd que status signals | |
| 64 | //--------------------------------------------------------------- | |
| 65 | port dram_rd_que_status_port { | |
| 66 | rd_que_status; | |
| 67 | // | |
| 68 | //dram_Ch{c}_rd_req | |
| 69 | //[7:0] dram_Ch{c}_rd_que_wr_ptr | |
| 70 | //[7:0] dram_Ch{c}_rd_que_rd_ptr | |
| 71 | //[3:0] dram_Ch{c}_rd_q_cnt | |
| 72 | //dram_Ch{c}_rd_q_full | |
| 73 | //[3:0] dram_Ch{c}_rd_colps_q_cnt | |
| 74 | //dram_Ch{c}_rd_colps_q_full | |
| 75 | //dram_Ch{c}_rd_q_empty | |
| 76 | //dram_Ch{c}_rd_colps_q_empty | |
| 77 | ||
| 78 | } | |
| 79 | ||
| 80 | port dram_rd_q_full_n_req_port { | |
| 81 | fsm_state; | |
| 82 | } | |
| 83 | ||
| 84 | //--------------------------------------------------------------- | |
| 85 | // wr que status signals | |
| 86 | //--------------------------------------------------------------- | |
| 87 | port dram_wr_que_status_port { | |
| 88 | wr_que_status; | |
| 89 | } | |
| 90 | ||
| 91 | port dram_wr_q_full_n_req_port { | |
| 92 | fsm_state; | |
| 93 | } | |
| 94 | ||
| 95 | port dram_que_wr_picked_port { | |
| 96 | wr_pick; | |
| 97 | } | |
| 98 | ||
| 99 | port dram_rd_wr_hit_port { | |
| 100 | rd_wr_hit; | |
| 101 | } | |
| 102 | ||
| 103 | // write memory read from the dram side | |
| 104 | port dram_wr_data_rd_mem_sample { | |
| 105 | en_n_addr; | |
| 106 | } | |
| 107 | ||
| 108 | //--------------------------------------------------------------- | |
| 109 | // Scrub and request to the same bank, scrb should be picked first. | |
| 110 | // No request to same bank in between a scrub | |
| 111 | //--------------------------------------------------------------- | |
| 112 | port dram_scb_req_same_bank_port { | |
| 113 | scb_req; | |
| 114 | } | |
| 115 | //--------------------------------------------------------------- | |
| 116 | // Power throttle blk bank open cross with hw refresh issued | |
| 117 | //--------------------------------------------------------------- | |
| 118 | port dram_pt_refresh_blk_bank { | |
| 119 | pt_refresh_blk_bank; | |
| 120 | } | |
| 121 | ||
| 122 | //--------------------------------------------------------------- | |
| 123 | // refresh monitor signal | |
| 124 | //--------------------------------------------------------------- | |
| 125 | port dram_refresh_all_clr_mon_state_port { | |
| 126 | fsm_state; | |
| 127 | } | |
| 128 | ||
| 129 | //--------------------------------------------------------------- | |
| 130 | // CAS Queue | |
| 131 | //--------------------------------------------------------------- | |
| 132 | port dram_cas_que_port { | |
| 133 | cas_valid; | |
| 134 | } | |
| 135 | ||
| 136 | //--------------------------------------------------------------- | |
| 137 | // CAS Queue | |
| 138 | //--------------------------------------------------------------- | |
| 139 | port dram_rd_wr_scrb_schmoo_port { | |
| 140 | rd_wr_scrb_vld; | |
| 141 | } | |
| 142 | ||
| 143 | //--------------------------------------------------------------- | |
| 144 | // RAS/CAS pending cnt, ras_picked, cas_picked | |
| 145 | //--------------------------------------------------------------- | |
| 146 | port dram_ras_cas_pend_cnt_port { | |
| 147 | ras_cas_pend_cnt; | |
| 148 | } | |
| 149 | port dram_ras_picked_port { | |
| 150 | ras_picked; | |
| 151 | } | |
| 152 | port dram_cas_picked_port { | |
| 153 | cas_picked; | |
| 154 | } | |
| 155 | ||
| 156 | //--------------------------------------------------------------- | |
| 157 | // DRAM registers | |
| 158 | //--------------------------------------------------------------- | |
| 159 | port dram_reg_port { | |
| 160 | registers; | |
| 161 | } | |
| 162 | port dram_reg_ack_nack_port { | |
| 163 | ack_nack; | |
| 164 | } | |
| 165 | ||
| 166 | //--------------------------------------------------------------- | |
| 167 | // DRAM perf cntr ( control and sticky bit ) | |
| 168 | //--------------------------------------------------------------- | |
| 169 | port dram_perf_cntr_port { | |
| 170 | perf; | |
| 171 | } | |
| 172 | ||
| 173 | //--------------------------------------------------------------- | |
| 174 | // DRAM parameters : (pa_err,s,r,bank,2ch,8bk) * 4 ( = rd/wr*lo/hi) | |
| 175 | //--------------------------------------------------------------- | |
| 176 | port dram_rank_stack_addr_param_rd_hi_port { | |
| 177 | addr_etc_info_rd_hi; | |
| 178 | } | |
| 179 | port dram_rank_stack_addr_param_wr_hi_port { | |
| 180 | addr_etc_info_wr_hi; | |
| 181 | } | |
| 182 | port dram_rank_stack_addr_param_rd_lo_port { | |
| 183 | addr_etc_info_rd_lo; | |
| 184 | } | |
| 185 | port dram_rank_stack_addr_param_wr_lo_port { | |
| 186 | addr_etc_info_wr_lo; | |
| 187 | } | |
| 188 | ||
| 189 | //--------------------------------------------------------------- | |
| 190 | // DRAM DP | |
| 191 | //--------------------------------------------------------------- | |
| 192 | port dram_dp_pioson_l2_data_port { | |
| 193 | dp_pioson_l2_data; | |
| 194 | } | |
| 195 | ||
| 196 | //--------------------------------------------------------------- | |
| 197 | // DRAM for line cov | |
| 198 | //--------------------------------------------------------------- | |
| 199 | //port dram_line_cov_port { | |
| 200 | // line_cov; | |
| 201 | //} | |
| 202 | ||
| 203 | //--------------------------------------------------------------- | |
| 204 | // Q counters to indicate how much time a request spend in RD/WR Q | |
| 205 | //--------------------------------------------------------------- | |
| 206 | port dram_rd_q_cntr_port { | |
| 207 | cntr; | |
| 208 | } | |
| 209 | port dram_wr_q_cntr_port { | |
| 210 | cntr; | |
| 211 | } | |
| 212 | ||
| 213 | //--------------------------------------------------------------- | |
| 214 | // Q counters to indicate how much time between | |
| 215 | // 1) rd req and rd data return | |
| 216 | // 2) wr req and wr ack | |
| 217 | //--------------------------------------------------------------- | |
| 218 | port dram_rd_req_ack_cntr_port { | |
| 219 | cntr; | |
| 220 | } | |
| 221 | port dram_wr_req_ack_cntr_port { | |
| 222 | cntr; | |
| 223 | } | |
| 224 | ||
| 225 | ||
| 226 | port dram_cs_bank_req_cntr_port { | |
| 227 | cntr; | |
| 228 | } | |
| 229 | ||
| 230 | ||
| 231 | //--------------------------------------------------------------- | |
| 232 | // DRAM-l2if rd wr handshake signals | |
| 233 | //--------------------------------------------------------------- | |
| 234 | port dram_rd_wr_l2if_port { | |
| 235 | rd_wr_l2if; | |
| 236 | //dram_Ch{c}_sctag_dram_rd_req, | |
| 237 | //dram_Ch{c}_sctag_dram_rd_dummy_req, | |
| 238 | //dram_Ch{c}_dram_sctag_rd_ack, | |
| 239 | //dram_Ch{c}_sctag_dram_wr_req, | |
| 240 | //dram_Ch{c}_dram_sctag_wr_ack, | |
| 241 | //dram_Ch{c}_sctag_dram_data_vld, | |
| 242 | //[3:0] dram_Ch{c}_l2if_b0_rd_val, | |
| 243 | //[3:0] dram_Ch{c}_l2if_b1_rd_val, | |
| 244 | //[3:0] dram_Ch{c}_l2if_b0_wr_val, | |
| 245 | //[3:0] dram_Ch{c}_l2if_b1_wr_val, | |
| 246 | //[5:0] dram_Ch{c}_l2if_wr_b0_data_addr, | |
| 247 | } | |
| 248 | ||
| 249 | // write memory wr from the l2 side | |
| 250 | port dram_wr_data_mem_sample { | |
| 251 | en_n_addr; | |
| 252 | } | |
| 253 | ||
| 254 | port dram_err_l2if_port { | |
| 255 | secc_pa_mecc_scb_secc_mecc; | |
| 256 | } | |
| 257 | ||
| 258 | port dram_l2if_data_ret_fifo_port { | |
| 259 | fifo_en; | |
| 260 | } | |
| 261 | ||
| 262 | // Error status and enables | |
| 263 | port dram_err_sts_port { | |
| 264 | err_en_n_sts; | |
| 265 | } | |
| 266 | ||
| 267 | ||
| 268 | ||
| 269 | //--------------------------------------------------------------- | |
| 270 | // DRAM-l2if freq schmoo between rd/wr req and sync pulse | |
| 271 | //--------------------------------------------------------------- | |
| 272 | port dram_rd_sync_port { | |
| 273 | rd_sync; | |
| 274 | } | |
| 275 | ||
| 276 | port dram_wr_sync_port { | |
| 277 | wr_sync; | |
| 278 | } | |
| 279 | ||
| 280 | port dram_mcu_ncu_intf_port { | |
| 281 | intr; | |
| 282 | } | |
| 283 | port dram_err_intr_ucb_trig_port1 { | |
| 284 | err_intr_ucb_trig1; | |
| 285 | } | |
| 286 | ||
| 287 | port dram_ucb_etc_port { | |
| 288 | ucb_etc; | |
| 289 | } | |
| 290 | port dram_raw_hazard_port { | |
| 291 | hazard; | |
| 292 | } | |
| 293 | port dram_refresh_port { | |
| 294 | refresh; | |
| 295 | } | |
| 296 | port dram_single_channel_port { | |
| 297 | single_ch; | |
| 298 | } | |
| 299 | port dram_fbd_fast_reset_port { | |
| 300 | fast_reset; | |
| 301 | } | |
| 302 | port dram_fbd_cmd_a_port { | |
| 303 | cmd; | |
| 304 | } | |
| 305 | port dram_fbd_cmd_b_port { | |
| 306 | cmd; | |
| 307 | } | |
| 308 | port dram_fbd_cmd_c_port { | |
| 309 | cmd; | |
| 310 | } | |
| 311 | port dram_fbd_dimm_cmd_a_port { | |
| 312 | frame; | |
| 313 | } | |
| 314 | port dram_fbd_dimm_cmd_b_port { | |
| 315 | frame; | |
| 316 | } | |
| 317 | port dram_fbd_dimm_cmd_c_port { | |
| 318 | frame; | |
| 319 | } | |
| 320 | port dram_fbd_l0s_state_port { | |
| 321 | l0sstate; | |
| 322 | } | |
| 323 | port dram_fbd_nb_ts0_port { | |
| 324 | frame; | |
| 325 | } | |
| 326 | port dram_fbd_nb_stspar_port { | |
| 327 | frame; | |
| 328 | } | |
| 329 | port dram_fbd_nb_idle_port { | |
| 330 | frame; | |
| 331 | } | |
| 332 | port dram_fbd_nb_alrt_port { | |
| 333 | frame; | |
| 334 | } | |
| 335 | port dram_fbd_nb_alrt_assrt_port { | |
| 336 | frame; | |
| 337 | } | |
| 338 | port dram_fbd_nb_nbde_port { | |
| 339 | frame; | |
| 340 | } | |
| 341 | port dram_dbg_rd_req_port { | |
| 342 | dbgrd; | |
| 343 | } | |
| 344 | port dram_dbg_wr_req_port { | |
| 345 | dbgwr; | |
| 346 | } | |
| 347 | port dram_dbg_err_port { | |
| 348 | dbgerr; | |
| 349 | } | |
| 350 | port dram_fbd_sb_port { | |
| 351 | frame; | |
| 352 | } | |
| 353 | port dram_failover_port { | |
| 354 | failover; | |
| 355 | } | |
| 356 | port dram_fbd0_sb_failover_port { | |
| 357 | failover; | |
| 358 | } | |
| 359 | port dram_fbd1_sb_failover_port { | |
| 360 | failover; | |
| 361 | } | |
| 362 | port dram_fbd0_nb_failover_port { | |
| 363 | failover; | |
| 364 | } | |
| 365 | port dram_fbd1_nb_failover_port { | |
| 366 | failover; | |
| 367 | } | |
| 368 | port dram_mem_poison_port { | |
| 369 | ecc; | |
| 370 | } | |
| 371 | port dram_wr_mem_poison_port { | |
| 372 | poison; | |
| 373 | } | |
| 374 | ||
| 375 | ||
| 376 | ||
| 377 | ||
| 378 | //--------------------------------------------------------------- | |
| 379 | ||
| 380 | ||
| 381 | ||
| 382 | . sub coreBindings { | |
| 383 | . my($core_num) = @_; | |
| 384 | . my $c = $core_num; | |
| 385 | ||
| 386 | //bind dram_clk_port dram_Ch${c}_dram_clk_bind { | |
| 387 | // dram_gclk dram_coverage_ifc_dram_clk.dram_gclk; | |
| 388 | //} | |
| 389 | ||
| 390 | //bind core_clk_port dram_Ch${c}_core_clk_bind { | |
| 391 | // cmp_clk dram_coverage_ifc_core_clk.cmp_clk; | |
| 392 | // cmp_diag_done dram_coverage_ifc_core_clk.cmp_diag_done; | |
| 393 | // cmp_grst_l dram_coverage_ifc_core_clk.cmp_grst_l; | |
| 394 | //} | |
| 395 | ||
| 396 | bind dram_que_fsm ${prefix}mcu_que_fsm_sample_bind_Ch${c} { | |
| 397 | que_pos dram_coverage_ifc_dram_clk.dram_Ch${c}_que_pos; | |
| 398 | } | |
| 399 | ||
| 400 | bind dram_rd_que_status_port ${prefix}mcu_rd_que_status_sample_bind_Ch${c}_l2b0 { | |
| 401 | rd_que_status { | |
| 402 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req, | |
| 403 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_que_wr_ptr, | |
| 404 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_que_rd_ptr, | |
| 405 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_cnt, | |
| 406 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_full, | |
| 407 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_cnt, | |
| 408 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_full, | |
| 409 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_empty, | |
| 410 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_colps_q_empty | |
| 411 | }; | |
| 412 | } | |
| 413 | ||
| 414 | bind dram_rd_que_status_port ${prefix}mcu_rd_que_status_sample_bind_Ch${c}_l2b1 { | |
| 415 | rd_que_status { | |
| 416 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req, | |
| 417 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_que_wr_ptr, | |
| 418 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_que_rd_ptr, | |
| 419 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_cnt, | |
| 420 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_full, | |
| 421 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_cnt, | |
| 422 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_full, | |
| 423 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_empty, | |
| 424 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_colps_q_empty | |
| 425 | }; | |
| 426 | } | |
| 427 | ||
| 428 | bind dram_rd_q_full_n_req_port ${prefix}mcu_rd_q_full_n_req_sample_bind_Ch${c} { | |
| 429 | fsm_state dram_coverage_ifc_core_clk.dram_rd_req_q_full_Ch${c}_rd_taken_state; | |
| 430 | } | |
| 431 | ||
| 432 | bind dram_scb_req_same_bank_port ${prefix}mcu_scb_req_same_bank_sample_bind_Ch${c} { | |
| 433 | scb_req { | |
| 434 | dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_indx_val, | |
| 435 | dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2req_valid, | |
| 436 | dram_coverage_ifc_dram_clk.dram_Ch${c}_que_pos | |
| 437 | }; | |
| 438 | } | |
| 439 | ||
| 440 | bind dram_wr_que_status_port ${prefix}mcu_wr_que_status_sample_bind_Ch${c}_l2b0 { | |
| 441 | wr_que_status { | |
| 442 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req, | |
| 443 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_wr_ptr, | |
| 444 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_que_rd_ptr, | |
| 445 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_cnt, | |
| 446 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_full, | |
| 447 | //dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_cnt, // not in N2 | |
| 448 | //dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_full, // not in N2 | |
| 449 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_empty, | |
| 450 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_colps_q_empty | |
| 451 | }; | |
| 452 | } | |
| 453 | ||
| 454 | bind dram_wr_que_status_port ${prefix}mcu_wr_que_status_sample_bind_Ch${c}_l2b1 { | |
| 455 | wr_que_status { | |
| 456 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req, | |
| 457 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_wr_ptr, | |
| 458 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_que_rd_ptr, | |
| 459 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_cnt, | |
| 460 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_full, | |
| 461 | //dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_cnt, // not in N2 | |
| 462 | //dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_full, // not in N2 | |
| 463 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_empty, | |
| 464 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_colps_q_empty | |
| 465 | }; | |
| 466 | } | |
| 467 | ||
| 468 | bind dram_wr_q_full_n_req_port ${prefix}l2_mcu_intf_wr_q_full_n_req_sample_bind_Ch${c}_l2b0 { | |
| 469 | fsm_state dram_coverage_ifc_core_clk.dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state; | |
| 470 | } | |
| 471 | bind dram_wr_q_full_n_req_port ${prefix}l2_mcu_intf_wr_q_full_n_req_sample_bind_Ch${c}_l2b1 { | |
| 472 | fsm_state dram_coverage_ifc_core_clk.dram_l2b0_wr_req_q_full_Ch${c}_wr_taken_state; | |
| 473 | } | |
| 474 | ||
| 475 | bind dram_que_wr_picked_port ${prefix}mcu_que_pick_wr_first_sample_bind_Ch${c} { | |
| 476 | wr_pick dram_coverage_ifc_dram_clk.dram_Ch${c}_que_pick_wr_first; | |
| 477 | } | |
| 478 | ||
| 479 | ||
| 480 | bind dram_rd_wr_hit_port ${prefix}mcu_rd_wr_hit_sample_bind_Ch${c} { | |
| 481 | rd_wr_hit dram_coverage_ifc_dram_clk.dram_Ch${c}_que_rd_wr_hit; | |
| 482 | } | |
| 483 | ||
| 484 | bind dram_refresh_all_clr_mon_state_port ${prefix}mcu_refresh_all_clr_mon_state_sample_bind_Ch${c} { | |
| 485 | fsm_state dram_coverage_ifc_dram_clk.dram_Ch${c}_refresh_all_clr_mon_state; | |
| 486 | } | |
| 487 | ||
| 488 | bind dram_cas_que_port ${prefix}mcu_cas_que_sample_bind_Ch${c} { | |
| 489 | cas_valid dram_coverage_ifc_dram_clk.dram_Ch${c}_que_cas_valid; | |
| 490 | } | |
| 491 | ||
| 492 | ||
| 493 | bind dram_ras_cas_pend_cnt_port ${prefix}mcu_ras_cas_pend_cnt_sample_bind_Ch${c} { // not necessary for N2 | |
| 494 | ras_cas_pend_cnt { | |
| 495 | dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_pend_cnt, | |
| 496 | dram_coverage_ifc_dram_clk.dram_Ch${c}_cas_pend_cnt | |
| 497 | }; | |
| 498 | } | |
| 499 | bind dram_ras_picked_port ${prefix}mcu_ras_picked_sample_bind_Ch${c} { | |
| 500 | ras_picked dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_picked; | |
| 501 | } | |
| 502 | bind dram_cas_picked_port ${prefix}mcu_cas_picked_sample_bind_Ch${c} { // not necessary for N2 | |
| 503 | cas_picked dram_coverage_ifc_dram_clk.dram_Ch${c}_que_cas_picked; | |
| 504 | } | |
| 505 | ||
| 506 | bind dram_rd_wr_scrb_schmoo_port ${prefix}mcu_rd_wr_scrb_schmoo_sample_bind_Ch${c}_l2b0 { | |
| 507 | rd_wr_scrb_vld { | |
| 508 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req_2a_addr_vld, | |
| 509 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req_2a_addr_vld, | |
| 510 | dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_req_2a_addr_vld | |
| 511 | }; | |
| 512 | } | |
| 513 | bind dram_rd_wr_scrb_schmoo_port ${prefix}mcu_rd_wr_scrb_schmoo_sample_bind_Ch${c}_l2b1 { | |
| 514 | rd_wr_scrb_vld { | |
| 515 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req_2a_addr_vld, | |
| 516 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req_2a_addr_vld, | |
| 517 | dram_coverage_ifc_dram_clk.dram_Ch${c}_scrb_req_2a_addr_vld | |
| 518 | }; | |
| 519 | } | |
| 520 | ||
| 521 | ||
| 522 | // registers { | |
| 523 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_chip_config_reg, | |
| 524 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_mode_reg, | |
| 525 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_rrd_reg, | |
| 526 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_rc_reg, | |
| 527 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_rcd_reg, | |
| 528 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_wtr_dly_reg, | |
| 529 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_rtw_dly_reg, | |
| 530 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_rtp_reg, | |
| 531 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_ras_reg, | |
| 532 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_rp_reg, | |
| 533 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_wr_reg, | |
| 534 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_mrd_reg, | |
| 535 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_iwtr_reg, | |
| 536 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg2, | |
| 537 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg1, | |
| 538 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_ext_mode_reg3, | |
| 539 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_eight_bank_mode, | |
| 540 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_rank1_present, | |
| 541 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_channel_disabled, | |
| 542 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_addr_bank_low_sel, | |
| 543 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_init, | |
| 544 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_data_del_cnt, | |
| 545 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_io_pad_clk_inv, | |
| 546 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_io_ptr_clk_inv, | |
| 547 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wr_mode_reg_done, | |
| 548 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_init_status_reg, | |
| 549 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_dimms_present, | |
| 550 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_fail_over_mode, | |
| 551 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_dram_fail_over_mask, | |
| 552 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_dbg_trig_en, | |
| 553 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_sts_reg, | |
| 554 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_err_inj_reg, | |
| 555 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_sshot_err_reg, | |
| 556 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_err_cnt | |
| 557 | // }; | |
| 558 | //} | |
| 559 | // | |
| 560 | ||
| 561 | bind dram_perf_cntr_port ${prefix}mcu_perf_cntr_sample_bind_Ch${c} { | |
| 562 | perf { | |
| 563 | dram_coverage_ifc_dram_clk.dram_Ch${c}_perf_cntl, | |
| 564 | dram_coverage_ifc_dram_clk.dram_Ch${c}_cnt0_sticky_bit, | |
| 565 | dram_coverage_ifc_dram_clk.dram_Ch${c}_cnt1_sticky_bit | |
| 566 | }; | |
| 567 | } | |
| 568 | ||
| 569 | bind dram_reg_ack_nack_port ${prefix}mcu_reg_ack_nack_sample_bind_Ch${c} { | |
| 570 | ack_nack { | |
| 571 | dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2if_ack_vld, | |
| 572 | dram_coverage_ifc_dram_clk.dram_Ch${c}_que_l2if_nack_vld | |
| 573 | }; | |
| 574 | } | |
| 575 | ||
| 576 | bind dram_rank_stack_addr_param_rd_hi_port ${prefix}mcu_rank_stack_addr_param_rd_hi_sample_bind_Ch${c}_l2b0 { | |
| 577 | addr_etc_info_rd_hi dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_adr_info_hi; | |
| 578 | } | |
| 579 | bind dram_rank_stack_addr_param_rd_hi_port ${prefix}mcu_rank_stack_addr_param_rd_hi_sample_bind_Ch${c}_l2b1 { | |
| 580 | addr_etc_info_rd_hi dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_adr_info_hi; | |
| 581 | } | |
| 582 | bind dram_rank_stack_addr_param_wr_hi_port ${prefix}mcu_rank_stack_addr_param_wr_hi_sample_bind_Ch${c}_l2b0 { | |
| 583 | addr_etc_info_wr_hi dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_adr_info_hi; | |
| 584 | } | |
| 585 | bind dram_rank_stack_addr_param_wr_hi_port ${prefix}mcu_rank_stack_addr_param_wr_hi_sample_bind_Ch${c}_l2b1 { | |
| 586 | addr_etc_info_wr_hi dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_adr_info_hi; | |
| 587 | } | |
| 588 | bind dram_rank_stack_addr_param_rd_lo_port ${prefix}mcu_rank_stack_addr_param_rd_lo_sample_bind_Ch${c}_l2b0 { | |
| 589 | addr_etc_info_rd_lo dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_adr_info_lo; | |
| 590 | } | |
| 591 | bind dram_rank_stack_addr_param_rd_lo_port ${prefix}mcu_rank_stack_addr_param_rd_lo_sample_bind_Ch${c}_l2b1 { | |
| 592 | addr_etc_info_rd_lo dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_adr_info_lo; | |
| 593 | } | |
| 594 | bind dram_rank_stack_addr_param_wr_lo_port ${prefix}mcu_rank_stack_addr_param_wr_lo_sample_bind_Ch${c}_l2b0 { | |
| 595 | addr_etc_info_wr_lo dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_adr_info_lo; | |
| 596 | } | |
| 597 | bind dram_rank_stack_addr_param_wr_lo_port ${prefix}mcu_rank_stack_addr_param_wr_lo_sample_bind_Ch${c}_l2b1 { | |
| 598 | addr_etc_info_wr_lo dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_adr_info_lo; | |
| 599 | } | |
| 600 | // to be binded laterx | |
| 601 | ||
| 602 | // en_n_addr dram_coverage_ifc_dram_clk.dram_Ch${c}_que_mem_addr; | |
| 603 | //} | |
| 604 | . for ( $i = 0; $i < 8; $i++ ) { | |
| 605 | ||
| 606 | bind dram_rd_q_cntr_port ${prefix}mcu_rd_q_cntr${i}_sample_bind_Ch${c}_l2b0 { | |
| 607 | cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_q_cntr_${i}; | |
| 608 | } | |
| 609 | bind dram_rd_q_cntr_port ${prefix}mcu_rd_q_cntr${i}_sample_bind_Ch${c}_l2b1 { | |
| 610 | cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_q_cntr_${i}; | |
| 611 | } | |
| 612 | bind dram_wr_q_cntr_port ${prefix}mcu_wr_q_cntr${i}_sample_bind_Ch${c}_l2b0 { | |
| 613 | cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_q_cntr_${i}; | |
| 614 | } | |
| 615 | bind dram_wr_q_cntr_port ${prefix}mcu_wr_q_cntr${i}_sample_bind_Ch${c}_l2b1 { | |
| 616 | cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_q_cntr_${i}; | |
| 617 | } | |
| 618 | bind dram_rd_req_ack_cntr_port ${prefix}mcu_rd_req_ack_${i}_sample_bind_Ch${c}_l2b0 { | |
| 619 | cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_rd_req_ack_cntr_${i}; | |
| 620 | } | |
| 621 | bind dram_rd_req_ack_cntr_port ${prefix}mcu_rd_req_ack_${i}_sample_bind_Ch${c}_l2b1 { | |
| 622 | cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_rd_req_ack_cntr_${i}; | |
| 623 | } | |
| 624 | .} | |
| 625 | ||
| 626 | bind dram_wr_req_ack_cntr_port ${prefix}mcu_wr_req_ack_sample_bind_Ch${c}_l2b0 { | |
| 627 | cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b0_wr_req_ack_cntr; | |
| 628 | } | |
| 629 | bind dram_wr_req_ack_cntr_port ${prefix}mcu_wr_req_ack_sample_bind_Ch${c}_l2b1 { | |
| 630 | cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_l2b1_wr_req_ack_cntr; | |
| 631 | } | |
| 632 | ||
| 633 | . for ( $ch = 0; $ch < 4; $ch++ ) { | |
| 634 | . for ( $i = 0; $i < 8; $i++ ) { | |
| 635 | bind dram_cs_bank_req_cntr_port ${prefix}mcu_cs${ch}_bank_req_cntr_${i}_sample_bind_Ch${c} { | |
| 636 | cntr dram_coverage_ifc_dram_clk.dram_Ch${c}_cs${ch}_bank_req_cntr_${i}; | |
| 637 | } | |
| 638 | .} | |
| 639 | .} | |
| 640 | ||
| 641 | bind dram_dp_pioson_l2_data_port ${prefix}mcu_dp_pioson_l2_data_sample_bind_Ch${c} { | |
| 642 | dp_pioson_l2_data { dram_coverage_ifc_dram_clk.dram_Ch${c}_dp_pioson_l2_chunk, | |
| 643 | dram_coverage_ifc_dram_clk.dram_Ch${c}_dp_pioson_l2_data | |
| 644 | }; | |
| 645 | } | |
| 646 | ||
| 647 | bind dram_raw_hazard_port ${prefix}mcu_raw_hazard_sample_bind_Ch${c} { | |
| 648 | hazard { | |
| 649 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif0_raw_hazard, | |
| 650 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif1_raw_hazard | |
| 651 | }; | |
| 652 | } | |
| 653 | ||
| 654 | bind dram_refresh_port ${prefix}mcu_refresh_sample_bind_Ch${c} { | |
| 655 | refresh { | |
| 656 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_ref_go, | |
| 657 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_refresh_rank | |
| 658 | }; | |
| 659 | } | |
| 660 | ||
| 661 | bind dram_single_channel_port ${prefix}mcu_single_channel_sample_bind_Ch${c} { | |
| 662 | single_ch { | |
| 663 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbd1_data, | |
| 664 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_single_channel_mode | |
| 665 | }; | |
| 666 | } | |
| 667 | ||
| 668 | bind dram_fbd_fast_reset_port ${prefix}mcu_fbd_fast_reset_sample_bind_Ch${c} { | |
| 669 | fast_reset { | |
| 670 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_fast_reset, | |
| 671 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_fbd_state | |
| 672 | }; | |
| 673 | } | |
| 674 | ||
| 675 | bind dram_fbd_fast_reset_port ${prefix}mcu_fbd_full_reset_sample_bind_Ch${c} { | |
| 676 | fast_reset { | |
| 677 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_fast_reset, | |
| 678 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_fbd_state | |
| 679 | }; | |
| 680 | } | |
| 681 | ||
| 682 | bind dram_fbd_cmd_a_port ${prefix}mcu_fbd_cmd_a_sample_bind_Ch${c} { | |
| 683 | cmd { | |
| 684 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_sync_frame_req, | |
| 685 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_scr_frame_req, | |
| 686 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_cmd_a | |
| 687 | }; | |
| 688 | } | |
| 689 | ||
| 690 | bind dram_fbd_cmd_b_port ${prefix}mcu_fbd_cmd_b_sample_bind_Ch${c} { | |
| 691 | cmd { | |
| 692 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_config_reg_write, | |
| 693 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_config_reg_read, | |
| 694 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_issue_cke_cmd, | |
| 695 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_cmd_b, | |
| 696 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_addr_b | |
| 697 | }; | |
| 698 | } | |
| 699 | ||
| 700 | bind dram_fbd_cmd_c_port ${prefix}mcu_fbd_cmd_c_sample_bind_Ch${c} { | |
| 701 | cmd { | |
| 702 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_config_reg_write, | |
| 703 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_issue_cke_cmd, | |
| 704 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_cmd_c, | |
| 705 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_addr_c | |
| 706 | }; | |
| 707 | } | |
| 708 | ||
| 709 | bind dram_fbd_dimm_cmd_a_port ${prefix}mcu_fbd_dimm_cmd_a_sample_bind_Ch${c} { | |
| 710 | frame { | |
| 711 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_dimm_a, | |
| 712 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_bank_a, | |
| 713 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_rank_a | |
| 714 | }; | |
| 715 | } | |
| 716 | ||
| 717 | bind dram_fbd_dimm_cmd_b_port ${prefix}mcu_fbd_dimm_cmd_b_sample_bind_Ch${c} { | |
| 718 | frame { | |
| 719 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_dimm_b, | |
| 720 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_bank_b, | |
| 721 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_rank_b | |
| 722 | }; | |
| 723 | } | |
| 724 | ||
| 725 | bind dram_fbd_dimm_cmd_c_port ${prefix}mcu_fbd_dimm_cmd_c_sample_bind_Ch${c} { | |
| 726 | frame { | |
| 727 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_dimm_c, | |
| 728 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_bank_c, | |
| 729 | dram_coverage_ifc_dram_clk.dram_Ch${c}_drif_dram_rank_c | |
| 730 | }; | |
| 731 | } | |
| 732 | ||
| 733 | bind dram_fbd_l0s_state_port ${prefix}mcu_fbd_l0s_state_sample_bind_Ch${c} { | |
| 734 | l0sstate { | |
| 735 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l0s_enable, | |
| 736 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l0s_stall | |
| 737 | }; | |
| 738 | } | |
| 739 | ||
| 740 | bind dram_fbd_nb_ts0_port ${prefix}mcu_fbd_nb_ts0_sample_bind_Ch${c} { | |
| 741 | frame { | |
| 742 | dram_coverage_ifc_dram_clk.dram_Ch${c}_ts0_hdr_0, | |
| 743 | dram_coverage_ifc_dram_clk.dram_Ch${c}_ts0_hdr_1 | |
| 744 | }; | |
| 745 | } | |
| 746 | ||
| 747 | bind dram_fbd_nb_stspar_port ${prefix}mcu_fbd_nb_stspar_sample_bind_Ch${c} { | |
| 748 | frame { | |
| 749 | dram_coverage_ifc_dram_clk.dram_Ch${c}_sts_par_0, | |
| 750 | dram_coverage_ifc_dram_clk.dram_Ch${c}_sts_par_1 | |
| 751 | }; | |
| 752 | } | |
| 753 | ||
| 754 | bind dram_fbd_nb_idle_port ${prefix}mcu_fbd_nb_idle_sample_bind_Ch${c} { | |
| 755 | frame { | |
| 756 | dram_coverage_ifc_dram_clk.dram_Ch${c}_idle_0, | |
| 757 | dram_coverage_ifc_dram_clk.dram_Ch${c}_idle_1 | |
| 758 | }; | |
| 759 | } | |
| 760 | ||
| 761 | bind dram_fbd_nb_alrt_port ${prefix}mcu_fbd_nb_alrt_sample_bind_Ch${c} { | |
| 762 | frame { | |
| 763 | dram_coverage_ifc_dram_clk.dram_Ch${c}_alrt_0, | |
| 764 | dram_coverage_ifc_dram_clk.dram_Ch${c}_alrt_1 | |
| 765 | }; | |
| 766 | } | |
| 767 | ||
| 768 | bind dram_fbd_nb_alrt_assrt_port ${prefix}mcu_fbd_nb_alrt_assrt_sample_bind_Ch${c} { | |
| 769 | frame { | |
| 770 | dram_coverage_ifc_dram_clk.dram_Ch${c}_alrt_assrt_0, | |
| 771 | dram_coverage_ifc_dram_clk.dram_Ch${c}_alrt_assrt_1 | |
| 772 | }; | |
| 773 | } | |
| 774 | ||
| 775 | bind dram_fbd_nb_nbde_port ${prefix}mcu_fbd_nb_nbde_sample_bind_Ch${c} { | |
| 776 | frame { | |
| 777 | dram_coverage_ifc_dram_clk.dram_Ch${c}_nbde_0, | |
| 778 | dram_coverage_ifc_dram_clk.dram_Ch${c}_nbde_1 | |
| 779 | }; | |
| 780 | } | |
| 781 | ||
| 782 | bind dram_fbd_sb_port ${prefix}mcu_fbd_sb_frame_sample_bind_Ch${c} { | |
| 783 | frame { | |
| 784 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic_f | |
| 785 | }; | |
| 786 | } | |
| 787 | ||
| 788 | bind dram_failover_port ${prefix}mcu_failover_sample_bind_Ch${c} { | |
| 789 | failover { | |
| 790 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fail_over_mode | |
| 791 | }; | |
| 792 | } | |
| 793 | ||
| 794 | bind dram_fbd0_sb_failover_port ${prefix}mcu_fbd0_sb_failover_sample_bind_Ch${c} { | |
| 795 | failover { | |
| 796 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic0_sb_failover, | |
| 797 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic0_sb_failover_mask | |
| 798 | }; | |
| 799 | } | |
| 800 | ||
| 801 | bind dram_fbd1_sb_failover_port ${prefix}mcu_fbd1_sb_failover_sample_bind_Ch${c} { | |
| 802 | failover { | |
| 803 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic1_sb_failover, | |
| 804 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic1_sb_failover_mask | |
| 805 | }; | |
| 806 | } | |
| 807 | ||
| 808 | bind dram_fbd0_nb_failover_port ${prefix}mcu_fbd0_nb_failover_sample_bind_Ch${c} { | |
| 809 | failover { | |
| 810 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic0_nb_failover, | |
| 811 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic0_nb_failover_mask | |
| 812 | }; | |
| 813 | } | |
| 814 | ||
| 815 | bind dram_fbd1_nb_failover_port ${prefix}mcu_fbd1_nb_failover_sample_bind_Ch${c} { | |
| 816 | failover { | |
| 817 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic1_nb_failover, | |
| 818 | dram_coverage_ifc_dram_clk.dram_Ch${c}_fbdic1_nb_failover_mask | |
| 819 | }; | |
| 820 | } | |
| 821 | ||
| 822 | bind dram_mem_poison_port ${prefix}l2_mcu_intf_mem_poison_sample_bind_Ch${c} { | |
| 823 | ecc { | |
| 824 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_mcu_data_mecc, | |
| 825 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_mcu_data_mecc | |
| 826 | }; | |
| 827 | } | |
| 828 | ||
| 829 | bind dram_wr_mem_poison_port ${prefix}mcu_wr_mem_poison_sample_bind_Ch${c} { | |
| 830 | poison { | |
| 831 | dram_coverage_ifc_dram_clk.dram_Ch${c}_l2poison_qw | |
| 832 | }; | |
| 833 | } | |
| 834 | ||
| 835 | // | |
| 836 | ||
| 837 | // line_cov { dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_addr_cnt0, | |
| 838 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_addr_cnt1, | |
| 839 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr0_load_cas2, | |
| 840 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr0_load, | |
| 841 | // dram_coverage_ifc_dram_clk.dram_Ch${c}_que_wl_data_addr1_load | |
| 842 | // }; | |
| 843 | //} | |
| 844 | ||
| 845 | ||
| 846 | ||
| 847 | ||
| 848 | // rd_wr_l2if { | |
| 849 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_req, | |
| 850 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_dummy_req, | |
| 851 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_rd_ack, | |
| 852 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_wr_req, | |
| 853 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_wr_ack, | |
| 854 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_data_vld, | |
| 855 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b0_rd_val, //not in N2 | |
| 856 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b1_rd_val, // not in N2 | |
| 857 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_b0_wr_val, | |
| 858 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_b1_wr_val | |
| 859 | // | |
| 860 | // | |
| 861 | // //dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_wr_b0_data_addr | |
| 862 | // | |
| 863 | // }; | |
| 864 | // } | |
| 865 | ||
| 866 | // rd_wr_l2if { | |
| 867 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_req, | |
| 868 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_dummy_req, | |
| 869 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_rd_ack, | |
| 870 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_wr_req, | |
| 871 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_wr_ack, | |
| 872 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_data_vld, | |
| 873 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b0_rd_val, // not in N2 | |
| 874 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_b1_rd_val, // not in N2 | |
| 875 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_b0_wr_val, | |
| 876 | // dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_b1_wr_val | |
| 877 | // //dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_wr_b0_data_addr | |
| 878 | // | |
| 879 | // }; | |
| 880 | // } | |
| 881 | // | |
| 882 | ||
| 883 | bind dram_err_l2if_port ${prefix}l2_mcu_intf_err_sample_bind_Ch${c}_l2b0 { | |
| 884 | secc_pa_mecc_scb_secc_mecc { | |
| 885 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_secc_err, | |
| 886 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_pa_err, | |
| 887 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_mecc_err, | |
| 888 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_scb_secc_err, | |
| 889 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_dram_sctag_scb_mecc_err | |
| 890 | }; | |
| 891 | } | |
| 892 | bind dram_err_l2if_port ${prefix}l2_mcu_intf_err_sample_bind_Ch${c}_l2b1 { | |
| 893 | secc_pa_mecc_scb_secc_mecc { | |
| 894 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_secc_err, | |
| 895 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_pa_err, | |
| 896 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_mecc_err, | |
| 897 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_scb_secc_err, | |
| 898 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_dram_sctag_scb_mecc_err | |
| 899 | }; | |
| 900 | } | |
| 901 | bind dram_l2if_data_ret_fifo_port ${prefix}mcu_l2if_data_ret_fifo_en_sample_bind_Ch${c} { | |
| 902 | fifo_en dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_data_ret_fifo_en; | |
| 903 | } | |
| 904 | ||
| 905 | bind dram_err_sts_port ${prefix}mcu_err_sts_sample_bind_Ch${c}_l2b0 { | |
| 906 | err_en_n_sts { | |
| 907 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_scrb_val_d2, | |
| 908 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_secc_err, | |
| 909 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_mecc_err_partial, | |
| 910 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_l2if_pa_err, | |
| 911 | dram_coverage_ifc_core_clk.dram_Ch${c}_err_sts_reg, | |
| 912 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en6, | |
| 913 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en5, | |
| 914 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en4, | |
| 915 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en3, | |
| 916 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en2, | |
| 917 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en1, | |
| 918 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en0, | |
| 919 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en , | |
| 920 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_addr_reg_en, | |
| 921 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_secc_loc_en | |
| 922 | }; | |
| 923 | } | |
| 924 | bind dram_err_sts_port ${prefix}mcu_err_sts_sample_bind_Ch${c}_l2b1 { | |
| 925 | err_en_n_sts { | |
| 926 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_scrb_val_d2, | |
| 927 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_secc_err, | |
| 928 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_mecc_err_partial, | |
| 929 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_l2if_pa_err, | |
| 930 | dram_coverage_ifc_core_clk.dram_Ch${c}_err_sts_reg, | |
| 931 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en6, | |
| 932 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en5, | |
| 933 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en4, | |
| 934 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en3, | |
| 935 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en2, | |
| 936 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en1, | |
| 937 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en0, | |
| 938 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_sts_reg_en , | |
| 939 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_err_addr_reg_en, | |
| 940 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_secc_loc_en | |
| 941 | }; | |
| 942 | } | |
| 943 | ||
| 944 | bind dram_wr_data_mem_sample ${prefix}l2_mcu_intf_wr_data_mem_sample_bind_Ch${c}_l2b0 { | |
| 945 | en_n_addr { dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_cpu_wr_en, | |
| 946 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_cpu_wr_addr | |
| 947 | }; | |
| 948 | } | |
| 949 | bind dram_wr_data_mem_sample ${prefix}l2_mcu_intf_wr_data_mem_sample_bind_Ch${c}_l2b1 { | |
| 950 | en_n_addr { dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_cpu_wr_en, | |
| 951 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_cpu_wr_addr | |
| 952 | }; | |
| 953 | } | |
| 954 | ||
| 955 | bind dram_wr_data_rd_mem_sample ${prefix}mcu_wr_data_rd_mem_sample_bind_Ch${c}_l2b0 { | |
| 956 | en_n_addr { dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_wdq_rd_en, | |
| 957 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_wdq_radr | |
| 958 | }; | |
| 959 | } | |
| 960 | bind dram_wr_data_rd_mem_sample ${prefix}mcu_wr_data_rd_mem_sample_bind_Ch${c}_l2b1 { | |
| 961 | en_n_addr { dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_wdq_rd_en, | |
| 962 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_wdq_radr | |
| 963 | }; | |
| 964 | } | |
| 965 | ||
| 966 | ||
| 967 | bind dram_rd_sync_port ${prefix}l2_mcu_intf_rd_sync_schmoo_sample_bind_Ch${c}_l2b0 { | |
| 968 | rd_sync { | |
| 969 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_rd_req, | |
| 970 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_clspine_dram_txrd_sync | |
| 971 | }; | |
| 972 | } | |
| 973 | bind dram_rd_sync_port ${prefix}l2_mcu_intf_rd_sync_schmoo_sample_bind_Ch${c}_l2b1 { | |
| 974 | rd_sync { | |
| 975 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_rd_req, | |
| 976 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_clspine_dram_txrd_sync | |
| 977 | }; | |
| 978 | } | |
| 979 | ||
| 980 | bind dram_wr_sync_port ${prefix}l2_mcu_intf_wr_sync_schmoo_sample_bind_Ch${c}_l2b0 { | |
| 981 | wr_sync { | |
| 982 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_sctag_dram_wr_req, | |
| 983 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b0_clspine_dram_txwr_sync | |
| 984 | }; | |
| 985 | } | |
| 986 | bind dram_wr_sync_port ${prefix}l2_mcu_intf_wr_sync_schmoo_sample_bind_Ch${c}_l2b1 { | |
| 987 | wr_sync { | |
| 988 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_sctag_dram_wr_req, | |
| 989 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2b1_clspine_dram_txwr_sync | |
| 990 | }; | |
| 991 | } | |
| 992 | ||
| 993 | bind dram_err_intr_ucb_trig_port1 ${prefix}mcu_err_intr_ucb_trig1_sample_bind_Ch${c} { | |
| 994 | err_intr_ucb_trig1 { | |
| 995 | dram_coverage_ifc_core_clk.dram_Ch${c}_l2if_ucb_trig | |
| 996 | }; | |
| 997 | } | |
| 998 | ||
| 999 | ||
| 1000 | ||
| 1001 | bind dram_dbg_wr_req_port ${prefix}mcu_dbg_wr_req_sample_bind_Ch${c} { | |
| 1002 | dbgwr { | |
| 1003 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_wrreq_in_0, | |
| 1004 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_wrreq_in_1, | |
| 1005 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_wrreq_out | |
| 1006 | }; | |
| 1007 | } | |
| 1008 | ||
| 1009 | ||
| 1010 | bind dram_dbg_rd_req_port ${prefix}mcu_dbg_rd_req_sample_bind_Ch${c} { | |
| 1011 | dbgrd { | |
| 1012 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_rdreq_in_0, | |
| 1013 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_rdreq_in_1, | |
| 1014 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_rdreq_out | |
| 1015 | }; | |
| 1016 | } | |
| 1017 | ||
| 1018 | ||
| 1019 | bind dram_dbg_err_port ${prefix}mcu_dbg_err_sample_bind_Ch${c} { | |
| 1020 | dbgerr { | |
| 1021 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_ucb_serdes_dtm, | |
| 1022 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_mecc_err, | |
| 1023 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_secc_err, | |
| 1024 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_fbd_err, | |
| 1025 | dram_coverage_ifc_jbus_clk.dram_Ch${c}_dbg1_err_mode, | |
| 1026 | dram_coverage_ifc_core_clk.dram_Ch0_dbg1_crc21, | |
| 1027 | dram_coverage_ifc_core_clk.dram_Ch0_dbg1_err_event | |
| 1028 | }; | |
| 1029 | } | |
| 1030 | ||
| 1031 | . | |
| 1032 | . } # coreBindings | |
| 1033 | . | |
| 1034 | ||
| 1035 | bind dram_ucb_etc_port ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch0 { | |
| 1036 | ucb_etc { | |
| 1037 | dram_coverage_ifc_jbus_clk.dram_Ch0_rd_req_vld, | |
| 1038 | dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_req_pend, | |
| 1039 | dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_dram_ack_busy, | |
| 1040 | dram_coverage_ifc_jbus_clk.dram_Ch0_ucb_dram_int_busy | |
| 1041 | }; | |
| 1042 | } | |
| 1043 | ||
| 1044 | bind dram_ucb_etc_port ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch1 { | |
| 1045 | ucb_etc { | |
| 1046 | dram_coverage_ifc_jbus_clk.dram_Ch1_rd_req_vld, | |
| 1047 | dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_req_pend, | |
| 1048 | dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_dram_ack_busy, | |
| 1049 | dram_coverage_ifc_jbus_clk.dram_Ch1_ucb_dram_int_busy | |
| 1050 | }; | |
| 1051 | } | |
| 1052 | ||
| 1053 | bind dram_ucb_etc_port ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch2 { | |
| 1054 | ucb_etc { | |
| 1055 | dram_coverage_ifc_jbus_clk.dram_Ch2_rd_req_vld, | |
| 1056 | dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_req_pend, | |
| 1057 | dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_dram_ack_busy, | |
| 1058 | dram_coverage_ifc_jbus_clk.dram_Ch2_ucb_dram_int_busy | |
| 1059 | }; | |
| 1060 | } | |
| 1061 | ||
| 1062 | bind dram_ucb_etc_port ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch3 { | |
| 1063 | ucb_etc { | |
| 1064 | dram_coverage_ifc_jbus_clk.dram_Ch3_rd_req_vld, | |
| 1065 | dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_req_pend, | |
| 1066 | dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_dram_ack_busy, | |
| 1067 | dram_coverage_ifc_jbus_clk.dram_Ch3_ucb_dram_int_busy | |
| 1068 | }; | |
| 1069 | } | |
| 1070 | ||
| 1071 | bind dram_mcu_ncu_intf_port ${prefix}mcu_ncu_intf_sample_bind_Ch0 { | |
| 1072 | intr { | |
| 1073 | dram_coverage_ifc_jbus_clk.dram_Ch0_mcu_ncu_ecc, | |
| 1074 | dram_coverage_ifc_jbus_clk.dram_Ch0_mcu_ncu_fbr | |
| 1075 | }; | |
| 1076 | } | |
| 1077 | ||
| 1078 | bind dram_mcu_ncu_intf_port ${prefix}mcu_ncu_intf_sample_bind_Ch1 { | |
| 1079 | intr { | |
| 1080 | dram_coverage_ifc_jbus_clk.dram_Ch1_mcu_ncu_ecc, | |
| 1081 | dram_coverage_ifc_jbus_clk.dram_Ch1_mcu_ncu_fbr | |
| 1082 | }; | |
| 1083 | } | |
| 1084 | ||
| 1085 | bind dram_mcu_ncu_intf_port ${prefix}mcu_ncu_intf_sample_bind_Ch2 { | |
| 1086 | intr { | |
| 1087 | dram_coverage_ifc_jbus_clk.dram_Ch2_mcu_ncu_ecc, | |
| 1088 | dram_coverage_ifc_jbus_clk.dram_Ch2_mcu_ncu_fbr | |
| 1089 | }; | |
| 1090 | } | |
| 1091 | ||
| 1092 | bind dram_mcu_ncu_intf_port ${prefix}mcu_ncu_intf_sample_bind_Ch3 { | |
| 1093 | intr { | |
| 1094 | dram_coverage_ifc_jbus_clk.dram_Ch3_mcu_ncu_ecc, | |
| 1095 | dram_coverage_ifc_jbus_clk.dram_Ch3_mcu_ncu_fbr | |
| 1096 | }; | |
| 1097 | } | |
| 1098 | ||
| 1099 | bind dram_pt_refresh_blk_bank ${prefix}mcu_pt_refresh_blk_bank_sample_bind_Ch0 { | |
| 1100 | pt_refresh_blk_bank { | |
| 1101 | dram_coverage_ifc_dram_clk.dram_Ch0_pt_selfrsh, | |
| 1102 | dram_coverage_ifc_dram_clk.dram_Ch0_pt_blk_new_openbank_d1 | |
| 1103 | }; | |
| 1104 | } | |
| 1105 | bind dram_pt_refresh_blk_bank ${prefix}mcu_pt_refresh_blk_bank_sample_bind_Ch1 { | |
| 1106 | pt_refresh_blk_bank { | |
| 1107 | dram_coverage_ifc_dram_clk.dram_Ch1_pt_selfrsh, | |
| 1108 | dram_coverage_ifc_dram_clk.dram_Ch1_pt_blk_new_openbank_d1 | |
| 1109 | }; | |
| 1110 | } | |
| 1111 | bind dram_pt_refresh_blk_bank ${prefix}mcu_pt_refresh_blk_bank_sample_bind_Ch2 { | |
| 1112 | pt_refresh_blk_bank { | |
| 1113 | dram_coverage_ifc_dram_clk.dram_Ch2_pt_selfrsh, | |
| 1114 | dram_coverage_ifc_dram_clk.dram_Ch2_pt_blk_new_openbank_d1 | |
| 1115 | }; | |
| 1116 | } | |
| 1117 | bind dram_pt_refresh_blk_bank ${prefix}mcu_pt_refresh_blk_bank_sample_bind_Ch3 { | |
| 1118 | pt_refresh_blk_bank { | |
| 1119 | dram_coverage_ifc_dram_clk.dram_Ch3_pt_selfrsh, | |
| 1120 | dram_coverage_ifc_dram_clk.dram_Ch3_pt_blk_new_openbank_d1 | |
| 1121 | }; | |
| 1122 | } | |
| 1123 | ||
| 1124 | // *********************************************************** | |
| 1125 | // Declare bindings for each core | |
| 1126 | // *********************************************************** | |
| 1127 | ||
| 1128 | . foreach $dr (@DRC_STR) { | |
| 1129 | . &coreBindings( $dr ); | |
| 1130 | . } | |
| 1131 | ||
| 1132 | #endif |